SAMSUNG S3C9688

S3C9688/P9688
1
PRODUCT OVERVIEW
PRODUCT OVERVIEW
SAM88RCRI PRODUCT FAMILY
Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated
peripherals, and various mask-programmable ROM sizes.
A dual address/data bus architecture and a large number of bit- or nibble-configurable I/O ports provide a flexible programming environment for
applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time
operations. Many SAM88RCRI microcontrollers have an external interface that provides access to external memory and other peripheral
devices.
S3C9688/P9688 MICROCONTROLLER
The S3C9688/P9688 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built around the powerful
SAM88RCRI CPU core.
Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register space, the size of the internal
register file was logically expanded. The S3C9688 has 8 K bytes of program
memory on-chip.
Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core:
—
Five configurable I/O ports (32 pins)
—
20 bit-programmable pins for external interrupts
—
8-bit timer/counter with three operating modes
—
Low speed USB function
The S3C9688/P9688 is a versatile microcontroller that can be used in a wide range of low speed USB support general purpose applications. It
is especially suitable for use as a keyboard controller and is available in a 42-pin SDIP and a 44-pin QFP package.
OTP
The S3C9688/P9688 microcontroller is also available in OTP (One Time Programmable) version, S3P9688. S3P9688 microcontroller has an
on-chip 8-Kbyte one-time-programmable EPROM instead of masked ROM. The S3P9688 is comparable to S3C9688/P9688, both in function
and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C9688/P9688
FEATURES
•
CPU
•
programmable oscillation stabilization interval generation
SAM88RCRI CPU core
function
•
Memory
•
8 K byte internal program memory (ROM)
•
208 byte RAM
One 8-bit basic timer for watchdog function and
One 8-bit timer/counter with Compare/Overflow
USB Serial Bus
•
Compatible to USB low speed (1.5 Mbps) device 2.0
specification.
Instruction Set
•
41 instructions
•
IDLE and STOP instructions added for power-down modes
•
1 Control endpoint and 2 Interrupt endpoint
•
Serial bus interface engine (SIE)
—
Packet decoding/generation
Instruction Execution Time
—
CRC generation and checking
•
—
NRZI encoding/decoding and bit-stuffing
0.66 µs at 6 MHz fOSC
•
8 bytes each receive/transmit USB buffer
Interrupts
•
•
29 interrupt sources with one vector, each source has its
Low Voltage Reset
pending bit
•
Low voltage detect for RESET
One level, one vector interrupt structure
•
Power on Reset
Oscillation Circuit
Operating Temperature Range
•
6 MHz crystal/ceramic oscillator
•
•
External clock source (6 MHz)
•
Embedded oscillation capacitor (XI, XO, 33pF)
– 40 ° C to + 85 ° C
Operating Voltage Range
•
4.0 V to 5.25 V
General I/O
•
Package Types
Bit programmable five I/O ports (34 pins total)
—
(D+/PS2, D-/PS2 Included)
Timer/Counter
1-2
•
42-pin SDIP
•
44-pin QFP
S3C9688/P9688
PRODUCT OVERVIEW
BLOCK DIAGRAM
P0.0-P0.7/INT2
P1.0-P1.7
Port 0
P2.0-P2.7/INT0
Port 1
Port 2
SAM88RCRI Bus
P3.0
X IN
Main
P3.1
OSC
X OUT
Port 3
I/O Port and Interrupt Control
P3.2
P3.3/CLO
Basic
Timer
P4.0/INT1
P4.1/INT1
Port 4
P4.2/INT1
P4.3/INT1
SAM88RCRI CPU
LVR
D+/PS2
USB
D-/PS2
3.3 V OUT
Timer
4 K/8KB ROM
208-Byte
Register File
40 bytes
USB
Buffer
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C9688/P9688
PIN ASSIGNMENTS
P3.1
1
42
P3.2
P3.0
2
41
P3.3/CLO
INT0/P2.0
3
40
D+/PS2
INT0/P2.1
4
39
D-/PS2
INT0/P2.2
5
38
3.3V
INT0/P2.3
6
37
NC
INT0/P2.4
7
36
P0.0/INT2
INT0/P2.5
8
35
P0.1/INT2
INT0/P2.6
9
34
P0.2/INT2
INT0/P2.7
10
33
P0.3/INT2
32
P0.4/INT2
S3C9688/P9688
(42-SDIP)
V DD
11
V SS
12
31
P0.5/INT2
X OUT
13
30
P0.6/INT2
X IN
14
P0.7/INT2
15
29
28
INT1/P4.0
16
27
P1.1
INT1/P4.1
17
26
P1.2
RESET
18
25
P1.3
INT1/P4.2
19
24
P1.4
INT1/P4.3
20
23
P1.5
21
22
P1.6
TEST
P1.7
P1.0
Figure 1-2. Pin Assignment Diagram (42-Pin SDIP Package)
1-4
OUT
PRODUCT OVERVIEW
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
P0.0/INT2
P0.1/INT2
P0.2/INT2
P0.3/INT2
P0.4/INT2
P0.5/INT2
P0.6/INT2
P0.7/INT2
S3C9688/P9688
3.3V
34
22
P1.0
D- /PS2
D+/PS2
35
21
P1.1
36
20
P1.2
CLO/P3.3
37
19
18
P1.3
P1.4
44-QFP
17
P1.5
(Top View)
16
OUT
P3.2
38
P3.1
39
P3.0
40
S3C9688/P9688
41
15
P1.6
P1.7
P2.1/INT0
42
14
P4.3/INT1
P2.2/INT0
43
13
P4.2/INT1
P2.3/INT0
44
12
RESET
INT0/P2.4
INT0/P2.5
INT0/P2.6
INT0/P2.7
V DD
V SS
X OUT
X IN
TEST
INT1/P4.0
INT1/P4.1
1
2
3
4
5
6
7
8
9
10
11
P2.0/INT0
NOTE:
The TEST pin must connect to V
SS
(GND) in the normal operation mode.
Figure 1-3. Pin Assignment Diagram (44-Pin QFP Package)
1-5
PRODUCT OVERVIEW
S3C9688/P9688
PIN DESCRIPTIONS
Table 1-1. S3C9688/P9688 Pin Descriptions
Pin Names
P0.0–P0.7
Pin
Pin
Circuit
Pin
Share
Type
Description
Number
Numbers
Pins
36–29
INT2
I/O
Bit-programmable I/O port for Schmitt trigger input or open-
B
drain output. Port0 can be individually configured as external
(30–23)
interrupt inputs. Pull-up resistors are assignable by software.
P1.0–P1.7
I/O
Bit-programmable I/O port for Schmitt trigger input or open-
B
drain output. Pull-up resistors are assignable by software.
P2.0–P2.7
I/O
Bit-programmable I/O port for Schmitt trigger input or open-
28–21
–
(22–15)
B
drain output. Port2 can be individually configured as external
3–10
INT0
(41–44, 1–4)
interrupt inputs. Pull-up resistors are assignable by software.
P3.0–P3.3
I/O
Bit-programmable I/O port for Schmitt trigger input, open-
C
drain or push -pull output. P3.3 can be used to system clock
2, 1, 42, 41
P3.3/CLO
(40–37)
output (CLO) pin.
P4.0–P4.3
I/O
Bit-programmable I/O port for Schmitt trigger input or open-
D
drain output or push -pull output. Port4 can be individually
16, 17, 19, 20
INT1
(10, 11, 13, 14)
configured as external interrupt inputs. In output mode, pullup resistors are assignable by software. But in input mode,
pull-up resistors are fixed.
D+/PS2 D-
I/O
Programmable port for
/PS2
USB interface
–
or PS2 interface.
40–39
–
(36–35)
3.3 V OUT
–
3.3 V output from internal voltage regulator
–
38 (34)
–
X IN, XOUT
–
System clock input and output pin (crystal/ceramic oscillator,
–
14, 13
–
or external clock source)
INT0
I
(8, 7)
External interrupt for bit-programmable port0, port2 and port4
INT1
–
pins when set to input mode.
INT2
3-10, 16,17, 19,
PORT2/
20, 29-36
PORT4/
(30-23, 41-44, 1-
PORT0
4, 10, 11, 13, 14)
RESET
I
RESET signal input pin. Input with internal pull-up resistor.
A
18 (12)
–
TEST
I
Test signal input pin (for factory use only; connected to VSS)
–
15 (9)
–
V DD
–
Power input pin
–
11 (5)
–
V SS
–
Ground input pin
–
12, (6)
–
NC
–
No connection
–
37 (31,32, 33)
–
NOTE :
Pin numbers shown in parenthesis '( )' are for the 44-QFP package; others are for the 42-SDIP package.
PIN CIRCUITS DIAGRAMS
Table 1-2. Pin Circuit Assignments for the S3C9688/P9688
1-6
Circuit Number
Circuit Type
S3C9688/P9688 Assignments
A
I
B
I/O
Ports 0, 1, and 2
C
I/O
Port 3
D
I/O
Port 4
RESET signal input
S3C9688/P9688
PRODUCT OVERVIEW
V DD
Pull-up
Resistor
Noise
Filter
Figure 1-4. Pin Circuit Type A (RESET)
V DD
Pull-up
Resistor
Pull-up Enable
Output Disable
I/O
Open Data
Input Data
V SS
D0
MUX
Mode
D1
Input Data
Output
D0
Input
D1
Figure 1-5. Pin Circuit Type B (Ports 0, 1 and 2)
1-7
PRODUCT OVERVIEW
S3C9688/P9688
V DD
Output Data
Open Drain
I/O
Output
Disable
V SS
Input Data
D0
MUX
D1
Mode
Input Data
Output
D0
Input
D1
Figure 1-6. Pin Circuit Type C (Port 3)
V DD
Pull-up
Resistor
Pull-up Enable
V DD
Output Data
Open Drain
I/O
Output
Disable
V SS
Input Data
D0
MUX
D1
Mode
Input Data
Output
D0
Input
D1
Figure 1-7. Pin Circuit Type D (Port 4)
1-8
S3C9688/P9688
PRODUCT OVERVIEW
APPLICATION CIRCUIT
5V
5V
V DD
0
Port 0
Port 3
1
2
Port 1
3
X IN
15
X OUT
S3C9688/P9688
0
Port 2
1
RESET
2
3
DP
O
7
D+/PS2
DM
D-/PS2
Port 4
H
S
T
KEYBOARD
MATRIX
V SS1
NOTE:
Port4 can use expend keyboard MATRIX.
D+/PS2, D-/PS2 can use PS2 keyboard interface (see PS2CONINT, page 4-34).
Port 4.2, 4.3 can use PS2 mouse interface.
Port 3 can use LED direct drive.
Figure 1-8. Keyboard Application Circuit Diagram
1-9
PRODUCT OVERVIEW
S3C9688/P9688
NOTES
1-10
S3C9688/P9688
2
ADDRESS SPACES
ADDRESS SPACES
OVERVIEW
The S3C9688/P9688 microcontroller has two kinds of address space:
—
Program memory (ROM), internal
—
Internal register file
A 1 3 -b i t a d d r e s s b u s s u p p o r t s b o t h p r o g r a m m e m o r y . A s e p a r a t e 8 -b i t r e g i s t e r b u s c a r r i e s a d d r e s s e s a n d d a t a
between the CPU and the internal register file.
T h e S 3 C 9 6 8 8 h a s 8 K b y t e s o f m a s k -p r o g r a m m a b l e p r o g r a m m e m o r y o n -c h i p . T h e r e i s o n e p r o g r a m m e m o r y
configuration option:
—
Internal ROM mode, in which only the 8 K byte internal program memory is used.
T h e S 3 C 9 6 8 8 / P 9 6 8 8 m i c r o c o n t r o l l e r h a s 2 0 8 g e n e r a l-p u r p o s e r e g i s t e r s i n i t s i n t e r n a l r e g i s t e r f i l e . T w e n t y -s e v e n
bytes in the register file are mapped for system and peripheral control functions.
2 -1
ADDRESS SAPCES
S3C9 6 8 8 / P 9 6 8 8
PROGRAM MEMORY (ROM)
Normal Operating Mode (Internal ROM)
T h e S 3 C 9 6 8 8 / P 9 6 8 8 h a s 8 K b y t e s ( l o c a t i o n s 0 H – 1 F F F H ) o f i n t e r n a l m a s k -p r o g r a m m a b l e p r o g r a m m e m o r y .
The first 2 bytes of the ROM (0000H– 0001H) are an interrupt vector address.
The program reset address in the ROM is 0100H.
(DECIMAL)
(HEX)
8,191
1FFFH (S3C9688/P9688)
8 K byte Internal
Program Memory
Area
4,095
0FFFH
4-Kbyte Internal
Program Memory
Area
256
Program Start
2
1
0
0100H
0002H
Interrupt Vector
0001H
0000H
F i g u r e 2 -1 . P r o g r a m M e m o r y A d d r e s s S p a c e
2 -2
S3C9688/P9688
ADDRESS SPACES
REGISTER ARCHITECTURE
The upper 64 by tes of the S3C9688/P9688's internal register file are addressed as working registers, system control
registers and peripheral control registers. The lower 192 bytes of internal register file (00H– BFH) is called the general
purpose register space. The total addressable register space is thereby 256 bytes. 233 registers in this space can
b e a c c e s s e d . ; 2 0 8 a r e a v a i l a b l e f o r g e n e r a l-p u r p o s e u s e .
For many SAM88RCRI microcontrollers, the addressable area of the internal register file is further expanded by the
additional of one or more register pages at general purpose register space (00H– BFH). This register file expansion is
not implemented in the S3C9688/P9688, however. Page addressing is controlled by the System Mode Register
(SYM.1–SYM.0).
The specific register types and the area (in bytes) that they occupy in the internal register file are summarized in
T a b l e 2 -1 .
T a b l e 2 -1 . R e g i s t e r T y p e S u m m a r y
Register Type
Number of Bytes
CPU and system control registers
11
P eripheral, I/O, and clock control and data registers
34
G e n e r a l-p u r p o s e r e g i s t e r s ( i n c l u d i n g t h e 1 6 -b i t c o m m o n w o r k i n g r e g i s t e r a r e a )
208
Total Addressable Bytes
253
2 -3
ADDRESS SAPCES
S3C9 6 8 8 / P 9 6 8 8
FFH
Peripheral Control
Register
E0H
DFH
D0H
CFH
System Control
Registers
64 Bytes of
Common Area
Working Register
C0H
BFH
General Purpose
Register File
and Stack Area
192 Bytes
00H
F i g u r e 2 -2 . I n t e r n a l R e g i s t e r F i l e O r g a n i z a t i o n
2 -4
S3C9688/P9688
ADDRESS SPACES
C O M M O N W O R K I N G R E G I S T E R A R E A ( C 0 H –C F H )
The SAM88RCRI register architecture provides an efficient method of working register addressing that takes full
advantage of shorter instruction form ats to reduce execution time.
T h i s 1 6 -b y t e a d d r e s s r a n g e i s c a l l e d c o m m o n a r e a . T h a t i s , l o c a t i o n s i n t h i s a r e a c a n b e u s e d a s w o r k i n g r e g i s t e r s
by operations that address any location on any page in the register file. Typically, these working registers serve as
temporary buffers for data operations between different pages. However, because the S3C9688/P9688 uses only
page 0, you can use the common area for any internal data operation.
The Register (R) addressing mode can be used to access this area
R e g i s te r s a r e a d d r e s s e d e i t h e r a s a s i n g l e 8 -b i t r e g i s t e r o r a s a p a i r e d 1 6 -b i t r e g i s t e r . I n 1 6 -b i t r e g i s t e r p a i r s , t h e
a d d r e s s o f t h e f i r s t 8 -b i t r e g i s t e r i s a l w a y s a n e v e n n u m b e r a n d t h e a d d r e s s o f t h e n e x t r e g i s t e r i s a n o d d n u m b e r .
T h e m o s t s i g n i f i c a n t b y t e o f t h e 1 6 -b i t d a t a i s a l w a y s s t o r e d i n t h e e v e n -n u m b e r e d r e g i s t e r ; t h e l e a s t s i g n i f i c a n t b y t e
i s a l w a y s s t o r e d i n t h e n e x t ( + 1 ) o d d -n u m b e r e d r e g i s t e r .
MSB
LSB
Rn
Rn+1
n = Even Address
F i g u r e 2 -3 . 1 6 -B i t R e g i s t e r P a i r s
F
PROGRAMMING TIP — Addressing the Common Working Register Area
As the following examples show, you should access working registers in the common area, locations C0H– CFH,
using working register addressing mode only.
Examples:
1.
LD
0C2H,40H
;
Invalid addressing mode!
Use working register addressing instead:
2.
LD
R2,40H
;
R2 (C2H) ¨ the value in location 40H
ADD
0C3H,#45H
;
Invalid addressing mode!
U s e w o r k i n g r e g is t e r a d d r e s s i n g i n s t e a d :
ADD
R3,#45H
;
R3 (C3H) ¨ R3 + 45H
2 -5
ADDRESS SAPCES
S3C9 6 8 8 / P 9 6 8 8
SYSTEM STACK
S 3 C 9 -s e r i e s m i c r o c o n t r o l l e r s u s e t h e s y s t e m s t a c k f o r s t o r i n g d a t a i n s u b r o u t i n e c a l l a n d r e t u r n . T h e P U S H a n d
POP instructions are used to control system stack operations. The S3C9688/P9688 architecture supports stack
operations in the internal register file.
Stack Operations
Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are
saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of
the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their
original locations. The stack address is always decremented before a push operation and incremented after a pop
operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure
2 -4 .
High Address
PCL
PCL
Top of
PCH
PCH
Top of
Stack
FLAGS
Stack
Stack Contents
After a Call
Stack Contents
Low Address
Instruction
After an
Interrupt
F i g u r e 2 -4 . S t a c k O p e r a t i o n s
Stack Pointer (SP)
R e g i s t e r l o c a t i o n D 9 H c o n t a i n s t h e 8 -b i t s t a c k p o i n t e r ( S P ) t h a t i s u s e d f o r s y s t e m s t a c k o p e r a t i o n s . A f t e r a r e s e t ,
the SP value is undetermined.
B e c a u s e o n l y i n t e r n a l m e m o r y s p a c e i s i m p l e m e n t e d i n t h e S 3 C 9 6 8 8 / P 9 6 8 8 , t h e S P m u s t b e i n i t i a l i z e d t o a n 8 -b i t
value in the range 00H– B F H .
NOTE
In case a Stack Pointer is initialized to 00H, it is decreased to FFH when stack operation starts. This means
that a Stack Pointer access invalid stack area.
2 -6
S3C9688/P9688
F
ADDRESS SPACES
PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP
The following example shows you how to perform stack operations in the internal register file using PUSH and POP
instructions:
LD
SP,#0C0H
;
SP ¨ C0H (Normally, the SP is set to 0C0H by the
;
initialization routine)
•
•
•
PUSH
SYM
;
Stack address 0BFH ¨ SYM
PUSH
CLKCON
;
S t a c k a d d r e s s 0 B E H ¨ C L K CO N
PUSH
20H
;
Stack address 0BDH ¨ 20H
PUSH
R3
;
Stack address 0BCH ¨ R3
POP
R3
;
R3 ¨ Stack address 0BCH
POP
20H
;
20H ¨ Stack address 0BDH
POP
CLKCON
;
CLKCON ¨ Stack address 0BEH
POP
SYM
;
SYM ¨ Stack address 0BFH
•
•
•
2 -7
ADDRESS SAPCES
S3C9 6 8 8 / P 9 6 8 8
NOTES
2 -8
S3C9688/P9688
3
ADDRESSING MODES
ADDRESSING MODES
OVERVIEW
Instructions that are stored in program memory are fetched for execution using the program counter. Instructions
indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to
determine the location of the data operand. The operands specified in SAM88RCRI instructions may be condition
codes, immediate data, or a location in the register file, program memory, or data memory.
The SAM88RCRI instruction set supports six explicit addressing modes. Not all of these addressing modes are
available for each instruction. The addressing modes and their symbols are as follows:
—
Register (R)
—
Indirect Register (IR)
—
Indexed (X)
—
Direct Address (D A )
—
Relative Address (RA)
—
Immediate (IM)
3 -1
ADDRESSING MODES
S3C9688/P9688
REGISTER ADDRESSING MODE (R)
I n R e g i s t e r a d d r e s s i n g m o d e , t h e o p e r a n d i s t h e c o n t e n t o f a s p e c i f i e d r e g i s t e r ( s e e F i g u r e 3 -1 ) . W o r k i n g r e g i s t e r
a d d r e s s i n g d i f f e r s f r o m R e g i s t e r a d d r e s s i n g b e c a u s e i t u s e s a n 1 6 -b y t e w o r k i n g r e g i s t e r s p a c e i n t h e r e g i s t e r f i l e a n d
a n 4 -b i t r e g i s t e r w i t h i n t h a t s p a c e ( s e e F i g u r e 3 -2).
Program Memory
Register File
8-Bit Register
File Address
dst
OPERAND
OPCODE
Point to One
Rigister in Register
One-Operand
File
Instruction
Value used in
(Example)
Instruction Execution
Sample Instruction:
DEC
CNTR
;
Where CNTR is the label of an 8-bit register address
F i g u r e 3 -1 . R e g i s t e r A d d r e s s i n g
Register File
CFH
Program Memory
4-Bit
Working Register
dst
src
4 LSBs
OPERAND
Point to the
OPCODE
Woking Register
Two-Operand
(1 of 16)
Instruction
(Example)
Sample Instruction:
ADD
R1, R2
;
Where R1 = C1H and R2 = C2H
F i g u r e 3 -2 . W o r k i n g R e g i s t e r A d d r e s s i n g
3 -2
C0H
S3C9688/P9688
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (IR)
In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the
operand. Depending on the instruction used, the actual address may point to a register in the register file, to program
m e m o r y ( R O M ) , o r t o a n e x t e r n a l m e m o r y s p a c e ( s e e F i g u r e s 3 -3 t h r o u g h 3 -6 ) .
Y o u c a n u s e a n y 8 -b i t r e g i s t e r t o i n d i r e c t l y a d d r e s s a n o t h e r r e g i s t e r . A n y 1 6 -b i t r e g i s t e r p a i r c a n b e u s e d t o i n d i r e c t l y
address another memory location.
Program Memory
Register File
8-Bit Register
File Address
dst
OPCODE
One-Operand
ADDRESS
Point to One
Rigister in Register
File
Instruction
(Example)
Address of Operand
used by Instruction
Value used in
OPERAND
Instruction Execution
Sample Instruction:
RL
@SHIFT
;
Where SHIFT is the label of an 8-Bit register address
F i g u r e 3 -3 . I n d i r e c t R e g i s t e r A d d r e s s i n g t o R e g i s t e r F i l e
3 -3
ADDRESSING MODES
S3C9688/P9688
I N D I R E C T R E G I S T E R A D D R E S S I N G M O D E ( C o n t i n u e d)
Register File
Program Memory
REGISTER
Example
dst
Instruction
References
OPCODE
PAIR
Points to
Rigister Pair
Program
16-Bit
Memory
Address
Points to
Program Memory
Program
Memory
Sample Instructions:
Value used in
OPERAND
Instruction
CALL
@RR2
JP
@RR2
F i g u r e 3 -4 . I n d i r e c t R e g i s t e r A d d r e s s i n g t o P r o g r a m M e m o r y
3 -4
S3C9688/P9688
ADDRESSING MODES
I N D I R E C T R E G I S T E R A D D R E S S I N G M O D E ( C o n t i n u e d)
Register File
CFH
Program Memory
4-Bit
Working
Register
Address
4 LSBs
dst
OPCODE
src
OPERAND
Point to the
Woking Register
C0H
(1 of 16)
Sample Instruction:
Value used in
OR
R6, @R2
OPERAND
Instruction
F i g u r e 3 -5 . I n d i r e c t W o r k i n g R e g i s t e r A d d r e s s i n g t o R e g i s t e r F i l e
3 -5
ADDRESSING MODES
S3C9688/P9688
I N D I R E C T R E G I S T E R A D D R E S S I N G M O D E ( C o n c l u d e d)
Register File
CFH
Program Memory
4-Bit Working
Register Address
dst
OPCODE
src
Register
Next 3-Bits Point
Pair
to Working
Example Instruction
Register Pair
References either
(1 of 8)
Program Memory or
C0H
16-Bit
address
Data Memory
points to
LSB Selects
Program Memory
or
Data Memory
program
memory
or data
memory
Value used in
Instruction
OPERAND
Sample Instructions:
LCD
R5,@RR2
LDE
R3,@RR14 ; External data memory access
; Program memory access
LDE
@RR4, R8 ; External data memory access
F i g u r e 3 -6 . I n d i r e c t W o r k i n g R e g i s t e r A d d r e s s i n g t o P r o g r a m o r D a t a M e m o r y
3 -6
S3C9688/P9688
ADDRESSING MODES
INDEXED ADDRESSING M ODE (X)
Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate
t h e e f f e c t i v e o p e r a n d a d d r e s s ( s e e F i g u r e 3 -7 ) . Y o u c a n u s e I n d e x e d a d d r e s s i n g m o d e t o a c c e s s l o c a t i o n s i n t h e
internal register file or in external memory.
I n s h o r t o f f s e t I n d e x e d a d d r e s s i n g m o d e , t h e 8 -b i t d i s p l a c e m e n t i s t r e a t e d a s a s i g n e d i n t e g e r i n t h e r a n g e
– 1 2 8 t o + 1 2 7 . T h i s a p p l i e s t o e x t e r n a l m e m o r y a c c e s s e s o n l y ( s e e F i g u r e 3 -8).
F o r r e g i s t e r f i l e a d d r e s s i n g , a n 8 -b i t b a s e a d d r e s s p r o v i d e d b y t h e i n s t r u c t i o n i s a d d e d t o a n 8 -b i t o f f s e t c o n t a i n e d i n
a working register. For external memory accesses, the base address is stored in the working register pair
d e s i g n a t e d i n t h e i n s t r u c t i o n . T h e 8 -b i t o r 1 6 -b i t o f f s e t g i v e n i n t h e i n s t r u c t i o n i s t h e n a d d e d t o t h e b a s e a d d r e s s ( s e e
F i g u r e 3 -9 ) .
Th e o n l y i n s t r u c t i o n t h a t s u p p o r t s I n d e x e d a d d r e s s i n g m o d e f o r t h e i n t e r n a l r e g i s t e r f i l e i s t h e L o a d i n s t r u c t i o n ( L D ) .
The LDC and LDE instructions support Indexed addressing mode for internal program memory, external program
memory, and for external data memory, when implemented.
Register File
~
~
Value used in
Instruction
OPERAND
+
Program Memory
~
~
X (OFFSET)
Two-Operand
Instruction
Example
dst
OPCODE
src
4 LSBs
INDEX
Point to One of the
Woking Register
(1 of 16)
Sample Instruction:
LD
R0, #BASE[R1] ; Where BASE is an 8-bit immediate value
F i g u r e 3 -7 . I n d e x e d A d d r e s s i n g t o R e g i s t e r F i l e
3 -7
ADDRESSING MODES
S3C9688/P9688
I N D E X E D A D D R E S S I N G M O D E ( C o n t i n u e d)
Program Memory
Register File
XS (OFFSET)
4-Bit Working
Register Address
dst
NEXT 3-Bit
src
OPCODE
Register
Point to Working
Pair
Register Pair
16-Bit
(1 of 8)
address
added to
offset
LSB Selects
+
8-Bit
16-Bit
Program Memory
or
Datamemory
OPERAND
16-Bit
Value used in
Instruction
Sample Instructions:
LDC
R4, #04H[RR2] ; The values in the program address (RR2 + #04H)
LDE
R4,#04H[RR2]
are loaded into register R4.
; Identical operation to LDC example, except that
external program memory is accessed.
F i g u r e 3 -8 . I n d e x e d A d d r e s s i n g t o P r o g r a m o r D a t a M e m o r y w i t h S h o r t O f f s e t
3 -8
S3C9688/P9688
ADDRESSING MODES
I N D E X E D A D D R E S S I N G M O D E ( C o n c l u d e d)
Program Memory
Register File
XL H (OFFSET)
XL L (OFFSET)
4-Bit Working
Register Address
dst
Register
NEXT 3-Bit
Pair
src
OPCODE
Point to Working
16-Bit
Register Pair
address
(1 of 8)
added to
offset
LSB Selects
+
16-Bit
16-Bit
Program Memory
or
Datamemory
OPERAND
16-Bit
Value used in
Instruction
Sample Instructions:
LDC
R4, #1000H[RR2]
; The values in the program address (RR2 + #1000H)
LDE
R4,#1000H[RR2]
; Identical operation to LDC example, except that
are loaded into register R4.
external program memory is accessed.
F i g u r e 3 -9 . I n d e x e d A d d r e s s i n g t o P r o g r a m o r D a t a M e m o r y w i t h L o n g O f f s e t
3 -9
ADDRESSING MODES
S3C9688/P9688
DIRECT ADDRESS MODE (DA)
I n D i r e c t A d d r e s s ( D A ) m o d e , t h e i n s t r u c t i o n p r o v i d e s t h e o p e r a n d ' s 1 6 -b i t m e m o r y a d d r e s s . J u m p ( J P ) a n d C a l l
( C A L L ) i n s t r u c t i o n s u s e t h i s a d d r e s s i n g m o d e t o s p e c i f y t h e 1 6 -b i t d e s t i n a t i o n a d d r e s s t h a t i s l o a d e d i n t o t h e P C
whenever a JP or CALL instruction is executed.
The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load
operations to program memory (LDC) or to external data memory (LDE), if implemented.
Program or
Data Memory
Memory
Program Memory
Address
Used
Upper Address Byte
Lower Address Byte
dst/src
"0" or "1"
OPCODE
LSB Selects Program
Memory or Data Memory:
"0" = Program Memory
"1" = Data Memory
Sample Instructions:
LDC
R5,1234H ;
The values in the program address (1234H)
LDE
R5,1234H ;
Identical operation to LDC example, except that
are loaded into register R5.
external program memory is accessed.
F i g u r e 3 -1 0 . D i r e c t A d d r e s s i n g f o r L o a d I n s t r u c t i o n s
3 -1 0
S3C9688/P9688
ADDRESSING MODES
D I R E C T A D D R E S S M O D E (C o n t i n u e d)
Program Memory
Next OPCODE
Program
Memory
Address
Used
Upper Address Byte
Lower Address Byte
OPCODE
Sample Instructions:
JP
C,JOB1
;
Where JOB1 is a 16-Bit immediate address
CALL
DISPLAY
;
Where DISPLAY is a 16-Bit immediate address
F i g u r e 3 -1 1 . D i r e c t A d d r e s s i n g f o r C a l l a n d J u m p I n s t r u c t i o n s
3 -1 1
ADDRESSING MODES
S3C9688/P9688
RELATIVE ADDRESS MODE (RA)
I n R e l a t i v e A d d r e s s ( R A ) m o d e , a t w o ' s -c o m p l e m e n t s i g n e d d i s p l a c e m e n t b e t w e e n – 1 2 8 a n d + 1 2 7 i s s p e c i f i e d i n
t h e i n s t r u c t i o n . T h e d i s p l a c em e n t v a l u e i s t h e n a d d e d t o t h e c u r r e n t P C v a l u e . T h e r e s u l t i s t h e a d d r e s s o f t h e n e x t
instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately
following the current instruction.
The instructions that support RA addressing is JR.
Program Memory
Next OPCODE
Program Memory
Address Used
Current
PC Value
Displacement
OPCODE
Current Instruction
+
Signed
Displacement Value
Sample Instructions:
JR
ULT,$+OFFSET
; Where OFFSET is a value in the range +127 to -128
F i g u r e 3 -1 2 . R e l a t i v e A d d r e s s i n g
IMMEDIATE MODE (IM)
In Immediate (IM) addressing mode, the operand value used in the in struction is the value supplied in the operand
field itself. Immediate addressing mode is useful for loading constant values into registers.
Program Memory
OPERAND
OPCODE
(The Operand value is in the instruction)
Sample Instruction:LD
R0,#0AAH
F i g u r e 3 -1 3 . I m m e d i a t e A d d r e s s i n g
3 -1 2
S3C9688/P9688
4
CONTROL REGISTERS
CONTROL REGISTERS
OVERVIEW
I n t h i s s e c t i o n , d e t a i l e d d e s c r i p t i o n s o f t h e S 3 C 9 6 8 8 / P 9 6 8 8 c o n t r o l r e g i s t e r s a r e p r e s e n t e d i n a n e a s y -t o -r e a d f o r m a t .
These descriptions will help you to familiarize yourself with the mapped locations in the register file. You can also
u s e t h e m a s a q u i c k -r e f e r e n c e s o u r c e w h e n w r i t i n g a p p l i c a t i o n p r o g r a m s .
S y s t e m a n d p e r i p h e r a l r e g i s t e r s a r e s u m m a r i z e d i n T a b l e 4 -1 . F i g u r e 4 -1 i l l u s t r a t e s t h e i m p o r t a n t f e a t u r e s o f t h e
standard register description format.
Control register descriptions are arranged in alphabetical order according to register mnemonic. More information
about control registers is presented in the context of the various peripheral hardware descriptions in Part II of this
manual.
4-1
CONTROL REGISTERS
S3C9688/P9688
T a b l e 4 -1 . S y s t e m a n d P e r i p h e r a l c o n t r o l R e g i s t e r s
Register Name
Mnemonic
Decimal
Hex
R/W
T0CNT
208
D0H
R
Timer 0 data register
T0DATA
209
D1H
R/W
Timer 0 control register
T0CON
210
D2H
R/W
USXCON
211
D3H
R/W
Clock control register
CLKCON
212
D4H
R/W
System flags register
FLAGS
213
D5H
R/W
P S2DATA
214
D6H
R/W
PS2CONINT
215
D7H
R/W
P0INT
216
D8H
R/W
SP
217
D9H
R/W
P0PND
218
DAH
R/W
Timer 0 counter register
USB selection and Transceiver crossover point
control register
D + / P S 2 , D -/ P S 2 d a t a r e g i s t e r
(Only PS2 Mode)
PS2 control and interrupt pending register
Port 0 interrupt control register
Stack pointer
Port 0 interrupt pending register
Location DBH is not mapped.
Basic timer control register
BTCON
220
DCH
R/W
Basic timer counter register
BTCNT
221
DDH
R
SYM
223
DFH
R/W
Port 0 data register
P0
224
E0H
R/W
Port 1 data register
P1
225
E1H
R/W
Port 2 data register
P2
226
E2H
R/W
Port 3 data register
P3
227
E3H
R/W
Port 4 data register
P4
228
E4H
R/W
P3CON
229
E5H
R/W
Port 0 control register (high byte)
P0CONH
230
E6H
R/W
Port 0 control register (low byte)
P0CONL
231
E7H
R/W
Port 1 control register (high byte)
P1CONH
232
E8H
R/W
Port 1 control register (low byte)
P1CONL
233
E9H
R/W
Port 2 control register (high byte)
P2CONH
234
EAH
R/W
Port 2 control register (low byte)
P2CONL
235
EBH
R/W
Port 2 interrupt control register
P2INT
236
ECH
R/W
Port 2 interrupt pending register
P2PND
237
EDH
R/W
Port 4 control register
P4CON
238
EEH
R/W
P4INTPND
239
EFH
R/W
Location DEH is not mapped.
System mode register
Port 3 control register
Port 4 interrupt enable/pending register
4 -2
S3C9688/P9688
CONTROL REGISTERS
4 -3
CONTROL REGISTERS
S3C9688/P9688
T a b l e 4 -1 . S y s t e m a n d P e r i p h e r a l c o n t r o l R e g i s t e r s ( C o n t i n u e d )
Register Name
Mnemonic
Decimal
Hex
R/W
FADDR
240
F0H
R/W
Control endpoint status register
EP0CSR
241
F1H
R/W
Interrupt endpoint 1 control status register
EP1CSR
242
F2H
R/W
Control endpoin t byte count register
EP0BCNT
243
F3H
R/W
Control endpoint FIFO register
EP0FIFO
244
F4H
R/W
Interrupt endpoint 1 FIFO register
EP1FIFO
245
F5H
R/W
USB interrupt pending register
USBPND
246
F6H
R/W
USBINT
247
F7H
R/W
PWRMGR
248
F8H
R/W
Interrupt endpoint 2 control status register
EP2CSR
249
F9H
R/W
Interrupt endpoint 2 FIFO register
EP2FIFO
250
FAH
R/W
Endpoint mode register
EPMODE
251
FBH
R/W
Endpoint 1 byte count
EP1BCNT
252
FCH
R/W
Endpoint 2 byte count
EP2BCNT
253
FDH
R/W
USB control register
USBCON
254
FEH
R/W
USB function address register
USB interrupt enable register
USB power management register
Location FFH is not mapped.
4 -4
S3C9688/P9688
CONTROL REGISTERS
Bit number(s) that is/are appended to the
register name for bit addressing
Name of individual
Register
Register address
bit or bit function
(hexadecimal)
Full Register name
mnemonic
D5H
FLAGS - System Flags Register
.7
Bit Identifier
RESET Value
Read/Write
.7
.6
.5
.4
.3
.2
.1
.0
x
x
x
x
x
x
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Carry Flag (C)
.6
0
Operation dose not generate a carry or borrow condition
1
Operation generates carry-out or borrow into high-order bit7
Zero Flag
.5
0
Operation result is a non-zero value
1
Operation result is zero
Sign Flag
0
Operation generates positive number (MSB = "0")
1
Operation generates negative number (MSB = "1")
R = Read-only
Description of the
RESET value notation:
W = Write-only
effect of specific
'-' = Not used
R/W = Read/write
bit settings
'x' = Undetermind value
' - ' = Not used
Addressing mode or
'0' = Logic zero
'1' = Logic one
Bit number:
modes you can use to
MSB = Bit 7
modify register values
LSB = Bit 0
F i g u r e 4 -1 . R e g i s t e r D e s c r i p t i o n F o r m a t
4 -5
CONTROL REGISTERS
BTCON
S3C9688/P9688
— Basic Timer Control Register
DCH
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
. 7 -. 4
Watchdog Timer Enable Bits
1
0
1
0
Any other value
.3 and .2
.1
.0
NOTE:
Enable watchdog function
Basic Timer Input Clock Selection Bits
0
0
f
0
1
f
1
0
f
1
1
Invalid setting
OSC
OSC
OSC
/4096
/1024
/128
B a s i c T i m e r C o u n t e r C l e a r B i t (note)
0
No effect
1
Clear BTCNT
B a s i c T i m e r D i v i d e r C l e a r B i t (note)
0
No effect
1
Clear both dividers
When you write a "1" to BTCON.0 (or BTCON.1), the basic timer counter (or basic timer divider) is cleared. The bit
is then cleared automatically to "0".
4 -6
Disable watchdog function
S3C9688/P9688
CLKCON
CONTROL REGISTERS
— System Clock Control Register
D4H
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
–
–
0
0
–
–
–
Read/Write
R/W
–
–
R/W
R/W
–
–
–
.7
O s c i l l a t o r I R Q W a k e -u p F u n c t i o n B i t
0
E n a b l e I R Q f o r m a i n s y s t e m o s c i l l a t o r w a k e-u p i n p o w e r d o w n m o d e
1
D i s a b l e I R Q f o r m a i n s y s t e m o s c i l l a t o r w a k e-u p i n p o w e r d o w n m o d e
.6 and .5
Not used for S3C9688/P9688
.4 and .3
C P U C l o c k ( S y s t e m C l o c k ) S e l e c t i o n B i t s (1)
. 2 –. 0
0
0
Divide by 16 (f
0
1
Divide by 8 (f
1
0
Divide by 2 (f
1
1
N o n -d i v i d e d c l o c k ( f
OSC
OSC
OSC
/16)
/8)
/2)
OSC
)
(2)
Not used for S3C9688/P9688
NOTES :
1.
After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the
2.
appropriate values to CLKCON.3 and CLKCON.4.
f OSC means oscillator frequency.
4 -7
CONTROL REGISTERS
EP0BCNT
S3C9688/P9688
— Endpoint 0 Write Counter Register
F3H
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R/W
R
R
R
R
.7
.6
.5
.4
. 3 –. 0
4 -8
Data_Toggle_Check Bit
0
DATA0 transaction toggle
1
DATA1 transaction toggle
Setup_transa ction Bit
0
Not setup transaction
1
Setup transaction
RCV_Over_8_BYTE Bit
0
Normal Operation
1
Indicates over 8 bytes received
Enable Bit
0
Disable Endpoint 0
1
Enable Endpoint 0
The Byte counter of Data that stored in Endpoint 0
0000
Minimum bytes stored in Endpoint 0
1000
Maximum bytes stored in Endpoint 0
S3C9688/P9688
EP0CSR
CONTROL REGISTERS
— Control Endpoint 0 Status Register
F1H
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
.6
.5
.4
.3
.2
.1
.0
Setup Transfer End Clear Bit
0
No effect (when write)
1
To clear SETUP_ TRANSFER_ END bit
Out Packet Ready Clear Bit
0
No effect (when write)
1
To clear OUT_PKT_RDY bit
Sending Stall Bit
0
No effect (when write)
1
To send STALL signal
Setup Transfer End Bit
0
No effect (when write)
1
SIE sets this bit when a control transfer ends before DATA_END (bit3) is set
Setup Data End Bit
0
No effect (when write)
1
MCU set this bit after loading or unloading the last packet data into the FIFO
Sent Stall Bit
0
MCU clear this bit to end the STALL condition
1
SIE sets this bit if a control transaction is ended due to a protocol violation
In Packet Ready Bit
0
SIE clear this bit once the packet has been successfully sent to the host
1
MCU sets this bit after writing a packet of data into ENDPOINT0 FIFO
Out Packet Ready Bit
0
No effect (when write)
1
SIE sets this bit once a valid token is written to the FIFO
4 -9
CONTROL REGISTERS
4 -1 0
S3C9688/P9688
S3C9688/P9688
EP0FIFO
CONTROL REGISTERS
— Endpoint 0 FIFO Address Register
F4H
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
. 7 –. 0
Endpoint 0 FIFO
T h i s r e g i s t e r i s b i-d i r e c t i o n a l 8 -b y t e d e p t h F I F O u s e d t o t r a n s f e r c o n t r o l E n d p o i n t 0
data.
4 -1 1
CONTROL REGISTERS
EP1BCNT
S3C9688/P9688
— Endpoint 1 Write Counter Register
FCH
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
–
0
0
0
0
0
0
Read/Write
R
–
R
R/W
R
R
R
R
.7
Data_Toggle_Check Bit
0
DATA0 transaction toggle
1
DATA1 transaction toggle
.6
Reserved
.5
RCV_Over_8_BYTE Bit
.4
. 3 –. 0
4 -1 2
0
Normal Operation
1
Indicates over 8 bytes received
Enable Bit
0
Disable Endpoint 1
1
Enable Endpoint 1
The Byte counter of Data that stored in Endpoint 1
0000
Minimum bytes stored in Endpoint 1
1000
Maximum bytes stored in Endpoint 1
S3C9688/P9688
EP1CSR
CONTROL REGISTERS
— Control Endpoint 1 Status Register
F2H
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
a) The bellows are configured as IN mode
.7
Data Toggle Sequence Clear Bit
0
No effect (when write)
1
MCU sets this bit to clear the data toggle sequence bit. The data toggle is
initialized to DATA0.
. 6 –. 3
Maximum Packet Size Bits
0
No effect (when write)
1
These bits indicate the maximum packet size for IN endpoint, and needs to be
updated by the MCU before it sets IN_PKT_RDY. Once set, the contents are
v a l i d t i l l M C U r e -w r i t e s t h e m .
.2
FIFO Flush Bit
0
No effect (when write)
1
When MCU writes a one to this register, the FIFO is flushed, and IN_PKT_RDY
cleared. The MCU should wait for IN_PKT_RDY to be cleared for the flush to take
place.
.1
Force STALL Bit
0
No effect (when write)
1
MCU writes a 1 to this register to issue a STALL handshake to USB. MCU clears
this bit, to end the STALL condition.
.0
In Packet Ready Bit
0
SIE clear this bit once the packet has been successfully sent to the host
1
MCU sets this bit, after writing a packet of data into ENDPOINT1 FIFO. USB
clears this bit, once the packet has been successfully sent to the host. An
interrupt is generated when USB clears this bit, so MCU can load the next
packet.
4 -1 3
CONTROL REGISTERS
EP1CSR
S3C9688/P9688
— Control Endpoint 1 Status Register
F2H
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
–
0
–
–
0
0
0
0
Read/Write
–
R/W
–
–
R/W
R/W
R/W
R/W
b) The bellows are configured as OUT mode
.7
Reserved
.6
CLR_OUT_PKT_RDY Bit
0
No effect (when write)
1
Clear OUT_PKT_RDY (bit 0) bit..
. 5 –. 4
Reserved
.3
RCV_STALL_SIG Bit
.2
.1
.0
4 -1 4
0
MCU can clear this bit
1
SIE sets this bit after sending stall packet
FLUSH_FIFO Bit
0
No effect (when write)
1
FIFO is flushed, and OUT_PKT_RDY bit is cleared..
FORCE_STALL Bit
0
MCU clears this bit to end the STALL condition
1
Issues a STALL handshake to USB
OUT_Packet Ready Bit
0
No effect (when write)
1
SIE sets this bit once a valid token is written to the FIFO
S3C9688/P9688
EP1FIFO
CONTROL REGISTERS
— Endpoint 1 FIFO Address Register
F5H
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
. 7 –. 0
Endpoint 1 FIFO
T h i s r e g i s t e r i s b i-d i r e c t i o n a l 8 -b y t e d e p t h F I F O u s e d t o t r a n s f e r c o n t r o l E n d p o i n t 1
data.
4 -1 5
CONTROL REGISTERS
EP2BCNT
S3C9688/P9688
— Endpoint 2 Write Counter Register
FDH
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
–
0
0
0
0
0
0
Read/Write
R
–
R
R/W
R
R
R
R
.7
Data_Toggle_Check Bit
0
DATA0 transaction toggle
1
DATA1 transaction toggle
.6
Reserved
.5
RCV_Over_8_BYTE Bit
.4
. 3 –. 0
4 -1 6
0
Normal Operation
1
Indicates over 8 bytes received
Enable Bit
0
Disable Endpoint 2
1
Enable Endpoint 2
The Byte counter of Data that stored in Endpoint 2
0000
Minimum bytes stored in Endpoint 2
1000
Maximum bytes stored in Endpoint 2
S3C9688/P9688
EP2CSR
CONTROL REGISTERS
— Control Endpoint 2 Status Register
F9H
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
a) The bellows are configured as IN mode
.7
Data Toggle Sequence Clear Bit
0
No effect (when write)
1
MCU sets this bit to clear the data toggle sequence bit. The data toggle is
initialized to DATA0.
. 6 –. 3
Maximum Packet Size Bits
0
No effect (when write)
1
These bits indicate the maximum packet size for IN endpoint, and needs to be
updated by the MCU before it sets IN_PKT_RDY. Once set, the contents are
v a l i d t i l l M C U r e -w r i t e s t h e m .
.2
FIFO Flush Bit
0
No effect (when write)
1
When MCU writes a one to this register, the FIFO is flushed, and IN_PKT_RDY
cleared. The MCU should wait for IN_PKT_RDY to be cleared for the flush to take
place.
.1
Force STALL Bit
0
No effect (when write)
1
MCU writes a 1 to this register to issue a STALL handshake to USB. MCU clears
this bit, to end the STALL condition.
.0
In Packet Ready Bit
0
SIE clear this bit once the packet has been successfully sent to the host
1
MCU sets this bit, after writing a packet of data into ENDPOINT 2 FIFO. USB
clears this bit, once the packet has been successfully sent to the host. An
interrupt is generated when USB clears this bit, so MCU can load the next
packet.
4 -1 7
CONTROL REGISTERS
EP2CSR
S3C9688/P9688
— Control Endpoint 2 Status Register
F9H
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
–
0
–
–
0
0
0
0
Read/Write
–
R/W
–
–
R/W
R/W
R/W
R/W
b) The bellows are configured a s O U T m o d e
.7
Reserved
.6
CLR_OUT_PKT_RDY Bit
0
No effect (when write)
1
Clear OUT_PKT_RDY (bit 0) bit..
. 5 –. 4
Reserved
.3
RCV_STALL_SIG Bit
.2
.1
.0
4 -1 8
0
MCU can clear this bit
1
SIE sets this bit after sending stall packet
FLUSH_FIFO Bit
0
No effect (when write)
1
FIFO is flushed, and OUT_PKT_RDY bit is cleared..
FORCE_STALL Bit
0
MCU clears this bit to end the STALL condition
1
Issues a STALL handshake to USB
OUT_Packet Ready Bit
0
No effect (when write)
1
SIE sets this bit once a valid token is written to the FIFO
S3C9688/P9688
EP2FIFO
CONTROL REGISTERS
— Endpoint 2 FIFO Address Register
FAH
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
. 7 –. 0
Endpoint 2 FIFO
T h i s r e g i s t e r i s b i-d i r e c t i o n a l 8 -b y t e d e p t h F I F O u s e d t o t r a n s f e r c o n t r o l E n d p o i n t 2
data.
4 -1 9
CONTROL REGISTERS
EPMODE
S3C9688/P9688
— Endpoint Mode Register
FBH
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
–
–
0
0
0
0
Read/Write
R/W
R/W
–
–
R/W
R/W
R/W
R/W
.7 and .6
Reset Length Selection Bits
0
0
20.954us
0
1
10.476us
1
0
5.236us
1
1
2.664us
. 5 –. 4
Not used for C9688/P9688
.3
Chip Test Mode : User must not set this bit.
.2
.1
.0
4 -2 0
0
Normal mode
1
Test mode
Output Enable Mode
0
Enhanced mode
1
Normal mode
Endpoint 2 Mode
0
Endpoint 2 acts as IN interrupt endpoint
1
Endpoint 2 acts as an OUT interrupt endpoint
Endpoint 1 Mode
0
Endpoint 1 acts as an IN interrupt endpoint
1
Endpoint 1 acts as an OUT interrupt endpoint
S3C9688/P9688
FADDR
CONTROL REGISTERS
— USB Function Address Register
F0H
.B i t I d e n t i f i e r
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
This register bit is used as test mode or special purpose mode, so user should set
zero value,
. 6 –. 0
FADDR
This register holds the USB address assigned by the host computer. FADDR is
located at address F0H and is read/write addressable.
4 -2 1
CONTROL REGISTERS
FLAGS
S3C9688/P9688
— System Flags Register
D5H
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
–
–
–
–
Read/Write
R/W
R/W
R/W
R/W
–
–
–
–
.7
Carry Flag (C)
0
.6
.5
.4
. 3 –. 0
4 -2 2
Operation does not generate a carry or borrow condition
Zero Flag (Z)
0
O p e r a t i o n r e s u l t i s a n o n -z e r o v a l u e
1
Operation result is zero
Sign Flag (S)
0
Operation generates a positive number (MSB = "0")
1
Operation generates a negative number (MSB = "1")
Overflow Flag (V)
0
Operation result is ≤ +127 or ≥ – 128
1
Operation result is ≥ +127 or ≤ – 128
Not used for S3C9688/P9688
S3C9688/P9688
P0CONH
CONTROL REGISTERS
— Port 0 Control Register (High Byte)
E6H
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7 and .6
.5 and .4
.3 and .2
.1 and .0
Port 0, P0.7 Configuration Bits
0
0
Schmitt trigger input, rising edge external interrupt
0
1
S c h m i t t t r i g g e r i n p u t , f a l l i n g e d g e e x t e r n a l i n t e r r u p t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
Port 0, P0.6 Configuration Bits
0
0
Schmitt trigger input, rising edge external interrupt
0
1
S c h m i t t t r i g g e r i n p u t , f a l l i n g e d g e e x t e r n a l i n t e r r u p t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
Port 0, P0.5 Configuration Bits
0
0
Schmitt trigger input, rising edge external interrupt
0
1
S c h m i t t t r i g g e r i n p u t , f a ll i n g e d g e e x t e r n a l i n t e r r u p t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
Port 0, P0.4 Configuration Bits
0
0
Schmitt trigger input, rising edge external interrupt
0
1
S c h m i t t t r i g g e r i n p u t , f a l l i n g e d g e e x t e r n a l i n t e r r u p t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
4 -2 3
CONTROL REGISTERS
P0CONL
S3C9688/P9688
— Port 0 Control Register (Low Byte)
E7H
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
R e a d/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7 and .6
.5 and .4
.3 and .2
.1 and .0
4 -2 4
Port 0, P0.3 Configuration Bits
0
0
Schmitt trigger input, rising edge external interrupt
0
1
S c h m i t t t r i g g e r i n p u t , f a l l i n g e d g e e x t e r n a l i n t e r r u p t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
Port 0, P0.2 Configuration Bits
0
0
Schmitt trigger input, rising edge external interrupt
0
1
S c h m i t t t r i g g e r i n p u t , f a l l i n g e d g e e x t e r n a l i n t e r r u p t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
Port 0, P0.1 Configuration Bits
0
0
Schmitt trigger input, rising edge external interrupt
0
1
S c h m i t t t r i g g e r i n p u t , f a l l i n g e d g e e x t e r n a l i n t e r r u p t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
Port 0, P0.0 Configuration Bits
0
0
Schmitt trigger input, rising edge external interrupt
0
1
S c h m i t t t r i g g e r i n p u t , f a l l i n g e d g e e x t e r n a l i n t e r r u p t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
S3C9688/P9688
P0INT
CONTROL REGISTERS
— Port 0 Interrupt Control Register
D8H
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
.6
.5
.4
.3
.2
.1
.0
P0.7 Configuration Bits
0
External interrupt disable
1
External interrupt enable
P0.6 Configuration Bits
0
External interrupt disable
1
External interrupt enable
P0.5 Configuration Bits
0
External interrupt dis able
1
External interrupt enable
P0.4 Configuration Bits
0
External interrupt disable
1
External interrupt enable
P0.3 Configuration Bits
0
External interrupt disable
1
External interrupt enable
P0.2 Configuration Bits
0
External interrupt disable
1
External interrupt enable
P0.1 Configuration Bits
0
External interrupt disable
1
External interrupt enable
P0.0 Configuration Bits
0
External interrupt disable
1
External interrupt enable
4 -2 5
CONTROL REGISTERS
4 -2 6
S3C9688/P9688
S3C9688/P9688
P0PND
CONTROL REGISTERS
— P o r t 0 I n te r r u p t P e n d i n g R e g i s t e r
DAH
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R e a d / W r i t e (NOTE)
.7
.6
.5
.4
.3
.2
.1
.0
P0.7 Interrupt Pending Bit
0
No pending (when read)/clear pending bit (when write)
1
Pending (when read)/no effect (when write)
P0.6 Interrupt Pending Bit
0
No pending (when read)/clear pending bit (when write)
1
Pending (when read)/no effect (when write)
P0.5 Interrupt Pending Bit
0
No pending (when read)/clear pending bit (when write)
1
Pending (when read)/no effect (when write)
P0.4 Interrupt Pending Bit
0
No pending (when read)/clear pending bit (when write)
1
Pending (when read)/no effect (when write)
P0.3 Interrupt Pending Bit
0
No pending (when read)/clear pending bit (when write)
1
Pending (when read)/no effect (when write)
P0.2 Interrupt Pending Bit
0
No pending (when read)/clear pending bit (when write)
1
Pending (when read)/no effect (when w rite)
P0.1 Interrupt Pending Bit
0
No pending (when read)/clear pending bit (when write)
1
Pending (when read)/no effect (when write)
P0.0 Interrupt Pending Bit
0
No pending (when read)/clear pending bit (when write)
1
Pending (when read)/no effect (when write)
4 -2 7
CONTROL REGISTERS
4 -2 8
S3C9688/P9688
S3C9688/P9688
P1CONH
CONTROL REGISTERS
— Port 1 Control Register (High Byte)
E8H
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
. 7 a n d .6
.5 and .4
.3 and .2
.1 and .0
Port 1, P1.7 Configuration Bits
0
0
Schmitt trigger input
0
1
S c h m i t t t r i g g e r i n p u t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
Port 1, P1.6 Configuration Bits
0
0
Schmitt trigger input
0
1
S c h m i t t t r i g g e r i n p u t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
Port 1, P1.5 Configuration Bits
0
0
Schmitt trigger input
0
1
S c h m i t t t r i g g e r i n p u t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
Port 1, P1.4 Configuration Bits
0
0
Schmitt trigger input
0
1
S c h m i t t t r i g g e r i n p u t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
4 -2 9
CONTROL REGISTERS
P1CONL
S3C9688/P9688
— Port 1 Control Register (Low Byte)
E9H
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7 and .6
.5 and .4
.3 and .2
.1 and .0
4 -3 0
Port 1, P1.3 Configuration Bits
0
0
Schmitt trigger input
0
1
S c h m i t t t r i g g e r i n p u t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
Port 1, P1.2 Configuration Bits
0
0
Schmitt trigger input
0
1
S c h m i t t t r i g g e r i n p u t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
Port 1, P1.1 Configuration Bits
0
0
Schmitt trigger input
0
1
S c h m i t t t r i g g e r i n p u t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
Port 1, P1.0 Configuration Bits
0
0
Schmitt trigger input
0
1
S c h m i t t t r i g g e r i n p u t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
S3C9688/P9688
P2CONH
CONTROL REGISTERS
— Port 2 Control Register (High Byte)
EAH
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7 and .6
.5 and .4
.3 and .2
.1 and .0
Port 2, P2.7 Configuration Bits
0
0
S c h m itt trigger input, rising edge external interrupt
0
1
S c h m i t t t r i g g e r i n p u t , f a l l i n g e d g e s e x t e r n a l i n t e r r u p t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
Port 2, P2.6 Configuration Bits
0
0
Schmitt trigger input, rising edge external interrupt
0
1
S c h m i t t t r i g g e r i n p u t , f a l l i n g e d g e s e x t e r n a l i n t e r r u p t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
Port 2, P2.5 Configuration Bits
0
0
Schmitt trigger input, rising edge external interrupt
0
1
S c h m i t t t r i g g e r i n p u t , f a l l i n g e d g e s e x t e r n a l i n t e r r u p t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
Port 2, P2.4 Configuration Bits
0
0
Schmitt trigger input, rising edge external interrupt
0
1
S c h m i t t t r i g g e r i n p u t , f a l l i n g e d g e s e x t e r n a l i n t e r r u p t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
4 -3 1
CONTROL REGISTERS
P2CONL
S3C9688/P9688
— Port 2 Control Registe r (Low Byte)
EBH
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7 and .6
.5 and .4
.3 and .2
.1 and .0
4 -3 2
Port 2, P2.3 Configuration Bits
0
0
Schmitt trigger input, rising edge external interrupt
0
1
S c h m i t t t r i g g e r i n p u t , f a l l i n g e d g e s e x t e r n a l i n t e r r u p t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
Port 2, P2.2 Configuration Bits
0
0
Schmitt trigger input, rising edge external interrupt
0
1
S c h m i t t t r i g g e r i n p u t , f a l l i n g e d g e s e x t e r n a l i n t e r r u p t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
Port 2, P2.1 Configuration Bits
0
0
Schmitt trigger input, rising edge external interrupt
0
1
S c h m i t t t r i g g e r i n p u t , f a l l i n g e d g e s e x t e r n a l i n t e r r u p t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
Port 2, P2.0 Configuration Bits
0
0
S c h m itt trigger input, rising edge external interrupt
0
1
S c h m i t t t r i g g e r i n p u t , f a l l i n g e d g e s e x t e r n a l i n t e r r u p t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
S3C9688/P9688
P2INT
CONTROL REGISTERS
— Port 2 Interrupt Enable Register
ECH
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
.6
.5
.4
.3
.2
.1
.0
P2.7 Interrupt Enable Bit
0
External interrupt disable
1
External interrupt enable
P2.6 Interrupt Enable Bit
0
External interrupt disable
1
External interrupt enable
P2.5 Interrupt Enable Bit
0
External interrupt disable
1
External interrupt enable
P2.4 Interrupt Enable Bit
0
External interrupt disable
1
External interrupt enable
P2.3 Interrupt Enable Bit
0
External interrupt disable
1
External interrupt enable
P2.2 Interrupt Enable Bit
0
External interrupt disable
1
External interrupt enable
P2.1 Interrupt Enable Bit
0
External interrupt disable
1
External interrupt enable
P2.0 Interrupt Enable Bit
0
External interrupt disable
1
External interrupt enable
4 -3 3
CONTROL REGISTERS
4 -3 4
S3C9688/P9688
S3C9688/P9688
P2PND
CONTROL REGISTERS
— Port 2 Interrupt Pending Register
EDH
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R e a d / W r i t e (NOTE)
.7
.6
.5
.4
.3
.2
.1
.0
P2.7 Interrupt Pending Bit
0
No pending (when read)/clear pending bit (when write)
1
Pending (when read)/no effect (when write)
P2.6 Interrupt Pending Bit
0
No pending (when read)/clear pending bit (when write)
1
Pending (when read)/no effect (when write)
P2.5 Interrupt Pending Bit
0
No pending (when read)/clear pending bit (when write)
1
Pending (when read)/no effect (when write)
P2.4 Interrupt Pending Bit
0
No pending (when read)/clear pending bit (when write)
1
Pending (when read)/no effect (when write)
P2.3 Interrupt Pending Bit
0
No pending (when read)/clear pending bit (when write)
1
P e n d i n g ( w h e n re a d ) / n o e f f e c t ( w h e n w r i t e )
P2.2 Interrupt Pending Bit
0
No pending (when read)/clear pending bit (when write)
1
Pending (when read)/no effect (when write)
P2.1 Interrupt Pending Bit
0
No pending (when read)/clear pending bit (when write)
1
Pending (when read)/no effect (when write)
P2.0 Interrupt Pending Bit
0
No pending (when read)/clear pending bit (when write)
1
Pending (when read)/no effect (when write)
4 -3 5
CONTROL REGISTERS
N O T E: To clear a port 2 interrupt pending condition, write a "0" to the corresponding P2PND register bit location.
4 -3 6
S3C9688/P9688
S3C9688/P9688
CONTROL REGISTERS
P 3 C O N — Port 3 Control Register
E5H
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7 and .6
.5 and .4
.3 and .2
.1 and .0
NOTE:
Port 3, P3.3 Configuration Bits
0
0
Schmitt trigger input
0
1
System clock output(CLO) mode. CLO comes from system clock circuit.
1
0
P u s h -p u l l o u t p u t
1
1
N -c h a n n e l o p e n -d r a i n o u t p u t m o d e
Port 3, P3.2 Configuration Bits
0
x
Schmitt trigger input
1
0
P u s h -p u l l o u t p u t
1
1
N -c h a n n e l o p e n -d r a i n o u t p u t m o d e
Port 3, P3.1 Configuration Bits
0
x
Schmitt trigger input
1
0
P u s h -p u l l o u t p u t
1
1
N -c h a n n e l o p e n -d r a i n o u t p u t m o d e
Port 3, P3.0
Configuration Bits
0
x
Schmitt trigger input
1
0
P u s h -p u l l o u t p u t
1
1
N -c h a n n e l o p e n -d r a i n o u t p u t m o d e
"x" means don't care.
4 -3 7
CONTROL REGISTERS
P4CON
S3C9688/P9688
— Port 4 Control Register
EEH
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7 and .6
.5 and .4
.3 and .2
.1 and .0
4 -3 8
Port 4, P4.3 Configuration Control Bits
0
0
S c h m i t t t r i g g e r i n p u t , f a l l i n g e d g e e x t e r n a l i n t e r r u p t w i t h p u l l -u p
0
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
O u t p u t p u s h-p u l l m o d e
Port 4, P4.2 Configuration Control Bits
0
0
S c h m i t t t r i g g e r i n p u t , f a l l i n g e d g e e x t e r n a l i n t e r r u p t w i t h p u l l -u p
0
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
O u t p u t p u s h -p u l l m o d e
Port 4, P4.1 Configuration Control Bits
0
0
S c h m i t t t r i g g e r i n p u t , f a l l i n g e d g e e x t e r n a l i n t e r r u p t w i t h p u l l -u p
0
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
O u t p u t p u s h -p u l l m o d e
Port 4, P4.0 Configuration Control Bits
0
0
S c h m i t t t r i g g e r i n p u t , f a l l i n g e d g e e x t e r n a l i n t e r r u p t w i t h p u l l -u p
0
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
O u t p u t p u s h -p u l l m o d e
S3C9688/P9688
P4INTPND
CONTROL REGISTERS
— P o rt 4 I n t e r r u p t E n a b l e a n d P e n d i n g R e g i s t e r
EFH
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
.6
.5
.4
.3
.2
.1
.0
P4.3 Interrupt Enable Bit
0
External interrupt disable
1
External interrupt enable
P4.2 Interrupt Enable Bit
0
External interrupt disable
1
External interrupt enable
P4.1 Interrupt Enable Bit
0
External interrupt disable
1
External interrupt enable
P 4.0 Interrupt Enable Bit
0
External interrupt disable
1
External interrupt enable
P4.3 Interrupt Pending Bit
0
No pending (when bit is read)/clear pending bit (when bit is write)
1
Pending (when bit is read)/no effect (when bit is write)
P4.2 Interrupt Pending Bit
0
No pending (when bit is read)/clear pending bit (when bit is write)
1
Pending (when bit is read)/no effect (when bit is write)
P4.1 Interrupt Pending Bit
0
N o p e n d i n g ( w h e n b i t i s r e a d ) / c l e a r p e n d i n g b i t ( w h e n b it i s w r i t e )
1
Pending (when bit is read)/no effect (when bit is write)
P4.0 Interrupt Pending Bit
0
No pending (when bit is read)/clear pending bit (when bit is write)
1
Pending (when bit is read)/no effect (when bit is write)
4 -3 9
CONTROL REGISTERS
4 -4 0
S3C9688/P9688
S3C9688/P9688
PS2CONINT
CONTROL REGISTERS
— PS2 Control and Interrupt Pending Register (PS2 Mode only)
D7H
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7 and .6
.5 and .4
.4
.3
.1
.0
D + / P S 2 C o n f i g u r a t i o n C o n tr o l B i t s
0
0
Schmitt trigger input, falling edge external interrupt
0
1
S c h m i t t t r i g g e r i n p u t , f a l l i n g e d g e e x t e r n a l i n t e r r u p t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
D -/ P S 2 C o n f i g u r a t i o n C o n t r o l B i t s
0
0
Schmitt trigger input, falling edge external interrupt
0
1
S c h m i t t t r i g g e r i n p u t , f a l l i n g e d g e e x t e r n a l i n t e r r u p t w i t h p u l l -u p
1
0
N -C H o p e n d r a i n o u t p u t m o d e
1
1
N -C H o p e n d r a i n o u t p u t m o d e w i t h p u l l -u p
D+/PS2 Interrupt Enable Bit
0
External interrupt disable
1
External interrupt enable
D -/ P S 2 I n t e r r u p t E n a b l e B i t
0
External interrupt disable
1
External interrupt enable
D+/PS2 Interrupt Pending Bit
0
No pending (when bit is read)/clear pending bit (when bit is write)
1
Pending (when bit is read)/no effect (when bit is write)
D -/ P S 2 I n t e r r u p t P e n d i n g B i t
0
No pending (when bit is read)/clear pending bit (when bit is write)
1
Pending (when bit is read)/no effect (when bit is write)
4 -4 1
CONTROL REGISTERS
P W R M GR
S3C9688/P9688
— U S B Power Management Register
F8H
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
–
–
–
0
0
0
–
0
Read/Write
–
–
–
R/W
R/W
R/W
–
R/W
. 7 –. 5
Not used for C9688/P9688
.4
DATA + monitoring Bit
.3
.2
0
DATA+ is zero
1
DATA - is one
DATA - monitoring Bit
0
DATA - is zero
1
DATA - is one
Clear Suspend Counter Bit
0
-
1
Clear internal suspend counter register..
.1
Not used for S3P9688
.0
SUSPEND Status Bit
0
Cleared when function receives resume signal from the host while in suspend
mode
1
4 -4 2
This bit is set when SUSPEND interrupt occur
S3C9688/P9688
SYM
CONTROL REGISTERS
— System Mode Register
DFH
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
–
–
–
–
–
0
0
0
Read/Write
–
–
–
–
–
R/W
R/W
R/W
. 7 –. 3
Not used for S3C9688/P9688
.2
G l o b a l I n t e r r u p t E n a b l e B i t (note)
.1 and .0
0
Disable global interrupt processing
1
Enable global interrupt processing
Page Selection Bits
0
0
Other values
N O T E:
Addressing page 0 locations for S3C9688/P9688
Not allowed in S3C9688/P9688
SYM must be selected bit 1 and 0 into 00 for S3C9688/P9688.
4 -4 3
CONTROL REGISTERS
T0CON
S3C9688/P9688
— Timer 0 Control Register
D2H
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7 and .6
.5 and .4
T0 Counter Input Clock Selection Bits
0
0
CPU clock/4096
0
1
CPU clock/256
1
0
CPU clock/8
1
1
Invalid selection
T0 Operating Mode Selection Bits
0
0
Interval timer mode (The counter is automatically cleared whenever T0DATA
value equals to T0CNT value)
.3
.2
.1
.0
N O T E:
4 -4 4
0
1
1
0
1
1
Invalid selection
Overflow mode (OVF interrupt can occur)
T0 Counter Clear Bit (T0CLR)
0
No effect when written
1
Clear T0 counter
T0 Overflow Interrupt Enable Bit (T0OVF)
0
Disable T0 overflow interrupt
1
Enable T0 overflow interrupt
T0 Match Interrupt Enable Bit (T0INT)
0
Disable T0 match interrupt
1
Enable T0 match interrupt
T0 Interrupt Pending Bit (T0PND)
0
N o i n t e r r u p t p e n d i n g / Clear this pending bit (when write)
1
Interrupt is pending(when read)/No effect (when write)
When you write a "1" to T0CON.3, the timer 0 counter is cleared. The bit is then cleared automatically to "0".
S3C9688/P9688
USBCON
CONTROL REGISTERS
— USB Control Register
FEH
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
–
–
0
0
1
0
1
1
Read/Write
–
–
R/W
R/W
R/W
R/W
R/W
R
.7 and .6
Reserved
.5
DP/DM Control Bit
.4
.3
.2
.1
.0
0
DP/DM can not be individually controlled by MCU
1
DP/DM can be individually controlled by MCU to set USBCON.4 and USBCON.3
DP Status Bit
0
DP is low
1
DP is high
DM Status Bit
0
DM is low
1
DM is high
USB Reset MCU Bit
0
USB which is been on RESET can not make MCU reset
1
USB which is been on RESET can be able to reset MCU
MCU reset USB Bit
0
No effect
1
MCU forces USB be reset
USB RESET Signal Receive Bit
0
USB Reset is detected.
1
USB Reset is undetected
4 -4 5
CONTROL REGISTERS
USBINT
S3C9688/P9688
— USB Interrupt Enable Register
F7H
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
–
–
–
0
0
0
0
0
Re ad/Write
–
–
–
R/W
R/W
R/W
R/W
R/W
. 7 –. 5
Not used for C9688/P9688
.4
USB Reset Interrupt Pending Bit
.3
.2
.1
.0
4 -4 6
0
Disable USB Reset Interrupt
1
Enable USB Reset Interrupt
ENDPOINT2 Interrupt Pending Bit
0
Disable ENDPOINT 2 interrupt
1
Enable ENDPOINT 2 interrupt
SUSPEND/RESUME Interrupt Enable Bit
0
Disable SUSPEND and RESUME interrupt
1
Enable SUSPEND and RESUME interrupt
ENDPOINT1 Interrupt Pending Bit
0
Disable ENDPOINT 1 interrupt
1
Enable ENDPOINT 1 interrupt
ENDP OINT0 Interrupt Pending Bit
0
Disable ENDPOINT 0 interrupt
1
Enable ENDPOINT 0 interrupt
S3C9688/P9688
USBPND
CONTROL REGISTERS
— USB Interrupt Pending Register
F6H
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
–
–
0
0
0
0
0
0
Read/Write
–
–
R/W
R/W
R/W
R/W
R/W
R/W
. 7 –. 6
Not used for C9688/P9688
.5
USB Reset Interrupt Pending Bit
.4
.3
.2
.1
.0
0
No effect (Write 1, this bit is cleared )
1
This bit is set, when USB bus reset is detected on the bus.
ENDPOINT 2 Interrupt Pending Bit
0
No effect (Write 1, this bit is cleared)
1
This bit is set, when endpoint2 needs to be serviced
RESUME Interrupt Pending Bit
0
No effect (Write 1, this bit is cleared)
1
While in suspend mode, if resume signaling is received this bit gets set
SUSPEND Interrupt Pending Bit
0
No effect (Write 1, this bit is cleared )
1
This bit is set, when suspend signaling is received
ENDPOINT1 Interrupt Pending Bit
0
No effect (Write 1, this bit is cleared)
1
This bit is set, when endpoint1 needs to be serviced
ENDPOINT0 Interrupt Pending Bit
0
No effect (Write1, this bit is cleared )
1
This bit is set, while endpoint 0 needs to serviced. It is set under the following
conditions;
—
OUT_PKT_RDY is set
—
IN_PKT_RDY get cleared
—
SENT_STALL gets set
—
SETUP_DATA_END gets cleared
—
SETUP_TRANSFER_END gets set
4 -4 7
CONTROL REGISTERS
USXCON
S3C9688/P9688
— USB Selection and Signal Crossover Point Control Register
D3H
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET V a l u e
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
.6
. 5 –. 0
USB/PS2 Mode select Bit
0
PS2 Mode
1
USB Mode
U S B P u l l -U p C o n t r o l r e g i s t e r
0
P u l l -U p D i s a b l e
1
P u l l -U p E n a b l e
USB Signal Crossover Point Control Bit
Edge delay
Bit 5, (2)
Bit 4, (1)
Bit 3, (0)
Control
RISE
0
edge
FALL
edge
NOTE:
4 -4 8
Bit 5, 4, 3: DM, Bit 2, 1, 0: DP
1
Delay
Delay
Value
Unit
0
0
0
0
1
1
1
0
2
(about)
1
1
4
2.5nsec
0
0
0
0
1
1
1
0
2
1
1
4
S3C9688/P9688
CONTROL REGISTERS
NOTES
4 -4 9
S3C9688/P9688
5
INTERRUPT STRUCTURE
INTERRUPT STRUCTURE
OVERVIEW
The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt
sources can be serviced through a interrupt vector which is assig ned in ROM address 0000H– 0001H.
VECTOR
SOURCES
S1
0000H
S2
0001H
S3
Sn
NOTES:
1. The SAM88RCRI interrupt has only one vector address (0000H-0001H).
2. The number of Sn value is expandable.
F i g u r e 5 -1 . S 3 C 9 -S e r i e s I n t e r r u p t T y p e
INTERRUPT PROCESSING CONTROL POINTS
Interrupt processing can be controlled in two ways: either globally, or by specific interrupt level and source. The
m a j o r f e a t u r e s o f s y s t e m -l e v e l c o n t r o l i n t h e i n t e r r u p t s t r u c t u r e a r e a s f o l l o w s :
—
Global interrupt enable and disable (by EI and DI instructions)
—
Interrupt sourc e enable and disable settings in the corresponding peripheral control register(s)
ENABLE/DISABLE INTERRUPT INSTRUCTIONS (E I, DI)
The system mode register, SYM (DFH), is used in settings interrupt processing enabled or disabled.
SYM.2 is the enable and disable bit for global interrupt processing respectively, by modifying SYM.2. An Enable
Interrupt (EI) instruction must be included in the initialization routine that follows a reset operation in order to enable
interrupt processing. Although you can manipulate SYM.2 directly to enable and disable interrupts during normal
operation, we recommend that you use the EI and DI instructions for this purpose.
5 -1
INTERRUPT STRUCTURE
S3C9688/P9688
INTERRUPT PENDING FUNCTION TYPES
When the interrupt service routine has been executed, the appropriate pending bit must be cleared in the application
program's service routine before the return from interrupt subroutine (IRET) occurs.
INTERRUPT PRIORITY
Because there is not a interrupt priority register in SAM88RCRI, the order of service is determined by a sequence of
source which is executed in interrupt service routine.
"EI" Instruction
Execution
RESET
S
Q
Interrupt Pending Register
R
Source
Interrpt priority
Interrupts
is determind by
software polling
Source
Vector
Interrupt
Cycle
method
Interrupt
Enable
Global Interrupt Control
(EI, DI instruction)
F i g u r e 5 -2 . I n t e r r u p t F u n c t i o n D i a g r a m
INTERRUPT SOURCE SERVICE SEQUENCE
The interrupt request polling and servicing sequence is as follows:
1.
A source generates an interrupt request by setting the interrupt request pending bit to "1".
2.
The CPU generates an interrupt acknowledge signal.
3.
The service routine starts and the source's pending flag is cleared to "0" by software.
4.
Interrupt priority must be determined by software polling method.
5 -2
S3C9688/P9688
INTERRUPT STRUCTURE
INTERRUPT SERVICE ROUTINES
Before an interrupt request can be serviced, the following conditions must be met:
—
Interrupt processing must be enabled (EI, SYM.2 = "1")
—
Interrupt must be enabled at the interrupt's source (peripheral control re gister)
If all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The
CPU then initiates an interrupt machine cycle that completes the following processing sequence:
1.
Reset (clear to "0") the global interrupt enable bit in the SYM register (DI, SYM.2 = "0")
to disable all subsequent interrupts.
2.
Save the program counter (PC) and status flags (FLAGs) to stack.
3.
Branch to the interrupt vector to fetch the service routine's address.
4.
P a s s c o n t r o l to the interrupt service routine.
When the interrupt service routine is completed, an Interrupt Return instruction (IRET) occurs. The IRET restores the
PC and status flags and sets SYM.2 to "1"(EI), allowing the CPU to process the next interrupt request.
GENERATING INTERRUPT VECTOR ADDRESSES
The interrupt vector area in the ROM contains the address of the interrupt service routine. Vectored interrupt
processing follows this sequence:
1.
P u s h t h e p r o g r a m c o u n t e r ' s l o w -b y t e v a l u e t o s t a c k .
2.
P u s h t h e p r o g r a m c o u n t e r ' s h i g h -b y t e v a l u e t o s t a c k .
3.
Push the FLAGS register values to stack.
4.
F e t c h t h e s e r v i c e r o u t i n e ' s h i g h -b y t e a d d r e s s f r o m t h e v e c t o r a d d r e s s 0 0 0 0 H .
5.
F e t c h t h e s e r v i c e r o u t i n e ' s l o w -b y t e a d d r e s s f r o m t h e v e c t o r a d d r e s s 0 0 0 1 H .
6.
B r a n c h t o t h e s e r v i c e r o u t i n e s p e c i f i e d b y t h e 1 6 -b i t v e c t o r a d d r e s s .
5 -3
INTERRUPT STRUCTURE
S3C9688/P9688
S3C9688/P9688 INTERRUPT STRUCTURE
The S3C9688/P9688 microcontroller has 29 peripheral interrupt sources:
—
Timer 0 match interrupt
—
Timer 0 overflow interrupt
—
Eight external interrupts for port 2, P2.0– P2.7
—
Four external interrupts for port 4, P4.0– P4.3
—
D -/ P S 2 a n d D + / P s 2 e x t e r n a l i n t e r r u p t s ( o n l y i n P S 2 m o d e )
—
USB EP0, 1, 2 Interrupt
—
Suspend interrupt
—
Resume interrupt
Vector
Pending Bits
Enable/Disable
Sources
Timer 0 Match Interrupt
T0CON.1
T0CON
Timer 0 Overflow Interrupt
T0CON.2
P0PND.X
P2PND.X
P0.X External Interrupt
P0INT.X
P2.X External Interrupt
P2INT.X
P4.0-3 External Interrupt
P4INTPND.0-3
P4INTPND.0
0000H
P4INTPND.1
(EI/DI)
P4INTPND.4-7
Endpoint 0 Interrupt
USBINT.0
Endpoint 1 Interrupt
USBINT.1
SYM.2
Endpoint 2 Interrupt
P4INTPND.4
USBINT.3
D-/PS2 Interrupt
PS2CONINT.0
PS2CONINT.2
D+/PS2 Interrupt
PS2CONINT.1
PS2CONINT.3
Suspend Interrupt
USBPND.2
USBINT.2
USBPND.3
NOTE:
Resume Interrupt
USBINT.2
"X" means 0-7 bit.
F i g u r e 5 -3 . S 3 C 9 6 8 8 / P 9 6 8 8 I n t e r r u p t S t r u c t u r e
5 -4
S3C9688/P9688
6
S A M 8 8RCRI INSTRUCTION SET
SAM88RCRI INSTRUCTION SET
OVERVIEW
T h e S A M 8 8 R C R I i n s t r u c t i o n s e t i s d e s i g n e d t o s u p p o r t t h e l a r g e r e g i s t e r f i l e . I t i n c l u d e s a f u l l c o m p l e m e n t o f 8 -b i t
arithmetic and logic operations. There are 41 instructions. No special I/O instructions are necessary because I/O
control and data registers are mapped directly into the register file. Flexible instructions for bit addressing, rotate,
and shift operations complete the powerful data manipulation capabilities of the SAM88RCRI instruction set.
REGISTER ADDRESSING
T o a c c e s s a n i n d i v i d u a l r e g i s t e r , a n 8 -b i t a d d r e s s i n t h e r a n g e 0 -2 5 5 o r t h e 4 -b i t a d d r e s s o f a w o r k i n g r e g i s t e r i s
s p e c i f i e d . P a i r e d r e g i s t e r s c a n b e u s e d t o c o n s tr u c t 1 3 -b i t p r o g r a m m e m o r y o r d a t a m e m o r y a d d r e s s e s . F o r d e t a i l e d
information about register addressing, please refer to Section 2, "Address Spaces".
ADDRESSING MODES
There are six addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative (RA), and
Immediate (IM). For detailed descriptions of these addressing modes, please refer to Section 3, "Addressing
Modes".
6 -1
SAM88RI INSTRUCTION SET
S3C9688/P9688
T a b l e 6 -1 . I n s t r u c t i o n G r o u p S u m m a r y
Mnemonic
Operands
Instruction
Load Instructions
CLR
dst
Clear
LD
dst,src
Load
LDC
dst,src
Load program memory
LDE
dst,src
Load external data memory
LDCD
dst,src
Load program memory and decrement
LDED
dst,src
Load external data memory and decrement
LDCI
dst,src
Load program memory and increment
LDEI
dst,src
Load external data memory and increment
POP
dst
Pop from stack
PUSH
src
Push to stack
Arithmetic Instructions
ADC
dst,src
Add with carry
ADD
dst,src
Add
CP
dst,src
Compare
DEC
dst
Dec rement
INC
dst
Increment
SBC
dst,src
Subtract with carry
SUB
dst,src
Subtract
Logic Instructions
AND
dst,src
Logical AND
COM
dst
Complement
OR
dst,src
Logical OR
XOR
dst,src
Logical exclusive OR
6 -2
S3C9688/P9688
S A M 8 8RCRI INSTRUCTION SET
T a b l e 6 -1 . I n s t r u c t i o n G r o u p S u m m a r y ( C o n t i n u e d )
Mnemonic
Operands
Instruction
Program Control Instructions
CALL
dst
IRET
Call procedure
Interrupt return
JP
cc,dst
Jump on condition code
JP
dst
Jump unconditional
JR
cc,dst
Jump relative on condition code
RET
Return
Bit Manipulation Instru ctions
TCM
dst,src
Test complement under mask
TM
dst,src
Test under mask
Rotate and Shift Instructions
RL
dst
Rotate left
RLC
dst
Rotate left through carry
RR
dst
Rotate right
RRC
dst
Rotate right through carry
SRA
dst
Shift right arithmetic
CPU Control Instructions
CCF
Complement carry flag
DI
Disable interrupts
EI
Enable interrupts
IDLE
Enter Idle mode
NOP
No operation
RCF
Reset carry flag
SCF
Set carry flag
STOP
Enter Stop mode
6 -3
SAM88RI INSTRUCTION SET
S3C9688/P9688
FLAGS REGISTER (FLAGS )
The FLAGS register contains eight bits that describe the current status of CPU operations. Four of these bits,
FLAGS.4 – FLAGS.7, can be tested and used with conditional jump instructions;
FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load
instruction. Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags
register. For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the
AND instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will
occur to the Flags register producing an unpredictable result.
System Flags Register (FLAGS)
D5H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Carry flag (C)
Not mapped
Zero flag (Z)
Sign flag (S)
Overflow (V)
F i g u r e 6 -1 . S y s t e m F l a g s R e g i s t e r ( F L A G S )
FLAG DESCRIPTIONS
Overflow Flag (FLAGS.4, V)
T h e V f l a g i s s e t t o " 1 " w h e n t h e r e s u l t o f a t w o ' s -c o m p l e m e n t o p e r a t i o n i s g r e a t e r t h a n + 1 2 7 o r l e s s t h a n – 1 2 8 . I t i s
also cleared to "0" following logic operations.
Sign Flag (FLAGS.5, S)
Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A logic
zero indicates a positive number and a logic one indicates a negative number.
Zero Flag (FLAGS.6, Z)
For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For operations that
test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is logic zero.
Carry Flag (FLAGS.7, C)
T h e C f l a g i s s e t t o " 1 " i f t h e r e s u l t f r o m a n a r i t h m e t i c o p e r a t i o n g e n e r a t e s a c a r r y -o u t f r o m o r a b o r r o w t o t h e b i t 7
position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register.
Program instructions can set, clear, or complement the carry flag.
6 -4
S3C9688/P9688
S A M 8 8RCRI INSTRUCTION SET
INSTRUCTION SET NOTATION
T a b l e 6 -2 . F l a g N o t a t i o n C o n v e n t i o n s
Flag
Description
C
Carry flag
Z
Zero flag
S
Sign flag
V
Overflow flag
0
Cleared to logic zero
1
Set to logic one
*
Set or cleared according to operation
–
Value is unaffected
x
Value is undefined
T a b l e 6 -3 . I n s t r u c t i o n S e t S y m b o l s
Symbol
Description
dst
Destination operand
src
Source operand
@
Indirect register address prefix
PC
Pro g r a m c o u n t e r
FLAGS
Flags register (D5H)
#
Immediate operand or register address prefix
H
Hexadecimal number suffix
D
Decimal number suffix
B
Binary number suffix
opc
Opcode
6 -5
SAM88RI INSTRUCTION SET
S3C9688/P9688
T a b l e 6 -4 . I n s t r u c t i o n N o t a t i o n C o n v e n t i o n s
Notation
cc
Description
Actual Operand Range
Condition code
S e e l i s t o f c o n d i t i o n c o d e s i n T a b l e 6 -6 .
r
Working register only
Rn (n = 0– 15)
rr
Working register pair
RRp (p = 0, 2, 4, ..., 14)
R
Register or working register
re g o r R n ( r e g = 0 – 2 5 5 , n = 0 – 1 5 )
Register pair or working register pair
reg or RRp (reg = 0– 254, even number only, where
RR
p = 0, 2, ..., 14)
Ir
Indirect working register only
@Rn (n = 0– 15)
IR
Indirect register or indirect working register
@Rn or @reg (reg = 0– 255, n = 0– 15)
Irr
Indirect working register pair only
@RRp (p = 0, 2, ..., 14)
Indirect register pair or indirect working
@RRp or @reg (reg = 0– 254, even only, where
register pair
p = 0, 2, ..., 14)
Indexed addressing mode
#reg[Rn] (reg = 0– 255, n = 0– 15)
Indexed (short offset) addressing mode
#addr[RRp] (addr = range – 128 to +127, where
IRR
X
XS
p = 0, 2, ..., 14)
xl
Indexed (long offset) addressing mode
#addr [RRp] (addr = range 0– 8191, where
p = 0, 2, ..., 14)
da
Direct addressing mode
addr (addr = range 0– 8191)
ra
Relative addressing mode
addr (addr = number in the range +127 to – 128 that is
an offset relative to the address of the next instruction)
im
6 -6
Immediate addressing mode
#data (data = 0– 255)
S3C9688/P9688
S A M 8 8RCRI INSTRUCTION SET
T a b l e 6 -5 . O p c o d e Q u ic k R e f e r e n c e
OPCODE MAP
LOWER NIBBLE (HEX)
U
P
P
E
R
–
0
1
2
0
DEC
DEC
ADD
ADD
ADD
ADD
ADD
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
RLC
RLC
ADC
ADC
ADC
ADC
ADC
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
INC
INC
SUB
SUB
SUB
SUB
SUB
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
1
2
3
N
I
B
6
7
4
5
6
JP
SBC
SBC
SBC
SBC
SBC
IRR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
4
5
3
OR
OR
OR
OR
OR
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
POP
POP
AND
AND
AND
AND
AND
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R 1
R1,IM
COM
COM
TCM
TCM
TCM
TCM
TCM
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
PUSH
PUSH
TM
TM
TM
TM
TM
R2
IR2
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
8
7
LD
r1, x, r2
B
L
E
9
E
X
RL
LD
R1
IR1
r2, x, r1
A
B
C
H
RL
D
E
F
CP
CP
CP
CP
CP
LDC
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
r1, Irr2, xL
CLR
CLR
XOR
XOR
XOR
XOR
XOR
LDC
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
r2, Irr2, xL
RRC
RRC
LDC
LD
R1
IR1
r1,Irr2
r1, Ir2
SRA
SRA
LDC
LD
LD
R1
IR1
r2,Irr1
IR1,IM
Ir1, r2
RR
RR
LDCD
LDCI
LD
LD
LD
LDC
R1
IR1
r1,Irr2
r1,Irr2
R2,R1
R2,IR1
R1,IM
r1, Irr2, xs
CALL
LD
CALL
LDC
IRR1
IR2,R1
DA1
r2, Irr1, xs
6 -7
SAM88RI INSTRUCTION SET
S3C9688/P9688
T a b l e 6 -5 . O p c o d e Q u i c k R e f e r e n c e ( C o n t i n u e d )
OPCODE MAP
LOWER NIBBLE (HEX)
–
U
0
P
1
P
2
E
3
R
4
8
9
A
B
C
D
E
LD
LD
JR
LD
JP
INC
r1,R2
r2,R1
cc,RA
r1,IM
cc,DA
r1
↓
↓
↓
↓
↓
↓
F
5
N
6
I
7
B
8
DI
B
9
EI
L
A
RET
E
B
IRET
C
RCF
H
D
E
E
X
F
6 -8
IDLE
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
STOP
SCF
CCF
LD
LD
JR
LD
JP
INC
r1,R2
r2,R1
cc,RA
r1,IM
cc,DA
r1
NOP
S3C9688/P9688
S A M 8 8RCRI INSTRUCTION SET
CONDITION CODES
T h e o p c o d e o f a c o n d i t i o n a l j u m p a l w a y s c o n t a i n s a 4 -b i t f i e l d c a l l e d t h e c o n d i t i o n c o d e ( c c ) . T h i s s p e c i f i e s u n d e r
which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a
c o m p a r e o p e r a t i o n o n l y j u m p s i f t h e t w o o p e r a n d s a r e e q u a l . C o n d i t i o n c o d e s a r e l i s t e d i n T a b l e 6 -6 .
The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump
instructions.
T a b l e 6 -6 . C o n d i t i o n C o d e s
Binary
Mnemonic
Description
Flags Set
0000
F
Always false
–
1000
T
Always true
–
0111 (1)
C
Carry
C = 1
1111 (1)
NC
No carry
C = 0
0110 (1)
Z
Zero
Z = 1
1110 (1)
NZ
Not zero
Z = 0
1101
PL
Plus
S = 0
0101
MI
Minus
S = 1
0100
OV
Overflow
V = 1
1100
NOV
No overflow
V = 0
0110 (1)
EQ
Equal
Z = 1
1110 (1)
NE
Not equal
Z = 0
1001
GE
Greater than or equal
(S XOR V) = 0
0001
LT
Less than
(S XOR V) = 1
1010
GT
Greater than
(Z OR (S XOR V)) = 0
0010
LE
Less than or equal
(Z OR (S XOR V)) = 1
1111 (1)
UGE
Unsigned greater than or equal
C = 0
0111 (1)
ULT
Unsigned less than
C = 1
1011
UGT
Unsigned greater than
(C = 0 AND Z = 0) = 1
0011
ULE
Unsigned less than or equal
(C OR Z) = 1
NOTES:
1.
Indicate condition codes that are related to two different mnemonics but which test the same flag.
For
example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used;
after a CP instruction, however, EQ would probably be used.
2.
For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.
6 -9
SAM88RI INSTRUCTION SET
S3C9688/P9688
INSTRUCTION DESCRIPTIONS
This section contains detailed information and programming examples for each instruction in the SAM88RCRI
instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The
following information is included in each instruction description:
—
Instruction name (mnemonic)
—
Full instruction name
—
Source/destination format of the instruction operand
—
Shorthand notation of the instruction's operation
—
Textual description of the instruction's effect
—
Specific flag settings affected by the instruction
—
Detailed description of the instruction's format, execution time, and addressing mode(s)
—
Programming example(s) explaining how to use the instruction
6 -1 0
S3C9688/P9688
ADC
S A M 8 8RCRI INSTRUCTION SET
— A d d W i t h C arry
ADC
dst,src
Operation:
dst ← dst + src + c
The source operand, along with the setting of the carry flag, is added to the destination operand and
t h e s u m i s s t o r e d i n t h e d e s t i n a t i o n . T h e c o n t e n t s o f t h e s o u r c e a r e u n a f f e c t e d . T w o ' s -c o m p l e m e n t
addition is performed. In multiple precision arithmetic, this instruction permits the carry from the
a d d i t i o n o f l o w -o r d e r o p e r a n d s t o b e c a r r i e d i n t o t h e a d d i t i o n o f h i g h -o r d e r o p e r a n d s .
Flags:
C:
Set if there is a carry from the most significant bit of the result; cleared otherwise.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result is negative; cleared otherwise.
V:
Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the
result is of the opposite sign; cleared otherwise.
D:
Always cleared to "0".
H:
S e t i f t h e r e i s a c a r r y f r o m t h e m o s t s i g n i f i c a n t b i t o f t h e l o w -o r d e r f o u r b i t s o f t h e r e s u l t ;
cleared otherwise.
Format:
Bytes
opc
opc
opc
Examples:
Given:
dst | src
src
dst
2
dst
src
3
3
Cycles
Opcode
Addr Mode
(Hex)
dst
src
4
12
r
r
6
13
r
lr
6
14
R
R
6
15
R
IR
6
16
R
IM
R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and
register 03H = 0AH:
ADC
R1,R2
→
R1 = 14H, R2 = 03H
ADC
R1,@R2
→
R1 = 1BH, R2 = 03H
ADC
01H,02H
→
Register 01H = 24H, register 02H = 03H
ADC
01H,@02H
→
Register 01H = 2BH, register 02H = 03H
ADC
01H,#11H
→
Register 01H = 32H
I n t h e f i r s t e x a m p le , d e s t i n a t i o n r e g i s t e r R 1 c o n t a i n s t h e v a l u e 1 0 H , t h e c a r r y f l a g i s s e t t o " 1 " , a n d
the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds 03H and
the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.
6 -1 1
SAM88RI INSTRUCTION SET
ADD
S3C9688/P9688
— Add
ADD
dst,src
Operation:
dst ← dst + src
The source operand is added to the destination operand and the sum is stored in the destination.
T h e c o n t e n t s o f t h e s o u r c e a r e u n a f f e c t e d . T w o ' s -c o m p l e m e n t a d d i t i o n i s p e r f o r m e d .
Flags:
C:
Set if there is a carry from the most significant bit of the result; cleared otherwise
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result is negative; cleared otherwise.
V:
Set if arithmetic overflow occurred, that is, if both operands are of the same sign and
the result is of the opposite sign; cleared otherwise.
D:
Always cleared to "0".
H:
S e t i f a c a r r y f r o m t h e l o w -o r d e r n i b b l e o c c u r r e d .
Format:
Bytes
opc
opc
opc
Examples:
Given:
dst | src
src
dst
2
dst
src
3
3
Cycles
Opcode
Addr Mode
(Hex)
dst
src
4
02
r
r
6
03
r
lr
6
04
R
R
6
05
R
IR
6
06
R
IM
R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
ADD
R1,R2
→
R1 = 15H, R2 = 03H
ADD
R1,@R2
→
R1 = 1CH, R2 = 03H
ADD
01H,02H
→
Register 01H = 24H, register 02H = 03H
ADD
01H,@02H
→
Register 01H = 2BH, register 02H = 03H
ADD
01H,#25H
→
Register 01H = 46H
In the first example, destination working regis ter R1 contains 12H and the source working register
R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in register
R1.
6 -1 2
S3C9688/P9688
AND
S A M 8 8RCRI INSTRUCTION SET
— Logical AND
AND
dst,src
Operation:
dst ← dst AND src
The source operand is logically ANDed with the destination operand. The result is stored in the
destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in
the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source
are unaffected.
Flags:
C:
Unaffected.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Always cleared to "0".
D:
Unaffected.
H:
Unaffected.
Format:
Bytes
opc
opc
opc
Examples:
Given:
dst | src
src
dst
2
dst
src
3
3
Cycles
Opcode
Addr Mode
(Hex)
dst
src
4
52
r
r
6
53
r
lr
6
54
R
R
6
55
R
IR
6
56
R
IM
R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
AND
R1,R2
→
R1 = 02H, R2 = 03H
AND
R1,@R2
→
R1 = 02H, R2 = 03H
AND
01H,02H
→
Register 01H = 01H, register 02H = 03H
AND
01H,@02H
→
Register 01H = 00H, register 02H = 03H
AND
01H,#25H
→
Register 01H = 21H
In the first example, destination working register R1 contains the value 12H and the source working
register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand 03H with
the destination operand value 12H, leaving the value 02H in register R1.
6 -1 3
SAM88RI INSTRUCTION SET
CALL
S3C9688/P9688
— Call Procedure
CALL
dst
Operation:
SP
@SP
SP
@SP
PC
←
←
←
←
←
SP – 1
PCL
SP –1
PCH
dst
The current contents of the program counter are pushed onto the top of the stack. The program
counter value used is the address of the first instruction following the CALL instruction. The specified
destination address is then loaded into the program counter and points to the first instruction of a
procedure. At the end of the procedure the return instruction (RET) can be used to return to the
original program flow. RET pops the top of the stack back into the program counter.
Flags:
No flags are affected.
Format:
Bytes
opc
dst
opc
Examples:
dst
Cycles
Addr Mode
(Hex)
dst
3
14
F6
DA
2
12
F4
IRR
Given:
R0 = 15H, R1 = 21H, PC = 1A47H, and SP = 0B2H:
CALL
1521H
→
Opcode
SP = 0B0H
(Memory locations 00H = 1AH, 01H = 4AH, where 4AH
is the address that follows the instruction.)
CALL
@RR0
→
SP = 0B0H (00H = 1AH, 01H = 49H)
I n t h e f i r s t e x am p l e , i f t h e p r o g r a m c o u n t e r v a l u e i s 1 A 4 7 H a n d t h e s t a c k p o i n t e r c o n t a i n s t h e v a l u e
0B2H, the statement "CALL 1521H" pushes the current PC value onto the top of the stack. The
stack pointer now points to memory location 00H. The PC is then loaded with the value 1521H, the
address of the first instruction in the program sequence to be executed.
If the contents of the program counter and stack pointer are the same as in the first example, the
statement "CALL @RR0" produces the same result except that the 49H is stored in stack location
0 1 H ( b e c a u s e t h e t w o -b y t e i n s t r u c t i o n f o r m a t w a s u s e d ) . T h e P C i s t h e n l o a d e d w i t h t h e v a l u e
1521H, the address of the first instruction in the program sequence to be executed.
6 -1 4
S3C9688/P9688
CCF
S A M 8 8RCRI INSTRUCTION SET
— Complement Carry Flag
CCF
Operation:
C ← NOT C
The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if
C = "0", the value of the carry flag is changed to logic one.
Flags:
C:
Complemented.
No other flags are affected.
F o r m a t:
Bytes
Cycles
Opcode
(Hex)
opc
Example:
Given:
1
4
EF
The carry flag = "0":
CCF
If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H), changing
its value from logic zero to logic one.
6 -1 5
SAM88RI INSTRUCTION SET
CLR
S3C9688/P9688
— Clear
CLR
dst
Operation:
dst ← "0"
The destination location is cleared to "0".
Flags:
No flags are affected.
Format:
Bytes
opc
Examples:
Given:
dst
2
Cycles
Opcode
Addr Mode
(Hex)
dst
4
B0
R
4
B1
IR
R e g i s t e r 0 0 H = 4 F H , r e g is t e r 0 1 H = 0 2 H , a n d r e g i s t e r 0 2 H = 5 E H :
CLR
00H
→
Register 00H = 00H
CLR
@01H
→
Register 01H = 02H, register 02H = 00H
In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H
value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR)
addressing mode to clear the 02H register value to 00H.
6 -1 6
S3C9688/P9688
COM
S A M 8 8RCRI INSTRUCTION SET
— Complement
COM
dst
Operation:
dst ← NOT dst
The contents of the destination location are complemented (one's comple ment); all "1s" are
c h a n g e d t o " 0 s " , a n d v i c e-v e r s a .
Flags:
C:
Unaffected.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Always reset to "0".
D:
Unaffected.
H:
Unaffected.
Format:
Bytes
opc
Examples:
Given:
dst
2
Cycles
Opcode
Addr Mode
(Hex)
dst
4
60
R
4
61
IR
R1 = 07H and register 07H = 0F1H:
COM
R1
→
R1 = 0F8H
COM
@R1
→
R1 = 07H, register 07H = 0EH
In the first example, destination working register R1 contains the value 07H (00000111B). The
statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros, and
v i c e-v e r s a , l e a v i n g t h e v a l u e 0 F 8 H ( 1 1 1 1 1 0 0 0 B ) .
In the second example, Indirect Register (IR) addressing mode is used to complement the value of
destination register 07H (11110001B), leaving the new value 0EH (00001110B).
6 -1 7
SAM88RI INSTRUCTION SET
CP
S3C9688/P9688
— Compare
CP
dst,src
Operation:
dst – src
The source operand is compared to (subtracted from) the destination operand, and the appropriate
flags are set accordingly. The contents of both operands are unaffected by the comparison.
Flags:
C:
Set if a "borrow" occurred (src > dst); cleared otherwise.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result is negative; cleared otherwise.
V:
Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and
the sign of the result is of the same as the sign of the source operand; cleared otherwise.
D:
Unaffected.
H:
Unaffected.
F o r m a t:
Bytes
opc
dst | src
opc
src
opc
Examples:
1.
dst
Cycles
2
dst
3
src
3
Opcode
Addr Mode
(Hex)
dst
src
4
A2
r
r
6
A3
r
lr
6
A4
R
R
6
A5
R
IR
6
A6
R
IM
Given: R1 = 02H and R2 = 03H:
CP
R1,R2
→
Set the C and S flags
Destination working register R1 contains the value 02H and source register R2 contains the value
03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value
(destination/minuend). Because a "borrow" occurs and the difference is negative, C and S are "1".
2.
Given:
SKIP
R1 = 05H and R2 = 0AH:
CP
R1,R2
JP
UGE,SKIP
INC
R1
LD
R3,R1
In this example, destination working register R1 contains the value 05H which is less than the
contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1"
and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1"
executes, the value 06H remains in working register R3.
6 -1 8
S3C9688/P9688
DEC
S A M 8 8RCRI INSTRUCTION SET
— Decrement
DEC
dst
Operation:
dst ← dst – 1
The contents of the destination operand are decremented by one.
Flags:
C:
Unaffected.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if result is negative; cleared otherwise.
V:
Set if arithmetic overflow occurred, that is, dst value is – 128(80H) and result value
is +127 (7FH); cleared otherwise.
D:
Unaffected.
H:
Unaffected.
Format:
Bytes
opc
Examples:
Given:
dst
2
Cycles
Opcode
Addr Mode
(Hex)
dst
4
00
R
4
01
IR
R1 = 03H and register 03H = 10H:
DEC
R1
→
R1 = 02H
DEC
@R1
→
Register 03H = 0FH
In the first example, if working register R1 contains the value 03H, the statement "DEC R1"
decrements the hexadecimal value by one, leaving the value 02H. In the second example, the
statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one,
leaving the value 0FH.
6 -1 9
SAM88RI INSTRUCTION SET
DI
S3C9688/P9688
— Disable Interrupts
DI
Operation:
SYM (2) ← 0
Bit zero of the system mode register, SYM.2, is cleared to "0", glo bally disabling all interrupt
processing. Interrupt requests will continue to set their respective interrupt pending bits, but the
CPU will not service them while interrupt processing is disabled.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
Example:
Given:
1
SYM
=
4
8F
04H:
DI
If the value of the SYM register is 04H, the statement "DI" leaves the new value 00H in the register
and clears SYM.2 to "0", disabling interrupt processing.
6 -2 0
S3C9688/P9688
S A M 8 8RCRI INSTRUCTION SET
E I — Enable Interrupts
EI
Operation:
SYM (2) ← 1
An EI instruction sets bit 2 of the system mode register, SYM.2 to "1". This allows interrupts to be
serviced as they occur. If an interrupt's pending bit was set while interrupt processing was disabled
(by executing a DI instruction), it will be serviced when you execute the EI instruction.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
Example:
Given:
1
SYM
=
4
9F
00H:
EI
I f t h e S Y M r e g i s t e r c o n t a i n s t h e v a l u e 0 0 H , t h a t i s , i f i n t e rr u p t s a r e c u r r e n t l y d i s a b l e d , t h e s t a t e m e n t
"EI" sets the SYM register to 04H, enabling all interrupts (SYM.2 is the enable bit for global interrupt
processing).
6 -2 1
SAM88RI INSTRUCTION SET
IDLE
S3C9688/P9688
— Idle Operation
IDLE
Operation:
The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle
mode can be released by an interrupt request (IRQ) or an external reset operation.
Flags:
No flags are affected.
Format:
Bytes
opc
Example:
The instruction
IDLE
stops the CPU clock but not the system clock.
6 -2 2
1
Cycles
4
Opcode
Addr Mode
(Hex)
dst
src
6F
–
–
S3C9688/P9688
INC
S A M 8 8RCRI INSTRUCTION SET
— Increment
INC
dst
Operation:
dst ← dst + 1
The contents of the destination operand are incremented by one.
Flags:
C:
Unaffected.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result is negative; cleared otherwise.
V:
Set if arithmetic overflow occurred, that is dst value is +127(7FH) and result is –
128(80H); cleared otherwise.
D:
Unaffected.
H:
Unaffected.
F o rm a t :
Bytes
dst | opc
1
Cycles
4
Opcode
Addr Mode
(Hex)
dst
rE
r
r = 0 to F
opc
Examples:
Given:
dst
2
4
20
R
4
21
IR
R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH:
INC
R0
→
R0 = 1CH
INC
00H
→
Register 00H = 0DH
INC
@R0
→
R0 = 1BH, register 01H = 10H
In the first example, if destination working register R0 contains the value 1BH, the statement "INC
R0" leaves the value 1CH in that same register.
The next example shows the effect an INC instruction has on register 00H, assuming that it
contains the value 0CH.
In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of
register 1BH from 0FH to 10H.
6 -2 3
SAM88RI INSTRUCTION SET
IRET
S3C9688/P9688
— Interrupt Return
IRET
IRET
Operation:
FLAGS
← @SP
SP
← SP
PC
← @SP
SP
← SP + 2
+
1
SYM(2) ← 1
This instruction is used at the end of an interrupt service routine. It restores the flag register and the
p r o g r a m c o u n t e r . I t a l s o r e -e n a b l e s g l o b a l i n t e r r u p t s .
Flags:
All flags are restored to their original settings (that is, the settings before the interrupt occurred).
Format:
IRET
Bytes
Cycles
(Normal)
opc
6 -2 4
Opcode
(Hex)
1
6
BF
S3C9688/P9688
JP
S A M 8 8RCRI INSTRUCTION SET
— Jump
JP
cc,dst
(Conditional)
JP
dst
(Unconditional)
Operation:
If cc is true, PC ← d s t
The conditional JUMP instruction transfers program control to the destination address if the
condition specified by the condition code (cc) is true; otherwise, the instruction following the JP
i n s t r u c t i o n i s e x ec u t e d . T h e u n c o n d i t i o n a l J P s i m p l y r e p l a c e s t h e c o n t e n t s o f t h e P C w i t h t h e
contents of the specified register pair. Control then passes to the statement addressed by the PC.
Flags:
No flags are affected.
F o r m a t : (1)
Bytes
Cycles
(2)
cc | opc
dst
3
8 (3)
Opcode
Addr Mode
(Hex)
dst
ccD
DA
cc = 0 to F
opc
dst
2
8
30
IRR
NOTES:
1.
The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump.
2.
In the first byte of the three-byte instruction format (conditional jump), the condition code and the opcode are both
Examples:
Given:
four bits.
The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H:
JP
C,LABEL_W
→
LABEL_W = 1000H, PC = 1000H
JP
@00H
→
PC = 0120H
The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement
"JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to
that location. Had the carry flag not been set, control would then have passed to the statement
immediately following the JP instruction.
The second example shows an unconditional JP. The statement "JP @00" replaces the contents of
the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.
6 -2 5
SAM88RI INSTRUCTION SET
JR
S3C9688/P9688
— Jump Relative
JR
cc,dst
Operation:
If cc is true, PC ← P C +
dst
If the condition specified by the condition code (cc) is true, the relative address is added to the
program counter and control passes to the statement whose address is now in the program counter;
otherwise, the instruction following the JR instruction is executed (See list of condition codes).
The range of the relative address is +127, – 128, and the original value of the program counter is
taken to be the address of the first instruction byte following the JR statement.
Flags:
No flags are affected.
Format:
Bytes
Cycles
(1)
cc | opc
dst
2
6 (2)
Opcode
Addr Mode
(Hex)
dst
ccB
RA
cc = 0 to F
N O T E:
In the first byte of the two-byte instruction format, the condition code and the opcode are each four bits.
Example:
Given:
JR
The carry flag = "1" and LABEL_X = 1FF7H:
C,LABEL_X
→
PC = 1FF7H
If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will
pass control to the statement whose address is now in the PC. Otherwise, the program instruction
following the JR would be executed.
6 -2 6
S3C9688/P9688
LD
S A M 8 8RCRI INSTRUCTION SET
— Load
LD
dst,src
Operation:
dst ← src
The contents of the source are loaded into the destination. The source's c ontents are unaffected.
Flags:
No flags are affected.
Format:
Bytes
dst | opc
src | opc
src
2
dst
2
Cycles
Opcode
Addr Mode
(Hex)
dst
src
4
rC
r
IM
4
r8
r
R
4
r9
R
r
r = 0 to F
opc
opc
opc
dst | src
src
dst
2
dst
src
3
3
4
C7
r
lr
4
D7
Ir
r
6
E4
R
R
6
E5
R
IR
6
E6
R
IM
6
D6
IR
IM
opc
src
dst
3
6
F5
IR
R
opc
dst | src
x
3
6
87
r
x [r]
opc
src | dst
x
3
6
97
x [r]
r
6 -2 7
SAM88RI INSTRUCTION SET
LD
S3C9688/P9688
— Load
LD
(Continued)
Examples:
Given:
R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H,
register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH:
6 -2 8
LD
R0,#10H
→
R0 = 10H
LD
R0,01H
→
R0 = 20H, register 01H = 20H
LD
01H,R0
→
Register 01H = 01H, R0 = 01H
LD
R1,@R0
→
R1 = 20H, R0 = 01H
LD
@R0,R1
→
R0 = 01H, R1 = 0AH, register 01H = 0AH
LD
00H,01H
→
Register 00H = 20H, register 01H = 20H
LD
02H,@00H
→
Register 02H = 20H, register 00H = 01H
LD
00H,#0AH
→
Register 00H = 0AH
LD
@00H,#10H
→
Register 00H = 01H, register 01H = 10H
LD
@00H,02H
→
Register 00H = 01H, register 01H = 02, register 02H = 02H
LD
R0,#LOOP[R1]
→
R0 = 0FFH, R1 = 0AH
LD
#LOOP[R0],R1
→
Register 31H = 0AH, R0 = 01H, R1 = 0AH
S3C9688/P9688
S A M 8 8RCRI INSTRUCTION SET
LDC/LDE
— Load Memory
LDC/LDE
dst,src
Operation:
dst ← src
T h i s i n s t r u c t i o n l o a d s a b y t e f r o m p r o g r a m o r d a t a m e m o r y i n t o a w o r k i n g r e g i s t e r o r v i c e-v e r s a . T h e
source values are unaffected. LDC refers to program m emory and LDE to data memory. The
assembler makes 'Irr' or 'rr' values an even number for program memory and an odd number for data
memory.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
Addr Mode
(Hex)
dst
src
1.
opc
dst | src
2
10
C3
r
Irr
2.
opc
src | dst
2
10
D3
Irr
r
3.
opc
dst | src
XS
3
12
E7
r
XS [rr]
4.
opc
src | dst
XS
3
12
F7
XS [rr]
r
5.
opc
dst | src
XL
H
4
14
A7
r
XL [rr]
6.
opc
src | dst
XL
H
4
14
B7
XL [rr]
r
7.
opc
dst | 0000
DA
H
4
14
A7
r
DA
8.
opc
src | 0000
DA
H
4
14
B7
DA
r
9.
opc
dst | 0001
DA
H
4
14
A7
r
DA
10.
opc
src | 0001
DA
H
4
14
B7
DA
r
L
L
L
L
L
L
XL
XL
DA
DA
DA
DA
NOTES:
1.
The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0–1.
2.
For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are each one byte.
3.
For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two bytes.
4.
The DA and r source values for formats 7 and 8 are used to address program memory; the second set of values,
used in formats 9 and 10, are used to address data memory.
6 -2 9
SAM88RI INSTRUCTION SET
LDC/LDE
S3C9688/P9688
— Load Memory
LDC/LDE
(Continued)
Examples:
Given:
R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R5 = 60H; Program memory
locations 0061 = AAH, 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H.
External data memory locations 0061H = BBH, 0103H = 5FH, 0104H = 2AH, 0105H = 7DH,
and 1104H = 98H:
LDC
R0,@RR2
;
;
LDE
R0,@RR2
LDC *
LDE
@RR2,R0
LDC
R0,#01H[RR4]
LDE
LDC
@RR2,R0
R0,#01H[RR4]
(note)
#01H[RR4],R0
LDE
#01H[RR4],R0
LDC
R0,#1000H[RR2]
LDE
R0,#1000H[RR2]
;
R0 ← contents of external data memory location 0104H
R0 = 2AH, R2 = 01H, R3 = 04H
;
11H (contents of R0) is loaded into program memory
;
location 0104H (RR2),
;
;
working registers R0, R2, R3 → no change
11H (contents of R0) is loaded into external data memory
;
location 0104H (RR2),
;
;
working registers R0, R2, R3 → no change
R0 ← contents of program memory location 0061H
;
(01H + RR4),
;
R0 = AAH, R2 = 00H, R3 = 60H
;
;
R0 ← contents of external data memory location 0061H
(01H + RR4), R0 = BBH, R4 = 00H, R5 = 60H
;
11H (contents of R0) is loaded into program memory location
;
0061H (01H + 0060H)
;
11H (contents of R0) is loaded into external data memory
;
location 0061H (01H + 0060H)
;
R0 ← contents of program memory location 1104H
(1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H
;
;
;
;
R0,1104H
;
LDE
R0,1104H
;
R0 ← contents of program memory location 1104H, R0 = 88H
R0 ← contents of external data memory location 1104H,
;
R0 = 98H
;
11H (contents of R0) is loaded into program memory location
;
;
1105H, (1105H) ← 11H
11H (contents of R0) is loaded into external data memory
;
location 1105H, (1105H) ← 11H
LDE
6 -3 0
R0 ← contents of external data memory location 1104H
(1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H
LDC
LDC
NOTE:
R0 ← contents of program memory location 0104H
R0 = 1AH, R2 = 01H, R3 = 04H
(note)
1105H,R0
1105H,R0
These instructions are not supported by masked ROM type devices.
S3C9688/P9688
S A M 8 8RCRI INSTRUCTION SET
LDCD/LDED
— Load Memory and Decrement
LDCD/LDED
dst,src
Operation:
dst ← src
rr ← rr – 1
These instructions are used for user stacks or block transfers of data from program or data memory
to the register file. The address of the memory location is specified by a working register pair. The
contents of the source location are loaded into the destination location. The memory address is then
decremented. The contents of the source are unaffected.
LDCD references program memory and LDED references external data memory. The assembler
makes ‘Irr’ an even number for program memory and an odd number for data memory.
Flags:
No flags are affected.
Format:
Bytes
opc
Examples:
Given:
dst | src
2
Cycles
Opcode
10
Addr Mode
(Hex)
dst
src
E2
r
Irr
R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and
external data memory location 1033H = 0DDH:
LDCD
LDED
R8,@RR6
R8,@RR6
;
0CDH (contents of program memory location 1033H) is loaded
;
into R8 and RR6 is decremented by one
;
R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 ← RR6 – 1)
;
0DDH (contents of data memory location 1033H) is loaded
;
into R8 and RR6 is decremented by one (RR6 ← RR6 – 1)
;
R8 = 0DDH, R6 = 10H, R7 = 32H
6 -3 1
SAM88RI INSTRUCTION SET
LDCI/LDEI
S3C9688/P9688
— Load Memory and Increment
LDCI/LDEI
dst,src
Operation:
dst ← src
rr ← r r + 1
These instructions are used for user stacks or block transfers of data from program or data memory
to the register file. The address of the memory location is specified by a working register pair. The
contents of the source location are loaded into the destination location. The memory address is then
incremented automatically. The contents of the source are unaffected.
LDCI refers to program memory and LDEI refers to external data mem ory. The assembler makes 'Irr'
even for program memory and odd for data memory.
Flags:
No flags are affected.
Format:
Bytes
opc
Examples:
Given:
dst | src
2
Cycles
10
Opcode
Addr Mode
(Hex)
dst
src
E3
r
Irr
R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and
1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H:
LDCI
LDEI
6 -3 2
R8,@RR6
R8,@RR6
;
0CDH (contents of program memory location 1033H) is loaded
;
into R8 and RR6 is incremented by one (RR6 ← RR6 + 1)
;
R8 = 0CDH, R6 = 10H, R7 = 34H
;
0DDH (contents of data memory location 1033H) is loaded
;
into R8 and RR6 is incremented by one (RR6 ← RR6 + 1)
;
R8 = 0DDH, R6 = 10H, R7 = 34H
S3C9688/P9688
NOP
S A M 8 8RCRI INSTRUCTION SET
— No Operation
NOP
Operation:
No action is performed when the CPU executes this instruction. Typically, one or more NOPs are
executed in sequence in order to effect a timing delay of variable duration.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
Example:
1
4
FF
When the instruction
NOP
is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution
time.
6 -3 3
SAM88RI INSTRUCTION SET
OR
S3C9688/P9688
— Logical OR
OR
dst,src
Operation:
dst ← dst OR src
The source operand is logically ORed with the destination operand and the result is stored in the
destination. The contents of the source are unaffected. The OR operation results in a "1" being
stored whenever either of the corresponding bits in the two operands is a "1"; otherwis e a "0" is
stored.
Flags:
C:
Unaffected.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Always cleared to "0".
D:
Unaffected.
H:
Unaffected.
Format:
Bytes
opc
dst | src
opc
src
opc
Examples:
Given:
dst
2
dst
src
3
3
Cycles
Opcode
Addr Mode
(Hex)
dst
src
4
42
r
r
6
43
r
lr
6
44
R
R
6
45
R
IR
6
46
R
IM
R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and
register 08H = 8AH:
OR
R0,R1
→
R0 = 3FH, R1 = 2AH
OR
R0,@R2
→
R0 = 37H, R2 = 01H, register 01H = 37H
OR
00H,01H
→
Register 00H = 3FH, register 01H = 37H
OR
01H,@00H
→
Register 00H = 08H, register 01H = 0BFH
OR
00H,#02H
→
Register 00H = 0AH
In the first example, if working register R0 contains the value 15H and register R1 the value 2AH, the
s t a t e m e n t " O R R 0 , R 1 " l o g i c a l-O R s t h e R 0 a n d R 1 r e g i s t e r c o n t e n t s a n d s t o r e s t h e r e s u l t ( 3 F H ) i n
destination register R0.
The other examples show the use of the logical OR instruction with the various addressing modes
and formats.
6 -3 4
S3C9688/P9688
POP
S A M 8 8RCRI INSTRUCTION SET
— POP From Stack
POP
dst
Operation:
dst ← @ S P
← SP + 1
SP
The contents of the location addressed by the stack pointer are loaded into the destination. The
stack pointer is then incremented by one.
Flags:
No flags affected.
Format:
Bytes
opc
Examples:
Given:
dst
2
Cycles
Opcode
Addr Mode
(Hex)
dst
8
50
R
8
51
IR
Register 00H = 01H, register 01H = 1BH, SP (0D9H) = 0BBH, and stack register 0BBH
= 55H:
POP
00H
→
Register 00H = 55H, SP = 0BCH
POP
@00H
→
Register 00H = 01H, register 01H = 55H, SP = 0BCH
In the first example, general register 00H contains the value 01H. The statement "POP 00H" loads
the contents of location 0BBH (55H) into destination register 00H and then increments the stack
pointer by one. Register 00H then contains the value 55H and the SP points to location 0BCH.
6 -3 5
SAM88RI INSTRUCTION SET
PUSH
S3C9688/P9688
— Push To Stack
PUSH
src
Operation:
SP
← SP – 1
@ SP
← src
A PUSH instruction decrements the stack pointer value and loads the contents of the source (src)
into the location addressed by the decremented stack pointer. The operation then adds the new
value to the top of the stack.
Flags:
No flags are affected.
Format:
Bytes
opc
Examples:
Given:
PUSH
src
2
Opcode
Addr Mode
(Hex)
dst
8
70
R
8
71
IR
Register 40H = 4FH, register 4FH = 0AAH, SP = 0C0H:
40H
→
Register 40H = 4FH, stack register 0BFH = 4FH,
SP
PUSH
Cycles
@40H
→
=
0BFH
Register 40H = 4FH, register 4FH = 0AAH, stack register
0BFH = 0AAH, SP = 0BFH
In the first example, if the stack pointer contains the value 0C0H, and general register 40H the value
4FH, the statement "PUSH 40H" decrements the stack pointer from 0C0 to 0BFH. It then loads the
contents of register 40H into location 0BFH. Register 0BFH then contains the value 4FH and SP
points to location 0BFH.
6 -3 6
S3C9688/P9688
RCF
S A M 8 8RCRI INSTRUCTION SET
— Reset Carry Flag
RCF
RCF
Operation:
C ← 0
T h e c a r r y f l a g i s c l e a re d t o l o g i c z e r o , r e g a r d l e s s o f i t s p r e v i o u s v a l u e .
Flags:
C:
Cleared to "0".
No other flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
Example:
Given:
1
4
CF
C = "1" or "0":
The instruction RCF clears the carry flag (C) to logic zero.
6 -3 7
SAM88RI INSTRUCTION SET
RET
S3C9688/P9688
— Return
RET
Operation:
PC
← @SP
SP
← SP + 2
The RET instruction is normally used to return to the previously executing procedure at the end of a
procedure entered by a CALL instruction. The contents of the location addre ssed by the stack
pointer are popped into the program counter. The next statement that is executed is the one that is
addressed by the new program counter value.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
Example:
Given:
RET
1
8
AF
SP = 0BCH, (SP) = 101AH, and PC = 1234:
→
PC = 101AH, SP = 0BEH
The statement "RET" pops the contents of stack pointer location 0BCH (10H) into the high byte of
the program counter. The stack pointer then pops the value in location 0BDH (1AH) into the PC's
low byte and the instruction at location 101AH is executed. The stack pointer now points to memory
location 0BEH.
6 -3 8
S3C9688/P9688
RL
S A M 8 8RCRI INSTRUCTION SET
— Rotate Left
RL
dst
Operation:
C ← dst (7)
dst (0) ← dst (7)
dst (n + 1) ← dst (n), n = 0– 6
The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is
moved to the bit zero (LSB) position and also replaces the carry flag.
7
0
C
Flags:
C:
Set if the bit rotated from the most significant bit position (bit 7) was "1".
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D:
Unaffected.
H:
Unaffected.
Format:
Bytes
opc
Examples:
Given:
dst
2
Cycles
Opcode
Addr Mode
(Hex)
dst
4
90
R
4
91
IR
Register 00H = 0AAH, register 01H = 02H and register 02H = 17H:
RL
00H
→
Register 00H = 55H, C = "1"
RL
@01H
→
Register 01H = 02H, register 02H = 2EH, C = "0"
In the first example, if general register 00H contains the value 0AAH (10101010B), the statement
"RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B) and
setting the carry and overflow flags.
6 -3 9
SAM88RI INSTRUCTION SET
RLC
S3C9688/P9688
— Rotate Left Through Carry
RLC
dst
Operation:
dst (0) ← C
C ← dst (7)
dst (n + 1) ← dst (n), n = 0– 6
The contents of the destination operand with the carry flag are rotated left one bit position. The initial
value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.
7
0
C
Flags:
C:
Set if the bit rotated from the most significant bit position (bit 7) was "1".
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwis e.
D:
Unaffected.
H:
Unaffected.
Format:
Bytes
opc
Examples:
Given:
dst
2
Cycles
Opcode
Addr Mode
(Hex)
dst
4
10
R
4
11
IR
Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0":
RLC
00H
→
Register 00H = 54H, C = "1"
RLC
@01H
→
Register 01H = 02H, register 02H = 2EH, C = "0"
In the first example, if general register 00H has the value 0AAH (10101010B), the statement "RLC
00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the
initial value of the C flag replaces bit zero of register 00H, leaving the value 55H (01010101B). The
MSB of register 00H resets the carry flag to "1" and sets the overflow flag.
6 -4 0
S3C9688/P9688
RR
S A M 8 8RCRI INSTRUCTION SET
— Rotate Right
RR
dst
Operation:
C ← dst (0)
dst (7) ← dst (0)
dst (n) ← dst (n + 1), n = 0– 6
The contents of the destination operand are rotated right one bit position. The initial value of bit zero
(LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
7
0
C
Flags:
C:
Set if the bit rotated from the least significant bit position (bit zero) was "1".
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D:
Unaffected.
H:
Unaffected.
Format:
Bytes
opc
Examples:
Given:
dst
Cycles
2
Opcode
Addr Mode
(Hex)
dst
4
E0
R
4
E1
IR
Register 00H = 31H, register 01H = 02H, and register 02H = 17H:
RR
00H
→
Register 00H = 98H, C = "1"
RR
@01H
→
Register 01H = 02H, register 02H = 8BH, C = "1"
In the first example, if general register 00H contains the value 31H (00110001B), the statement "RR
00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7,
leaving the new value 98H (10011000B) in the destination register. The initial bit zero also resets the
C flag to "1" and the sign flag and overflow flag are also set to "1".
6 -4 1
SAM88RI INSTRUCTION SET
RRC
S3C9688/P9688
— Rotate Right Through Carry
RRC
dst
Operation:
dst (7) ← C
C ← dst (0)
dst (n) ← dst (n + 1), n = 0– 6
The contents of the destination operand and the carry flag are rotated right one bit position. The
initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7
(MSB).
7
0
C
Flags:
C:
Set if the bit rotated from the least significant bit position (bit zero) was "1".
Z:
Set if the result is "0" cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D:
Unaffected.
H:
Unaffected.
Format:
Bytes
opc
Examples:
Given:
dst
2
Cycles
Opcode
Addr Mode
(Hex)
dst
4
C0
R
4
C1
IR
Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0":
RRC
00H
→
Register 00H = 2AH, C = "1"
RRC
@01H
→
Register 01H = 02H, register 02H = 0BH, C = "1"
In the first example, if general register 00H contains the value 55H (01010101B), the statement
"RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1") replaces
the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH
(00101010B) in destination register 00H. The sign flag and overflow flag are both cleared to "0".
6 -4 2
S3C9688/P9688
SBC
S A M 8 8RCRI INSTRUCTION SET
— Subtract With Carry
SBC
dst,src
Operation:
dst ← dst –
src –
c
The source operand, along with the current value of the carry flag, is subtracted from the destination
operand and the result is stored in the destination. The contents of the source are unaffected.
S u b t r a c t i o n i s p e r f o r m e d b y a d d i n g t h e t w o ' s -c o m p l e m e n t o f t h e s o u r c e o p e r a n d t o t h e d e s t i n a t i o n
operand. In multiple precision arithmetic, this instruction permits the carry ("borrow") from the
s u b t r a c t i o n o f t h e l o w -o r d e r o p e r a n d s t o b e s u b t r a c t e d f r o m t h e s u b t r a c t i o n o f h i g h -o r d e r o p e r a n d s .
Flags:
C:
Set if a borrow occurred (src > dst); cleared otherwise.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result is negative; cleared otherwise.
V:
Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the
sign of the result is the same as the sign of the source; cleared otherwise.
D:
Always set to "1".
H:
C l e a r e d i f t h e r e i s a c a r r y f r o m t h e m o s t s i g n i f i c a n t b i t o f t h e l o w -o r d e r f o u r b i t s o f t h e
result; set otherwise, indicating a "borrow".
Format:
Bytes
opc
dst | src
opc
src
opc
Examples:
Given:
dst
2
dst
src
3
3
Cycles
Opcode
Addr Mode
(Hex)
dst
src
4
32
r
r
6
33
r
lr
6
34
R
R
6
35
R
IR
6
36
R
IM
R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register
03H = 0AH:
SBC
R1,R2
→
R1 = 0CH, R2 = 03H
SBC
R1,@R2
→
R1 = 05H, R2 = 03H, register 03H = 0AH
SBC
01H,02H
→
Register 01H = 1CH, register 02H = 03H
SBC
01H,@02H
→
Register 01H = 15H,register 02H = 03H, register 03H = 0AH
SBC
01H,#8AH
→
Register 01H = 95H; C, S, and V = "1"
In the first example, if working register R1 contains the value 10H and register R2 the value 03H, the
statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the
destination (10H) and then stores the result (0CH) in register R1.
6 -4 3
SAM88RI INSTRUCTION SET
SCF
S3C9688/P9688
— Set Carry Flag
SCF
Operation:
C ← 1
The carry flag (C) is set to logic one, regardless of its previous value.
Flags:
C:
Set to "1".
No other flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
Example:
The statement
SCF
sets the carry flag to logic one.
6 -4 4
1
4
DF
S3C9688/P9688
SRA
S A M 8 8RCRI INSTRUCTION SET
— Shift Right Arithmetic
SRA
dst
Operation:
dst (7) ← dst (7)
C ← dst (0)
dst (n) ← dst (n + 1), n = 0– 6
A n a r i t h m e t i c s h i f t -r i g h t o f o n e b i t p o s i t i o n i s p e r f o r m e d o n t h e d e s t i n a t i o n o p e r a n d . B i t z e r o ( t h e
LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit
position 6.
7
6
0
C
Flags:
C:
Set if the bit shifted from the LSB position (bit zero) was "1".
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result is negative; cleared otherwise.
V:
Always cleared to "0".
D:
Unaffected.
H:
Unaffected.
Format:
Bytes
opc
Examples:
Given:
dst
2
Cycles
Opcode
Addr Mode
(Hex)
dst
4
D0
R
4
D1
IR
Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1":
SRA
00H
→
Register 00H = 0CD, C = "0"
SRA
@02H
→
Register 02H = 03H, register 03H = 0DEH, C = "0"
In the first example, if general register 00H contains the value 9AH (10011010B), the statement
"SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C flag
and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the value
0CDH (11001101B) in destination register 00H.
6 -4 5
SAM88RI INSTRUCTION SET
STOP
S3C9688/P9688
— Stop Operation
STOP
Operation:
The STOP instruction stops both the CPU clock and system clock and causes the microcontroller
t o e n t e r S t o p m o d e . D u r i n g S t o p m o d e , t h e c o n t e n t s o f o n -c h i p C P U r e g i s t e r s , p e r i p h e r a l r e g i s t e r s ,
and I/O port control and data registers are retained. Stop mode can be released by an external reset
o p e r a t i o n o r E x t e r n a l i n t e r r u p t i n p u t . F o r t h e r e s e t o p e r a t i o n , t h e RESET p i n m u s t b e h e l d t o L o w l e v e l
until the required oscillation stabilization interval has elapsed.
Flags:
No flags are affected.
Format:
Bytes
opc
Example:
The statement
STOP
halts all microcontroller operations.
6 -4 6
1
Cycles
4
Opcode
Addr Mode
(Hex)
dst
src
7F
–
–
S3C9688/P9688
SUB
S A M 8 8RCRI INSTRUCTION SET
— Subtract
SUB
dst,src
Operation:
dst ← dst – src
The source operand is subtracted from the destination operand and the result is stored in the
destination. The contents of the source are unaffected. Subtraction is performed by adding the two's
complement of the source operand to the destination operand.
Flags:
C:
Set if a "borrow" occurred; cleared otherwise.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the re sult is negative; cleared otherwise.
V:
Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the
sign of the result is of the same as the sign of the source operand; cleared otherwise.
D:
Always set to "1".
H:
C l e a r e d i f t h e r e i s a c a r r y f r o m t h e m o s t s i g n i f i c a n t b i t o f t h e l o w -o r d e r f o u r b i t s o f t h e
result; set otherwise indicating a "borrow".
Format:
Bytes
opc
opc
opc
Examples:
Given:
dst | src
src
dst
2
dst
src
3
3
Cycles
Opcode
Addr Mode
(Hex)
dst
src
4
22
r
r
6
23
r
lr
6
24
R
R
6
25
R
IR
6
26
R
IM
R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
SUB
R1,R2
→
R1 = 0FH, R2 = 03H
SUB
R1,@R2
→
R1 = 08H, R2 = 03H
SUB
01H,02H
→
Register 01H = 1EH, register 02H = 03H
SUB
01H,@02H
→
Register 01H = 17H, register 02H = 03H
SUB
01H,#90H
→
Register 01H = 91H; C, S, and V = "1"
SUB
01H,#65H
→
R e g i s t e r 0 1 H = 0 B CH ; C a n d S = " 1 " , V = " 0 "
In the first example, if working register R1 contains the value 12H and if register R2 contains the
value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination value
(12H) and stores the result (0FH) in destination register R1.
6 -4 7
SAM88RI INSTRUCTION SET
TCM
S3C9688/P9688
— Test Complement Under Mask
TCM
dst,src
Operation:
(NOT dst) AND src
This instruction tests selected bits in the destination operand for a logic one value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of the source operand (mask).
The TCM statement complements the destination operand, which is then ANDed with the source
mask. The zero (Z) flag can then be checked to determine the result. The destination and source
operands are unaffected.
Flags:
C:
Unaffected.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Always cleared to "0".
D:
Unaffected.
H:
Unaffected.
Format:
Bytes
opc
opc
opc
Examples:
Given:
dst | src
src
dst
Cycles
2
dst
src
3
3
Opcode
Addr Mode
(Hex)
dst
src
4
62
r
r
6
63
r
lr
6
64
R
R
6
65
R
IR
6
66
R
IM
R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and
register 02H = 23H:
TCM
R0,R1
→
R0 = 0C7H, R1 = 02H, Z = "1"
TCM
R0,@R1
→
R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"
TCM
00H,01H
→
Register 00H = 2BH, register 01H = 02H, Z = "1"
TCM
00H,@01H
→
R e g i s t e r 0 0 H = 2 B H, r e g i s t e r 0 1 H = 0 2 H ,
register 02H = 23H, Z = "1"
TCM
00H,#34
→
Register 00H = 2BH, Z = "0"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the
value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register for a
"1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one and can
be tested to determine the result of the TCM operation.
6 -4 8
S3C9688/P9688
TM
S A M 8 8RCRI INSTRUCTION SET
— Test Under Mask
TM
dst,src
Operation:
dst AND src
This instruction tests selected bits in the destination operand for a logic zero value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of the source operand (mask),
which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine
the result. The destination and source operands are unaffected.
Flags:
C:
Unaffected.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Always reset to "0".
D:
Unaffected.
H:
Unaffected.
Format:
Bytes
opc
opc
opc
Examples:
Given:
dst | src
src
dst
Cycles
2
dst
src
3
3
Opcode
Addr Mode
(Hex)
dst
src
4
72
r
r
6
73
r
lr
6
74
R
R
6
75
R
IR
6
76
R
IM
R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and
register 02H = 23H:
TM
R0,R1
→
R0 = 0C7H, R1 = 02H, Z = "0"
TM
R0,@R1
→
R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"
TM
00H,01H
→
Register 00H = 2BH, register 01H = 02H, Z = "0"
TM
00H,@01H
→
Register 00H = 2BH, register 01H = 02H,
register 02H = 23H, Z = "0"
TM
00H,#54H
→
Register 00H = 2BH, Z = "1"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the
value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register for a "0"
value. Because the mask value does not match the test bit, the Z flag is cleared to logic zero and
can be tested to determine the result of the TM operation.
6 -4 9
SAM88RI INSTRUCTION SET
XOR
S3C9688/P9688
— Logical Exclusive OR
XOR
dst,src
Operation:
dst ← dst XOR src
T h e s o u r c e o p e r a n d i s l o g i c a l l y e x c l u s i v e -O R e d w i t h t h e d e s t i n a t i o n o p e r a n d a n d t h e r e s u l t i s s t o r e d
i n t h e d e s t i n a t i o n . T h e e x c l u s i v e -O R o p e r a t i o n r e s u l t s i n a " 1 " b i t b e i n g s t o r e d w h e n e v e r t h e
corresponding bits in the operands are different; otherwise, a "0" bit is stored.
Flags:
C:
Unaffected.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Always reset to "0".
D:
Unaffected.
H:
Unaffected.
Format:
Bytes
opc
opc
opc
Examples:
Given:
dst | src
src
dst
2
dst
src
3
3
Cycles
Opcode
Addr Mode
(Hex)
dst
src
4
B2
r
r
6
B3
r
lr
6
B4
R
R
6
B5
R
IR
6
B6
R
IM
R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and
register 02H = 23H:
XOR
R0,R1
→
R0 = 0C5H, R1 = 02H
XOR
R0,@R1
→
R0 = 0E4H, R1 = 02H, register 02H = 23H
XOR
00H,01H
→
Register 00H = 29H, register 01H = 02H
XOR
00H,@01H
→
Register 00H = 08H, register 01H = 02H, register 02H = 23H
XOR
00H,#54H
→
Register 00H = 7FH
In the first example, if working register R0 contains the value 0C7H and if register R1 contains the
v a l u e 0 2 H , t h e s t a t e m e n t " X O R R 0 , R 1 " l o g i c a l l y e x c l u s i v e -O R s t h e R 1 v a l u e w i t h t h e R 0 v a l u e a n d
stores the result (0C5H) in the destination register R0.
6 -5 0
S3C9688/P9688
7
CLOCK CIRCUIT
CLOCK CIRCUIT
OVERVIEWAE
The crystal or ceramic oscillation source provides a maximum 6 MHz clock for the S3C9688/P9688. The X
IN
and X
OUT
p i n s a r e c o n n e c t e d w i t h t h e o s c i l l a t i o n s o u r c e t o t h e o n -c h i p c l o c k c i r c u i t .
X IN
6 MHz
S3C9688/P9688
X OUT
F i g u r e 7 -1 . M a i n O s c i l l a t o r C i r c u i t ( C r y s t a l / C e r a m i c O s c i l l a t o r )
M A I N O S C I L L A T O R L O G IC
T o i n c r e a s e p r o c e s s i n g s p e e d a n d t o r e d u c e c l o c k n o i s e , n o n -d i v i d e d l o g i c i s i m p l e m e n t e d f o r t h e m a i n o s c i l l a t o r
circuit. For this reason, very high resolution waveforms (square signal edges) must be generated in order for the CPU
to efficiently process logic operations.
C L O C K S T A T U S D U R I N G P O W E R -D O W N M O D E S
T h e t w o p o w e r-d o w n m o d e s , S t o p m o d e a n d I d l e m o d e , a f f e c t c l o c k o s c i l l a t i o n a s f o l l o w s :
—
In Stop mode, the main oscillator "freezes", halting the CPU and peripherals. The contents of the register file and
current system register values are retained. Stop mode is released, and the oscillator started, by a reset
o p e r a t i o n o r b y a n e x t e r n a l i n t e r r u p t w i t h R C -d e l a y n o i s e f i l t e r ( f o r S 3 C 9 6 8 8 / P 9 6 8 8 , I N T 0 – INT2).
—
In Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt control and the timer. The
c u r r e n t C P U s t a t u s i s p r e s er v e d , i n c l u d i n g s t a c k p o i n t e r , p r o g r a m c o u n t e r , a n d f l a g s . D a t a i n t h e r e g i s t e r f i l e i s
r e t a i n e d . I d l e m o d e i s r e l e a s e d b y a r e s e t o r b y a n i n t e r r u p t ( e x t e r n a l o r i n t e r n a l l y -g e n e r a t e d ) .
7 -1
CLOCK CIRCUIT
S3C9688/P9688
SYSTEM CLOCK CONTROL REGISTER (CLKCON)
The system clock control register, CLKCON, is located in location D4H. It is read/write addressable and has the
following functions:
—
O s c i l l a t o r I R Q w a k e-u p f u n c t i o n e n a b l e / d i s a b l e ( C L K C O N . 7 )
—
O s c i l l a t o r f r e q u e n c y d i v i d e -b y v a l u e : n o n -d i v i d e d , 2 , 8 o r 1 6 ( C L K C O N . 4 a n d C L K C O N . 3 )
The CLKCON register controls whether or not an external interrupt can be used to trigger a Stop mode release (This
i s c a l l e d t h e " I R Q w a k e-u p " f u n c t i o n ) . T h e I R Q w a k e-u p e n a b l e b i t i s C L K C O N . 7 .
A f t e r a r e s e t , t h e e x t e r n a l i n t e r r u p t o s c i l l a t o r w a k e-u p f u n c t i o n i s e n a b l e d , t h e m a i n o s c i l l a t o r i s a c t i v a t e d , a n d t h e
f
OSC
/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock
speed to f
OSC
, f
OSC
/2 or f /8.
s
System Clock Control Register (CLKCON)
D4H, R/W
MSB
.7
.6
.5
.4
.3
Oscillator IRQ wake-up enable bit:
.2
.1
oscillator wake-up function
oscillator wake-up function
Divide-by selection bits for
CPU clock frequency:
00 = f
OSC /16
01 = f
OSC /8
10 = f
OSC /2
11 = f
OSC
(non-divided)
Not used for S3C9688/P9688
F i g u r e 7 -2 . S y s t e m C l o c k C o n t r o l R e g i s t e r ( C L K C O N )
7 -2
LSB
Not used for S3C9688/P9688
0 = Enable IRQ for main-system
1 = Disable IRQ for main-system
.0
S3C9688/P9688
CLOCK CIRCUIT
Stop
CLKCON.3, .4
Instruction
Oscillator
Stop
Main
OSC
1/2
M
U
1/8
CPU Clock
X
P3.3/CLO
Oscillator
Wake-up
1/16
P3CON
Noise
Filter
CLKCON.7
INT Pin
F i g u r e 7 -3 . S y s t e m C l o c k C i r c u i t D i a g r a m
7 -3
CLOCK CIRCUIT
S3C9688/P9688
NOTES
7 -4
S3C9688/P9688
8
RESET AND POWER-D O W N
RESET A N D P O W E R -D O W N
SYSTEM RESET
OVERVIEW
D u r i n g a p o w e r-o n r e s e t , t h e v o l t a g e a t V
DD
i s H i g h l e v e l a n d t h e RESET p i n i s f o r c e d t o L o w l e v e l . T h e RESET s i g n a l i s
input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This brings the
S3C9688/P9688 into a known operating status.
The RESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance
in order to allow time for internal CPU clock oscillation to stabilize. The minimum required oscillation stabilization
t i m e f o r a r e s e t i s a p p r o x i m a t e l y 1 0 m s ( @ 2 16/ f
OSC
, f
OSC
= 6 MHz).
When a reset occurs during normal operation (with both V
DD
a n d RESET a t H i g h l e v e l ) , t h e s i g n a l a t t h e RESET p i n i s
forced Low and the reset operation starts. All system and peripheral control registers are then set to their default
h a r d w a r e r e s e t v a l u e s ( s e e T a b l e 8 -1 ) .
The following sequence of events occurs during a reset operation:
—
All interrupts are disabled.
—
The watchdog function (basic timer) is enabled.
—
P o r t s 0 -4 a r e s e t t o s c h m i t t t r i g g e r i n p u t m o d e a n d a l l p u l l -u p r e s i s t o r s a r e d i s a b l e d .
—
Peripheral control and data registers are disabled and reset to their initial values.
—
The program counter is loaded with the ROM reset address, 0100H.
—
When the programmed oscillation stabilization time interval has elapsed, the address stored in ROM location
0100H (and 0101H) is fetched and executed.
NOTE
To program the duration of the oscillation stabilization interval, you must make the appropriate settings to
the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the
basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you
can disable it by writing '1010B' to the upper nibble of BTCON.
8 -1
RESET AND POWER-D O W N
S3C9688/P9688
P O W E R -D O W N M O D E S
STOP MODE
Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all
p e r i p h e r a l s i s h a l t e d . T h a t i s , t h e o n -c h i p m a i n o s c i l l a t o r s t o p s a n d t h e s u p p l y c u r r e n t i s r e d u c e d t o l e s s t h a n
300
µA .
All system functions are halted when the clock "freezes", but data stored in the internal register fi le is
r e t a i n e d . S t o p m o d e c a n b e r e l e a s e d i n b o t h w a y s : b y a RESET s i g n a l o r b y a n e x t e r n a l i n t e r r u p t .
Using RESET to Release Stop Mode
S t o p m o d e i s r e l e a s e d w h e n t h e RESET s i g n a l i s r e l e a s e d a n d r e t u r n s t o H i g h l e v e l . A l l s y s t e m a n d p e r i p h e r a l c o n t r o l
registers are then reset to their default values and the contents of all data registers are retained. A reset operation
a u t o m a t i c a l l y s e l e c t s a s l o w c l o c k ( 1 / 1 6 ) b e c a u s e C L K C O N . 3 a n d C L K C O N . 4 a r e c l e a r e d t o ‘ 0 0 B ’ . A fter the
o s c i l l a t i o n s t a b i l i z a t i o n i n t e r v a l h a s e l a p s e d , t h e C P U e x e c u t e s t h e s y s t e m i n i t i a l i z a t i o n r o u t i n e b y f e t c h i n g t h e 1 6 -b i t
address stored in ROM locations 0100H and 0101H.
Using an External Interrupt to Release Stop Mode
O n l y e x t e r n a l i n t e r r u p t s w i t h a n R C -d e l a y n o i s e f i l t e r c i r c u i t c a n b e u s e d t o r e l e a s e S t o p m o d e ( C l o c k -r e l a t e d
external interrupts cannot be used). External interrupts INT0 – INT2 in the S3C9688/P9688 interrupt structure meet
this criteria.
Note that when Stop mode is released by an external interrupt, the current values in system and peripheral control
registers are not changed. When you use an interrupt to release Stop mode, the CLKCON.3 and CLKCON.4 register
values remain unchanged, and the currently selected clock value is used. If you use an external interrupt for Stop
mode release, you can also program the duration of the oscillation stabilization interval. To do this, you must make
t h e a p p r o p r i a t e c o n t r o l a n d c l o c k s e t t i n g s before e n t e r i n g S t o p m o d e .
The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service routine,
the instruction immediately following the one that initiated Stop mode is executed.
IDLE MODE
Idle mode is invoked by the instruction IDLE (opcode 6FH). In Idle mode, CPU operations are halted while select
peripherals remain active. During Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt logic
and timer/counters. Port pins retain the mode (input or output) they had at the time Idle mode was entered.
There are two ways to release Idle mode:
1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents of
all data registers are retained. The reset automatically selects a slow clock (1/16) because CLKCON.3 and
CLKCON.4 are cleared to ‘00B’. If interrupts are masked, a reset is the only way to release Idle mode.
2. Activate any enabled interrupt, causing Idle mode to be released. When you use an interrupt to release Idle
mode, the CLKCON.3 and CLKCON.4 register values remain unchanged, and the currently selected clock value
is used. The interrupt is then serviced. Following the IRET from the service routine, the instruction immediately
following the one that initiated Idle mode is executed.
NOTE
O n l y e x t e r n a l i n t e r r u p t s t h a t a r e n o t c l o c k -r e l a t e d c a n b e u s e d t o r e l e a s e S t o p m o d e . T o r e l e a s e I d l e m o d e ,
however, any type of interrupt (that is, internal or external) can be used.
8 -2
S3C9688/P9688
RESET AND POWER-D O W N
HARDWARE RESET VALUES
T a b l e s 8 -1 t h r o u g h 8 -3 l i s t t h e v a l u e s f o r C P U a n d s y s t e m r e g i s t e r s , p e r i p h e r a l c o n t r o l r e g i s t e r s a n d p e r i p h e r a l d a t a
registers following a reset operation in normal operating mode. The following notation is used in these tables to
represent specific reset values:

A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.

An 'x' means that the bit value is undefined following a reset.

A d a s h ( '-' ) m e a n s t h a t t h e b it i s e i t h e r n o t u s e d o r n o t m a p p e d .
T a b l e 8 -1 . R e g i s t e r V a l u e s a f t e r a R e s e t
Register Name
Mnemonic
Address
Bit Values after RESET
Dec
Hex
7
6
5
4
3
2
1
0
–
000– 191
00H–BFH
x
x
x
x
x
x
x
x
R0–R15
192– 207
C0H–CFH
x
x
x
x
x
x
x
x
T0CNT
208
D0H
0
0
0
0
0
0
0
0
Timer 0 data register
T0DATA
209
D1H
1
1
1
1
1
1
1
1
Timer 0 control register
T0CON
210
D2H
0
0
0
0
0
0
0
0
USXCON
211
D3H
0
0
0
0
0
0
0
0
Clock control register
CLKCON
212
D4H
0
0
0
0
0
0
0
0
System flags register
FLAGS
213
D5H
0
0
0
0
–
–
–
–
PS2DATA
214
D6H
0
0
0
0
0
0
0
0
PS2CONINT
214
D7H
0
0
0
0
0
0
0
0
P0INT
216
D8H
0
0
0
0
0
0
0
0
SP
217
D9H
x
x
x
x
x
x
x
x
P0PND
218
DAH
0
0
0
0
0
0
0
0
General purpose registers
Working registers
Timer 0 counter
USB selection and transceiver
crossover point control register
D + / P S 2 , D -/ P S 2 d a t a r e g i s t e r
(only PS2 mode)
PS2 control and interrupt
pending register
Port 0 interrupt control register
Stack pointer
Port 0 interrupt pending register
Location DBH is not mapped.
Basic timer control register
BTCON
220
DCH
0
0
0
0
0
0
0
0
Basic timer counter
BTCNT
221
DDH
0
0
0
0
0
0
0
0
Location DEH is not mapped.
System mode register
SYM
223
DFH
–
–
–
–
–
0
0
0
Port 0 data register
P0
224
E0H
0
0
0
0
0
0
0
0
Port 1 data register
P1
225
E1H
0
0
0
0
0
0
0
0
Port 2 data register
P2
226
E2H
0
0
0
0
0
0
0
0
Port 3 data register
P3
227
E3H
0
0
0
0
0
0
0
0
Port 4 data register
P4
228
E4H
0
0
0
0
0
0
0
0
8 -3
RESET AND POWER-D O W N
S3C9688/P9688
T a b l e 8 -1 . R e g i s t e r V a l u e s a f t e r a R e s e t ( c o n t i n u e d )
Bank 0 Register Name
Mnemonic
Address
Bit Values after a Reset
Dec
Hex
7
6
5
4
3
2
1
0
P3CON
229
E5H
0
0
0
0
0
0
0
0
Port 0 control register (high byte)
P0CONH
230
E6H
0
0
0
0
0
0
0
0
Port 0 control register (low byte)
P0CONL
231
E7H
0
0
0
0
0
0
0
0
Port 1 control register (high byte)
P1CONH
232
E8H
0
0
0
0
0
0
0
0
Port 1 control register (low byte)
P1CONL
233
E9H
0
0
0
0
0
0
0
0
Port 2 control register (h igh byte)
P2CONH
234
EAH
0
0
0
0
0
0
0
0
Port 2 control register (low byte)
P2CONL
235
EBH
0
0
0
0
0
0
0
0
P2INT
236
ECH
0
0
0
0
0
0
0
0
Port 2 interrupt pending register
P2PND
237
EDH
0
0
0
0
0
0
0
0
Port 4 control register
P4CON
238
EEH
0
0
0
0
0
0
0
0
P4INTPND
239
EFH
0
0
0
0
0
0
0
0
FADDR
240
F0H
0
0
0
0
0
0
0
0
Control endpoint status register
EP0CSR
241
F1H
0
0
0
0
0
0
0
0
Interrupt endpoint status register
EP1CSR
242
F2H
0
0
0
0
0
0
0
0
Control endpoint byte count register
EP0BCNT
243
F3H
0
0
0
0
0
0
0
0
Control endpoint FIFO register
EP0FIFO
244
F4H
x
x
x
x
x
x
x
x
Interrupt endpoint FIFO register
EP1FIFO
245
F5H
x
x
x
x
x
x
x
x
USB interrupt pending register
USBPND
246
F6H
0
0
0
0
0
0
0
0
USBINT
247
F7H
0
0
0
0
1
0
1
1
USB power management register
PWRMGR
248
F8H
0
0
0
0
0
0
0
0
Interrupt endpoint 2 control status
EP2CSR
249
F9H
0
0
0
0
0
0
0
0
Interrupt endpoint 2 FIFO register
EP2FIFO
250
FAH
x
x
x
x
x
x
x
x
Endpoint mode register
EPMODE
251
FBH
0
0
0
0
0
0
0
0
Endpoint 1 byte count
EP1BCNT
252
FCH
0
0
0
0
0
0
0
0
Endpoint 2 byte count
EP2BCNT
253
FDH
0
0
0
0
0
0
0
0
USB control register
USBCON
254
FEH
0
0
0
0
1
0
1
1
Port 3 control register
Port 2 interrupt enable register
Port 4 interrupt enable/pending register
USB function address register
USB interrupt enable register
register
Location FFH is not mapped
8 -4
S3C9688/P9688
9
I/O PORTS
I/O PORTS
OVERVIEW
The S3C9688/P9688 USB Mode has five I/O ports (0 – 4) with a total of 32 pins.
P S 2 M o d e h a s t w o I / O p o r t s ( D + / P S 2 , D -/ P S 2 ) w i t h a t o t a l o f 3 4 p i n s .
You can acces s these ports directly by writing or reading port data register addresses.
For keyboard applications, ports 0, 1 and 2 are usually configured as keyboard matrix input/output. Port 3 can be
configured as LED drive. Port 4 is used for host communication or for controlling a mouse or other external device.
T a b l e 9 -1 . S 3 C 9 6 8 8 / P 9 6 8 8 P o r t C o n f i g u r a t i o n O v e r v i e w
Port
0
Function Description
B i t -p r o g r a m m a b l e I / O p o r t f o r s c h m i t t t r i g g e r i n p u t o r o p e n -d r a i n o u t p u t .
Programmability
Bit
P o r t 0 c a n b e i n d i v i d u a l l y c o n f i g u r e d a s e x t e r n a l i n t e r r u p t i n p u t s . P u l l -u p
resistors are assignable by software.
1
B i t -p r o g r a m m a b l e I / O p o r t f o r s c h m i t t t r i g g e r i n p u t o r o p e n -d r a i n o u t p u t .
Bit
P u l l -u p r e s i s t o r s a r e a s s i g n a b l e b y s o f t w a r e .
2
B i t -p r o g r a m m a b l e I / O p o r t f o r s c h m i t t t r i g g e r i n p u t o r o p e n -d r a i n o u t p u t .
Bit
P o r t 2 c a n b e i n d i v i d u a l l y c o n f i g u r e d a s e x t e r n a l i n t e r r u p t i n p u t s . P u l l -u p
resistors are assignable by software.
3
B i t -p r o g r a m m a b l e I / O p o r t f o r s c h m i t t t ri g g e r i n p u t , o p e n -d r a i n o r p u s h-p u l l
Bit
output. P3.3 can be used to system clock output (CLO) pin.
4
B i t -p r o g r a m m a b l e I / O p o r t f o r s c h m i t t t r i g g e r i n p u t o r o p e n -d r a i n o u t p u t o r
Bit
p u s h-p u l l o u t p u t . P o r t 4 c a n b e i n d i v i d u a l l y c o n f i g u r e d a s e x t e r n a l i n t e r r u p t
i n p u t s . I n o u t p u t m o d e , p u l l -u p r e s i s t o r s a r e a s s i g n a b l e b y s o f t w a r e . B u t i n
i n p u t m o d e , p u l l -u p r e s i s t o r s a r e f i x e d .
D+/PS2
B i t -p r o g r a m m a b l e I / O p o r t f o r s c h m i t t t r i g g e r i n p u t o r o p e n -d r a i n o u t p u t o r
D -/ P S 2
p u s h-p u l l o u t p u t . T h i s p o r t i n d i v i d u a l l y c o n f i g u r e d a s e x t e r n a l i n t e r r u p t
(PS2 mode
Only)
Bit
i n p u t s . I n o u t p u t m o d e , p u l l -u p r e s i s t o r s a r e a s s i g n a b l e b y s o f t w a r e . B u t i n
i n p u t m o d e , p u l l -u p r e s i s t o r s a r e f i x e d .
9 -1
I/O PORTS
S3C9688/P9688
PORT DATA REGISTERS
T a b l e 9 -2 g i v e s y o u a n o v e r v i e w o f t h e p o r t d a t a r e g i s t e r n a m e s , l o c a t i o n s a n d a d d r e s s i n g c h a r a c t e r i s t i c s . D a t a
r e g i s t e r s f o r p o r t s 0 – 4 h a v e t h e s t r u c t u r e s h o w n i n F i g u r e 9 -1 .
T a b l e 9 -2 . P o r t D a t a R e g i s t e r S u m m a r y
Register Na m e
Mnemonic
Decimal
Hex
R/W
Port 0 data register
P0
224
E0H
R/W
Port 1 data register
P1
225
E1H
R/W
Port 2 data register
P2
226
E2H
R/W
Port 3 data register
P3
227
E3H
R/W
Port 4 data register
P4
228
E4H
R/W
I/O Port n Data Register (n = 0-4)
MSB
.7
.6
Pn.7
NOTE:
NOTE:
Pn.6
.5
Pn.5
.4
Pn.4
.3
Pn.3
.2
Pn.2
.1
Pn.1
.0
Pn.0
Becauseonly
onlythe
thefour
fourlower-nibble
lower-nibblepins
pinsofofport
port3 3
Because
andport
port4 4are
aremapped,
mapped,data
dataregister
registerbits
bitsP3.4-P3.7
P3.4-P3.7
and
andP4.4-P4.7
P4.4-P4.7are
arenot
notused.
used.
and
F i g u r e 9 -1 . P o r t D a t a R e g i s t e r F o r m a t
9 -2
LSB
S3C9688/P9688
I/O PORTS
PORT 0 AND PORT 1
P o r t s 0 b i t -p r o g r a m m a b l e , g e n e r a l-p u r p o s e , I / O p o r t s . Y o u c a n s e l e c t s c h m i t t t r i g g e r i n p u t m o d e , N -C H o p e n d r a i n
output mode.
You can access ports 0 and 1 directly by writing or reading the corresponding port data registers — P0 (E0H) and P1
(E1H). A reset clears the port control registers P0CONH, P0CONL, P1CONH and P1CONL to '00H', configuring all
port 0 and port 1 pins as schmitt trigger inputs.
In typical keyboard controller applications, the sixteen port 0 and port 1 pins can be used to check pressed key from
keyboard matrix by generating keystroke output signals.
Port 0 Control Registers
P0CONH, E6H, R/W, P0CONL, E7H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
P0CONH
P0.7/INT2
P0.6/INT2
P0.5/INT2
P0.4/INT2
P0CONL
P0.3/INT2
P0.2/INT2
P0.1/INT2
P0.0/INT2
LSB
7,5,3,1
6,4,2,0
Port Mode Selection
0
0
Schmitt trigger input, rising edge external interrupt mode
0
1
Schmitt trigger input, falling edge external interrupt mode
1
0
N-CH open drain output mode
1
1
N-CH open drain output mode with pull-up
with pull-up
F i g u r e 9 -2 . P o r t 0 C o n t r o l R e g i s t e r s ( P 0 C O N H , P 0 C O N L )
9 -3
I/O PORTS
S3C9688/P9688
Port 1 Control Registers
P1CONH, E8H, R/W, P1CONL, E9H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
P1CONH
P1.7
P1.6
P1.5
P1.4
P1CONL
P1.3
P1.2
P1.1
P1.0
7,5,3,1
6,4,2,0
Port Mode Selection
0
0
Schmitt trigger input mode
0
1
Schmitt trigger input mode with pull-up
1
0
N-CH open-drain output mode
1
1
N-CH open-drain output mode with pull-up
LSB
F i g u r e 9 -3 . P o r t 1 C o n t r o l R e g i s t e r s ( P 1 C O N H , P 1 C O N L )
9 -4
S3C9688/P9688
I/O PORTS
PORT 2
P o r t 2 i s a n 8 -b i t I / O p o r t w i t h i n d i v i d u a l l y c o n f i g u r a b l e p i n s . I t c a n b e u s e d f o r g e n e r a l I / O ( S c h m i t t t r i g g e r i n p u t m o d e
o r p u s h-p u l l o u t p u t m o d e ) . O r , y o u c a n u s e p o r t 2 p i n s a s e x t e r n a l i n t e r r u p t ( I N T 0 ) i n p u t s . I n a d d i t i o n , y o u c a n
c o n f i g u r e a p u l l -u p r e s i s t o r t o i n d i v i d u a l p i n s u s i n g c o n t r o l r e g i s t e r s e t t i n g s . A l l p o r t 2 p i n c i r c u i t s h a v e n o i s e f i l t e r s .
In typical keyboard controller applications, the port 2 pins are programmed to receive key input data from the
keyboard matrix.
Y o u c a n a d d r e s s p o r t 2 b i t s d i r e c t l y b y w r i t i n g o r r e a d i n g t h e p o r t 2 d a t a r e g i s t e r , P 2 ( E 2 H ) . T h e p o r t 2 h i g h -b y t e a n d
l o w -b y t e c o n t r o l r e g i s t e r s , P 2 C O N H a n d P 2 C O N L , a r e l o c a t e d a t a d d r e s s e s E A H a n d E B H , r e s p e c t i v e l y .
T w o a d d i t i o n a l r e g i s t e r s , a r e u s e d f o r i n t e r r u p t c o n t r o l: P 2 I N T ( E C H ) a n d P 2 P N D ( E D H ) . B y s e t t i n g b i t s i n t h e p o r t 2
interrupt enable register P2INT, you can configure specific port 2 pins to generate interrupt requests when rising or
falling signal edges are detected. The application program polls the port 2 interrupt pending register, P2PND, to
detect interrupt requests. When an interrupt request is acknowledged, the corresponding pending bit must be cleared
by the interrupt service routine.
In case of keyboard applications, the port 2 pins can be used to read key value from key matrix.
Port 2 Control Registers
P2CONH, EAH, R/W, P2CONL, EBH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
P2CONH
P2.7/INT0
P2.6/INT0
P2.5/INT0
P2.4/INT0
P2CONL
P2.3/INT0
P2.2/INT0
P2.1/INT0
P2.0/INT0
7,5,3,1
6,4,2,0
0
0
Schmitt trigger input, rising edge external interrupt
0
1
Schmitt trigger input, falling edge external interrupt
1
0
N-CH open-drain
1
1
N-CH open-drain with pull-up
LSB
Port Mode Selection
with pull-up
F i g u r e 9 -4 . P o r t 2 C o n t r o l R e g i s t e r s ( P 2 C O N H , P 2 C O N L )
9 -5
I/O PORTS
S3C9688/P9688
Port 2 Interrupt Enable Register (P2INT)
ECH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P2.0/INT0
P2.1/INT0
P2.2/INT0
P2.3/INT0
P2.4/INT0
P2.5/INT0
Port 2 Interrupt Control Settings:
P2.6/INT0
0 = Disable interrupt at P2.n pin
P2.7/INT0
1 = Enable interrupt at P2.n pin
F i g u r e 9 -5 . P o r t 2 I n t e r r u p t E n a b l e R e g i s t e r ( P 2 I N T )
Port 2 Interrupt Pending Register (P2PND)
EDH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P2.0/INT0
P2.1/INT0
P2.2/INT0
P2.3/INT0
P2.4/INT0
P2.5/INT0
P2.6/INT0
P2.7/INT0
Port 2 Interrupt Request Pending Bits:
0 = Not interrupt is pending
1 = Interrupt request is pending
F i g u r e 9 -6 . P o r t 2 I n t e r r u p t P e n d i n g R e g i s t e r ( P 2 P N D )
9 -6
S3C9688/P9688
I/O PORTS
PORT 3
P o r t 3 i s a 4 -b i t , b i t -c o n f i g u r a b l e , g e n e r a l I / O p o r t . I t i s d e s i g n e d f o r h i g h -c u r r e n t f u n c t i o n s s u c h a s L E D d r i v e .
A r e s e t c o n f i g u r e s P 3 . 0 -P 3 . 3 t o s c h m i t t t r i g g e r i n p u t m o d e . U s i n g t h e P 3 C O N r e g i s t e r ( E 5 H ) , y o u c a n a l t e r n a t i v e l y
c o n f i g u r e t h e p o r t 3 p i n s a s n -c h a n n e l , o p e n -d r a i n o u t p u t s . P 3 . 3 c a n b e u s e d t o s y s t e m c l o c k o u t p u t ( C L O ) p o r t .
Port 3 Control Register (P3CON)
E5H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P3.0
P3.1
P3.2
P3.3/CLO
Bit 7 Bit 6
Port Mode Selection (P3.3)
0
0
Schmitt trigger input
0
1
System Clock Ouput (CLO) mode.
1
0
Push-pull output
1
1
N-CH open drain output
CLO comes from System clock circuit.
5,3,1 4,2,0
Port Mode Selection (P3.2-P3.0)
0
x
Schmitt trigger input,
1
0
Push-pull output
1
1
N-CH open drain output
F i g u r e 9 -7 . P o r t 3 C o n t r o l R e g i s t e r ( P 3 C O N )
9 -7
I/O PORTS
S3C9688/P9688
PORT 4
P o r t 4 i s a 4 -b i t I / O p o r t w i t h i n d iv i d u a l l y c o n f i g u r a b l e p i n s . I t c a n b e u s e d f o r g e n e r a l I / O ( S c h m i t t t r i g g e r , N -C H o p e n
d r a i n o u t p u t m o d e , p u s h-p u l l o u t p u t m o d e ) . O r , y o u c a n u s e p o r t 4 p i n s a s e x t e r n a l i n t e r r u p t ( I N T 1 ) i n p u t s . I n
a d d i t i o n , y o u c a n c o n f i g u r e a p u l l -u p r e s i s t o r t o i n d i v i d u a l p i n s u s i n g c o n t r o l r e g i s t e r s e t t i n g s . A l l p o r t 4 p i n s h a v e
noise filters.
A r e s e t c o n f i g u r e s P 4 . 0 -P 4 . 3 t o i n p u t m o d e . Y o u a d d r e s s p o r t 4 d i r e c t l y b y w r i t i n g o r r e a d i n g t h e p o r t 4 d a t a r e g i s t e r ,
P4 (E4H). The port 4 control register, P4CON, is located at E E H .
A additional registers used for interrupt control: P4INTPND (EFH). By setting bits in the port 4 interrupt enable and
p e n d i n g r e g i s t e r P 4 I N T P N D . 7 -P 4 I N T P N D . 4 , y o u c a n c o n f i g u r e s p e c i f i c p o r t 4 p i n s t o g e n e r a t e i n t e r r u p t r e q u e s t s
when falling signal edges are detected. The application program polls the interrupt pending register, P4INTPND.3P4INTPND.0, to detect interrupt requests. When an interrupt request is acknowledged, the corresponding pending bit
must be cleared by the interrupt service routine.
Port 4 Control Register (P4CON)
EEH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P4.0/INT1
P4.1/INT1
P4.2/INT1
P4.3/INT1
P4CON Pin Configuration Settings:
00
Schmitt trigger input, falling edge external interrupt with pull-up
01
N-CH open-drain output with pull-up register
10
N-CH open-drain output
11
Push-pull output
F i g u r e 9 -8 . P o r t 4 C o n t r o l R e g i s t e r ( P 4 C O N )
9 -8
S3C9688/P9688
I/O PORTS
Port 4 Interrupt Enable and Pending Register (P4INTPND)
EFH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P4.0/INT1
P4.1/INT1
P4.2/INT1
P4.3/INT1
P4.0/INT1
P4.1/INT1
P4.2/INT1
P4.3/INT1
P4INTPND.7-.4: Port 4 interrupt control settings:
0 = Disable interrupt at P4.n pin
1 = Enable interrupt at P4.n pin
P4INTPND.3-.0: Port 4 interrupt pending bit:
0 = No interrupt request pending
1 = Interrupt request is pending
F i g u r e 9 -9 . P o r t 4 I n t e r r u p t E n a b l e a n d P e n d i n g R e g i s t e r ( P 4 I N T P N D )
9 -9
I/O PORTS
S3C9688/P9688
D + / P S 2 , D -/ P S 2
PS2 Control and Interrupt and Pending Register
D7H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
D-/PS2PND
D+/PS2PND
D-/PS2INT
D+/PS2INT
D-/PS2
D+/PS2
PS2CONINT.7-4 Pin Configration Settings: D+/PS2, D-/PS2
00
Schmitt trigger input, falling edge external interrupt
01
Schmitt trigger input, falling edge external interrupt with pull-up
10
N-CH open-drain output
11
N-CH open-drain output with pull-up register
PS2CONINT.3-2 : Interrupt Control Setting
0 = Disable interrupt
1 = Enable interrupt
PS2CONINT.1-0 : Interrupt Pending Bit
0 = No interrupt request pending
1 = Interrupt request pending
NOTE :
Used only PS2MODE.
F i g u r e 9 -1 0 . P S 2 C o n t r o l a n d I n t e r r u p t a n d P e n d i n g R e g i s t e r ( P S 2 C O N I N T )
9 -1 0
S3C9688/P9688
10
BASIC TIMER AND TIMER 0
BASIC TIMER and TIMER 0
MODULE OVERVIEW
T h e S 3 C 9 6 8 8 / P 9 6 8 8 h a s t w o d e f a u l t t i m e r s : a n 8 -b i t b a s i c t i m e r a n d o n e 8 -b i t g e n e r a l-p u r p o s e t i m e r / c o u n t e r . T h e
8 -b i t t i m e r / c o u n t e r i s c a l l e d t i m e r 0 .
Basic Timer (BT)
You can use the basic timer (BT) in two different ways:
—
As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction.
—
To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release.
The functional components of the basic timer block are:
—
Clock frequency divider (f
—
8 -b i t b a s i c t i m e r c o u n t e r , B T C N T ( D D H , r e a d -o n l y )
—
Basic tim er control register, BTCON (DCH, read/write)
OSC
divided by 4096, 1024, or 128) with multiplexer
Timer 0
Timer 0 has two operating modes, one of which you select by the appropriate T0CON setting:
—
Interval timer mode
—
Overflow mode
Timer 0 has the following functional components:
—
Clock frequency divider (f
—
8 -b i t c o u n t e r ( T 0 C N T ) , 8 -b i t c o m p a r a t o r , a n d 8 -b i t r e f e r e n c e d a t a r e g i s t e r ( T 0 D A T A )
—
Timer 0 overflow interrupt (T0OVF) and match interrupt (T0INT) generation
—
Timer 0 control re gister, T0CON
OSC
divided by 4096, 256, or 8) with multiplexer
1 0 -1
BASIC TIMER AND TIMER 0
S3C9688/P9688
BASIC TIMER CONTROL REGISTER (BTCON)
The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter
and frequency dividers, and to enable or disable the watchdog timer function.
A reset clears BTCON to '00H'. This enables the watchdog function and selects a basic timer clock frequency of
f
OSC
/4096. To disable the watchdog function, you must write the signature code '1010B' to the basic tim er register
c o n t r o l b i t s B T C O N . 7 -B T C O N . 4 .
T h e 8 -b i t b a s i c t i m e r c o u n t e r , B T C N T , c a n b e c l e a r e d a t a n y t i m e d u r i n g n o r m a l o p e r a t i o n b y w r i t i n g a " 1 " t o
BTCON.1. To clear the frequency dividers for both the basic timer input clock and the timer 0 clock, you write a "1"
to BTCON.0.
Basic Timer Control Register (BTCON)
DCH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Divider clear bit for basic:
Watchdog timer enable bits:
0 = No effect
1010B
1 = Clear both dividers
= Disable watchdog
function
Other value
= Enable watchdog
function
Basic timer counter clear bit:
0 = No effect
1 = Clear BTCNT
Basic timer input clock selection bits:
00 = f
OSC/4096
01 = f
OSC/1024
10 = f
OSC/128
11 = Invalid selection
F i g u r e 1 0 -1 . B a s i c T i m e r C o n t r o l R e g i s t e r ( B T C O N )
1 0 -2
S3C9688/P9688
BASIC TIMER AND TIMER 0
BASIC TIMER FUNCTION DESCRIPTION
Watchdog Timer F unction
Y o u c a n p r o g r a m t h e b a s i c t i m e r o v e r f l o w s i g n a l t o g e n e r a t e a r e s e t b y s e t t i n g B T C O N . 7 -B T C O N . 4 t o a n y v a l u e o t h e r
than '1010B' (The '1010B' value disables the watchdog function). A reset clears BTCON to '00H', automatically
enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the current CLKCON
register setting) divided by 4096 as the BT clock.
A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must
prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must be
cleared (by writing a "1" to BTCON.1) at regular intervals.
If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will
not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal operation, the
b a s i c t i m e r o v e r f l o w l o o p ( a b i t 7 o v e r f l o w o f t h e 8 -b i t b a s i c t i m e r c o u n t e r , B T C N T ) i s a l w a y s b r o k e n b y a B T C N T c l e a r
instruction. If a malfunction does occur, a reset is triggered automatically.
Oscillation Stabilization Interval Timer Function
You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when Stop
mode has been released by an external interrupt.
In Stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts
increasing at the rate of f
OSC
/4096 (for reset), or at the rate of the preset clock source (for an external interrupt). When
BTCNT.4 is set, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock
signal off to the CPU so that it can resume normal operation.
In summary, the following events occur when Stop mode is released:
1.
D u r i n g S t o p m o d e , a p o w e r-o n r e s e t o r a n e x t e r n a l i n t e r r u p t o c c u r s t o t r i g g e r t h e S t o p m o d e r e l e a s e a n d
oscillation starts.
2.
If a p o w e r-o n r e s e t o c c u r r e d , t h e b a s i c t i m e r c o u n t e r w i l l i n c r e a s e a t t h e r a t e o f f
OSC
/4096. If an external interrupt
is used to release Stop mode, the BTCNT value increases at the rate of the preset clock source.
3.
Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter is set.
4.
When a BTCNT.4 is set, normal CPU operation resumes.
F i g u r e s 1 0 -2 a n d 1 0 -3 s h o w s t h e o s c i l l a t i o n s t a b i l i z a t i o n t i m e o n R E S E T a n d S T O P m o d e r e l e a s e
1 0 -3
BASIC TIMER AND TIMER 0
S3C9688/P9688
Oscillation Stabilization
0.5 V
Normal Operating mode
DD
V DD
Reset ReleaseVoltage
RESET
~RC
trst ~
Internal
Reset
Release
0.5 V
DD
Oscillator
(X OUT )
Oscillator Stabilization Time
BTCNT
clock
10000B
BTCNT
value
00000B
tWAIT = (4096x16)/f
OSC
Basic timer increment and
CPU operations are IDLE mode
NOTE:
During of the oscillator stabilization wait time, t
WAIT,
when it is released
by a Power-on-reset is 4096x16/fosc.
~RC (R is external resister and C is on chip capacitor)
trst ~
F i g u r e 1 0 -2 . O s c i l l a t i o n S t a b i l i z a t i o n T i m e o n R E S E T
1 0 -4
S3C9688/P9688
BASIC TIMER AND TIMER 0
STOP Mode
Normal
Oscillation Stabilization Time
Normal
Operating
Operating
Mode
Mode
V DD
STOP
Instruction
STOP Mode
Execution
Release Signal
External
Interrupt
RESET
STOP
Release
Signal
Oscillator
(X OUT)
BTCNT
clock
10000B
BTCNT
00000B
Value
t WAIT
Basic Timer Increment
NOTE:
Duration of the oscillator stabilzation wait time, tWAIT, it is released by an
interrupt is determined by the setting in basic timer control register, BTCON.
tWAIT
tWAIT (When f OSC is 6 MHz)
BTCON.3
BTCON.2
0
0
(4096 x 16)/fosc
10.92 ms
0
1
(1024 x 16)/fosc
2.7 ms
1
0
(128 x 16)/fosc
0.34 ms
1
1
Invalid setting
F i g u r e 1 0 -3 . O s c i l l a t i o n S t a b i l i z a t i o n T i m e o n S T O P M o d e R e l e a s e
1 0 -5
BASIC TIMER AND TIMER 0
S3C9688/P9688
T I M E R 0 C O N T R O L R E G IS T E R ( T 0 C O N )
T0CON is located at address D2H, and is read/write addressable.
A reset clears T0CON to '00H'. This sets timer 0 to normal interval match mode, selects an input clock frequency of
f
OSC
/4096, and disables the timer 0 overflow interrupt and match interrupt. You can clear the timer 0 counter at any
time during normal operation by writing a "1" to T0CON.3.
The timer 0 overflow interrupt can be enabled by writing a "1" to T0CON.2. When a timer 0 overflow interrupt occurs
and is serviced by the CPU, the pending condition must be cleared by software by writing a "0" to the timer 0
interrupt pending bit, T0CON.0.
To enable the timer 0 match interrupt, you must write T0CON.1 to "1". To detect an interrupt pending condition, the
application program polls T0CON.0. When a "1" is detected, a timer 0 match/ capture interrupt is pending. When the
interrupt request has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 0
interrupt pending bit, T0CON.0.
Timer 0 Control Register (T0CON)
D2H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Timer 0 input clock selection bits:
Timer 0 interrupt pending bit:
00 = f
OSC /4096
0 = No interrupt pending
01 = f
OSC /256
0 = Clear pending bit (when write)
10 = f
OSC /8
1 = Interrupt is pending (When read)
11 = Invalid selection
No effect (When write)
Timer 0 match interrupt enable bit:
Timer 0 operating mode selection bits:
0 = Disable match interrupt
00 = Interval match mode
1 = Enable match interrupt
01 = Invalid selection
10 = Invalid selection
Timer 0 overflow interrupt enable bit:
11 = Overflow mode
0 = Disable overflow interrupt
1 = Enable overflow interrupt
Timer 0 counter clear bit:
0 = No effect
1 = Clear the timer 0 counter (when write)
F i g u r e 1 0 -4 . T i m e r 0 C o n t r o l R e g i s t e r ( T 0 C O N )
1 0 -6
S3C9688/P9688
BASIC TIMER AND TIMER 0
TIMER 0 FUNCTION DES CRIPTION
Interval Match Mode
In interval match mode, a match signal is generated when the counter value is identical to the value written to the T0
reference data register, T0DATA. The match signal generates a timer 0 match interrupt and then clears the counter.
If for example, you write the value '10H' to T0DATA, the counter will increment until it reaches '10H'. At this point, the
T0 match interrupt is generated, the counter value is reset and counting resumes.
Ove rflow Mode
In overflow mode, a overflow signal is generated regardless of the value written to the T0 reference data register when
the counter value is overflowed. The overflow signal generates a timer 0 overflow interrupt and then T0 counter is
cleared.
T0OVF
Data Bus
T0PND
8
CLK
Counter
Comparator
T0INT
R
Match
T0DATA Buffer
Register
When 8-Bit counter is cleared,
this buffer is open
T0DATA
8
Data Bus
F i g u r e 1 0 -5 . S i m p l i f i e d T i m e r 0 F u n c t i o n D i a g r a m : I n t e r v a l T i m e r M o d e
1 0 -7
BASIC TIMER AND TIMER 0
S3C9688/P9688
Write '1010xxxxB' to disable
Data Bus
Bit 1
Bits 7, 6, 5, 4
8
RESET or STOP
1/4096
XIN
DIV
1/1024
8-Bit Basic Counter
OVF
RESET
(BTCNT, Read-only)
MUX
1/128
When BTCNT. 4 is set after releasing from
R
RESET or STOP mode, CPU clock start.
Bit 2
Bits 3, 2
Bit 0
Bits 7, 6
OVINT
Data Bus
Overflow
R
8
1/4096
2-Bit
DIV
1/256
1/8
SCA
8-Bit Counter
(T0CNT, Read-only)
Bit 3
R
Match
8
LER
T0CLR
Signal
Bit 1
T0INT
Match/
8-Bit Comparator
Overflow
Bit 0
IRQ
8
Bits 5, 4
T0DATA Buffer Register
When 8-bit counter is cleared,
this buffer is open.
T0DATA
8
Data Bus
Basic Timer Control Register
Timer 0 Control Register
F i g u r e 1 0 -6 . B a s i c T i m e r a n d T i m e r 0 B l o c k D i a g r a m
1 0 -8
S3C9688/P9688
11
UNIVERSAL SERIAL BUS
UNIVERSAL SERIAL BUS
OVERVIEW
Universal Serial Bus (USB) is a communication architecture that supports data transfer between a host computer
and a wide range of PC peripherals. USB is actually a cable bus in which the peripherals share its bandwidth through
a host scheduled token based protocol.
The USB module in S3C9688/P9688 is designed to serve at a low speed transfer rate (1.5 Mbs) USB device as
described in the Universal Serial Bus Specification Revision 2.0. S3C9688/P9688 can be briefly describe as a
m i c r o c o n t r o l l e r w i t h S A M 8 8 R C R I c o r e w i t h a n o n -c h i p U S B p e r i p h e r a l a s c a n b e s e e n i n f i g u r e 1 1 -1 .
T h e S 3 C 9 6 8 8 / P 9 6 8 8 c o m e s e q u i p p e d w i t h S e r i a l I n t e r f a c e E n g i n e ( S I E ) , w h i c h h a n d l e s t h e c o m m un i c a t i o n p r o t o c o l
of the USB. The S3C9688/P9688 supports the following control logic: packet decoding/generation, CRC
generation/checking, NRZI encoding/decoding, Sync detection, EOP (end of packet) detection and bit stuffing.
S3C9688/P9688 supports two types of data transfers; control and interrupt. Three endpoints are used in this device;
Endpoint 0, Endpoint 1, and Endpoint 2 . Please refer to the USB specification revision 2.0 for detail description of
USB.
1 1 -1
UNIVERSAL SERIAL BUS
S3C9688/P9688
D+/PS2
D-/PS2
Transceiver
Voltage
Regulator
SAM88RCRI
SIE
Core
(Serial Interface
Engine)
Endpoint 0 FIFO
Endpoint 1, 2
Interface
FIFO
F i g u r e 1 1 -1 . U S B P e r i p h e r a l I n t e r f a c e
1 1 -2
S3C9688/P9688
UNIVERSAL SERIAL BUS
Serial Bus Interface Engine (SIE)
The Serial Interface Engine interfaces to the USB serial data and handles, deserialization/serialization of data, NRZI
encoding/decoding, clock extraction, CRC generation and checking, bit stuffing and other specifications pertaining to
the USB protocol such as handling inter packet time out and PID decoding.
Control Logic
The USB control logic manages data movements between the CPU and the transceiver by manipulating the
transceiver and the endpoin t register. This includes both transmit and receive operations on the USB. The logic
contains byte count buffers for transmit operations that load the active transmit endpoint's byte count and use this to
determine the number of bytes to transfer. The same buffer is used for receive transactions to count the number of
bytes received and transfer that number to the receive endpoint's byte count register at the end of the transaction.
The control logic in S3C9688/P9688, when transmitting, manages parallel to serial conversion, packet generation,
CRC generation, NRZI encoding and bit stuffing.
When receiving, the control logic in S3C9688/P9688 handles Sync detection, packet decoding, EOP (end of packet)
detection, bit stuffing, NRZI decoding, CRC checking and serial to parallel conversion
Bus Protocol
All bus transactions involve the transmission of packets. S3C9688/P9688 supports three packet types; Token, Data
and Handshake. Each transaction starts when the host controller sends a Token Packet to the USB devi ce. The
Token packets are generated by the USB host and decoded by the USB device. A Token Packet includes the type
description, direction of the transaction, USB device address and the endpoint number.
Data and Handshake packets are both decoded and generated by the USB device. In any transaction, the data is
transferred from the host to a device or from a device to the host. The transaction source then sends a Data Packet
or indicates that it has no data to transfer. The destination then responds with a Handshake Packet indicating
whether the transfer was successful.
Data Transfer Types
USB data transfer occurs between the host software and a specific endpoint on the USB device. An endpoint
supports a specific type of data transfer. The S3C9688/P9688 supports two data transfer endpoints: control and
interrupt.
Control transfer configures and assigns an address to the device when detected. Control transfer also supports
status transaction, returning status information from device to host.
Interrupt transfe r refers to a small, spontaneous data transfer from USB device to host.
Endpoints
Communication flows between the host software and the endpoints on the USB device. Each endpoint on a device
has an identifier number. In addition to the endpoint number, each endpoint supports a specific transfer type.
S3C9688/P9688 supports three endpoints: Endpoint 0 supports control transfer, and Endpoint 1 and Endpoint 2
supports interrupt transfer.
1 1 -3
UNIVERSAL SERIAL BUS
S3C9688/P9688
STRUCTURE OF USB AND PS/2 COMBINATIONAL PORT
Pull-up Enable
USB Enable
[A]
[B]
Voltage Regulator
USB Signal Transceiver
(3.3 V Generation)
(With Pull-up)
USB Control
[C]
PS/2 Control
(P2CONINT)
NOTE:
PS/2 Signal Transceiver
(With Pull-up)
That block explain USB block can be enabled or disabled with pull-up by s/w.
Voltage regulator also disabled automatically when USB block was disabled.
And PS/2 block can be controlled by software with pull-up.
F i g u r e 1 1 -2 . B l o c k D i a g r a m o f U S B a n d P S / 2 T r a n s c e i v e r
1 1 -4
DM
DP
S3C9688/P9688
UNIVERSAL SERIAL BUS
STRUCTURE OF VOLTAGE REGULATOR
Enable
Reference
Voltage
Generator
A
NOTE:
Current
3.3 V
Amplifier
B
This block can give a explanation how it can be controlled automatically.
If the 3.3 voltage regulator is enabled by software, it operates to cover fluctuation of
the line load, sometimes the line is unstable and the driving ability dropped.
As it operates in the normal stage without any peak, power will be supplied with
8 mA, and when the operating. It was designed to cover by 50 mA, the peak current
consumption. It means any kind of load problem will be compensated with the above
design.
F i g u r e 1 1 -3 . B l o c k D i a g r a m o f V o l t a g e R e g u l a t o r
1 1 -5
UNIVERSAL SERIAL BUS
S3C9688/P9688
Pull-up Control
R, 1.5 K Ω
+5 %
C
A
B
DM
D-
V3.3IN
DM
TX/RX
Control
Slope
CTRL
Sinals
Control
DP
Enable
D+
DP
TX/RX
D
NOTE:
We didn't used the by-pass capacitor on the 3.3 V out, since the 3.3 V regulator and clamp
circuit will give a solution through the feedback.
USB block was designed to cover the line load, the typically designed value is 300 pF (max: 800 pF).
The clamp block operating after it detect the voltage variation
(actually the current fluctuation will be feedback into voltage variation, di/dt to dt/dt variation.
Bias controls the slope.
Control signal means NRZI, EOP, XCON, IN/OUT.
Enable is for the Tx, Rx.
Internal pull-up resistor will be 1.5 k
Ω
+10 %
F i g u r e 1 1 -4 . B l o c k D i a g r a m o f U S B S i g n a l T r a n s c e i v e r
V DD
V DD
DM_DRVP
DP_DRVP
Pull-up Enable
Pull-up Enable
DM
DM_DRVN
NOTE:
PS/2 Data
DP
DP_DRVN
PS/2 Clock
It explain the PS2 block.
The pull-up resistor value will be 4.3 k
Ω
+ 20 %
This block can be controlled with pull-up resistor and it was designed with totally
different from usb.
F i g u r e 1 1 -5 . B l o c k D i a g r a m o f G P I O S i g n a l T r a n s m i t t e r
1 1 -6
S3C9688/P9688
UNIVERSAL SERIAL BUS
USB FUNCTION ADDRESS REGISTER (FADDR)
This register holds the USB address assigned by the host computer. FADDR is located at address F0H and is
read/write addressable.
Bit7
This register bit is used as test mode or special purpose mode, so user should set zero value,
Bit6– 0
FADDR:
MCU updates this register once it decodes a SET_ADDRESS command. MCU must write this
register before it clears OUT_PKT_RDY (bit0) and sets DATA_END (bit3) in the EP0CSR register. The
function controller use this register's value to decode USB Token packet address. At reset, if the device
is not yet configured the value is reset to 0.
USB Function Address Register (FADDR)
F0H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
This register bit sets zero value
7-bit programming device address. This register
maintains the USB address assigned by the host.
The function controller uses this register's value to
decode USB token packet address. At reset when
the device is not yet configured the value is reset to 0.
F i g u r e 1 1 -6 . U S B F u n c t i o n A d d r e s s R e g i s t e r ( F A D D R )
1 1 -7
UNIVERSAL SERIAL BUS
S3C9688/P9688
C O N T R O L E N D P O I N T S T A T U S R E G I S T E R ( E P 0 C S R)
EP0CSR register controls Endpoint 0 (Control Endpoint), and also holds status bits for Endpoint 0. EP0CSR is
located at F1H and is read/write addressable.
Bit7
CLEAR_SETUP_END: MCU writes "1" to this bit to clear SETUP_END bit (bit4). This bit is
automatically cleared after clearing SETUP_END bit by SIE. So read value will be always "0".
Bit6
CLEAR_OUT_PKT_RDY: MCU writes "1" to this bit to clear OUT_PKT_RDY bit (bit0). This bit is
automatically cleare d after clearing OUT_PKT_RDY bit by USB block. So read value will be always "0".
Bit5
SEND_STALL: MCU writes "1" to this bit to send STALL packet to Host, it must clear OUT_PKT_RDY
(bit 0) at the same time. If MCU receive invalid command then should write #60h to this register. The SIE
issues a STALL handshake to the current control transfer(Means next transaction). This bit will be cleared
after sending STALL handshake.
Bit4
S E T U P _ E N D : SIE sets this bit, when a control transfer ends without setting D ATA_END bit (bit3). MCU
clears this bit, by writing a "1" to CLEAR_SETUP_END bit (bit7). When SIE sets this bit, an interrupt is
generated to MCU. When such condition occurs, SIE flushes the FIFO. MCU can not access to FIFO
until this bit cleared. This flag is a read only bit so MCU can not write to this bit directly.
Bit3
DATA_END: MCU sets this bit:
—
After loading the last packet of data into the FIFO, and at the same time IN_PKT_RDY bit should be
set.
— While it clears OUT_PKT_RDY bit after unloading the last packet of data.
—
Bit2
For a zero length data phase, this bit should be set when it clears OUT_PKT_RDY bit.
SENT_STALL: SIE sets this bit after send stall handshake to host. There are two cases which issue stall
packet to host. If MCU set SEND_STALL bit, then SIE will send stall to the next transaction and set this
bit. The other case is send stall by SIE automatically since protocol violation. An interrupt is generated
when this bit gets set. This bit is a read/write bit so MCU s hould clears this bit to end the STALL
condition.
Bit1
IN_PKT_RDY: MCU sets this bit, after loading data into Endpoint 0 FIFO. SIE clears this bit, once the
packet has been successfully sent to the host. An interrupt is generated when SIE clears this bit so that
MCU can load the next packet. For a zero length data phase, MCU sets IN_PKT_RDY bit without load
data to FIFO.
Bit0
O U T _ P K T _ R D Y : SIE sets this bit, if the device receive valid data from host. An interrupt is generated,
when SIE sets this bit. MCU should download data and clears this bit by writing "1" to
CLEAR_OUT_PKT_RDY bit at the end of execution.
NOTE
When SETUP_END bit is set, OUT_PKT_RDY bit may also be set. This happens when the current transfer
has terminated by new setup transaction. In such case, MCU should first clear SETUP_END bit, and then
start servicing the
1 1 -8
new control transfer.
S3C9688/P9688
UNIVERSAL SERIAL BUS
Control Endpoint Status Register (EP0CSR)
F1H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
OUT_PKT_RDY
CLEAR_
SETUP_END
IN_PKT_RDY
CLEAR_
SENT_STALL
OUT_PKT_RDY
SEND_STALL
DATA_END
SETUP_END
F i g u r e 1 1 -7 . C o n t r o l E n d p o i n t S t a t u s R e g i s t e r ( E P 0 C S R )
1 1 -9
UNIVERSAL SERIAL BUS
S3C9688/P9688
I N T R R U P T E N D P O I N T S S T A T U S R E G I S T E R ( E P 1 C S R , E P 2 C S R )— I N M O D E
E P 1CSR register controls Endpoint 1, and also holds status bits for Endpoint 1. EP1CSR is located at F2H and is
read/write addressable. EP2CSR register controls Endpoint2, and the contents is perfectly same to EP1CSR.
EP2CSR is located at F9H and is read/write addressable.
EP1CSR and EP2CSR have two modes. These are IN and OUT mode which are decided by ENDPOINT_MODE
register. The below is IN mode configuration.
Bit7
C L R _ D A T A _ T O G G L E : MCU write "1" to this bit for initializing data toggle sequence. Data toggle
sequence can be monitored through WRT_CNT register.
Bit6
MAXP[3].
Bit5
MAXP[2].
Bit4
MAXP[1].
Bit3
MAXP[0].
Bit2
—
S3P9688 is a low speed USB controller so the maximum packet size is 8 bytes,
—
T h i s p a r t i s a l i m i t a t i o n o f M A X M U M p a c k e t s i z e s o t h e d e v i c e c a n n o t s e n d m o r e d a t a t h a n t h i s value.
UC_FIFO_FLUSH: MCU sets this bit for initializing the FIFO. MCU can not clear IN_PKT_RDY so if
MCU want to clear IN_PKT_RDY after set then MCU should issue UC_FIFO_FLUSH for clearing
IN_PKT_RDY.
Bit1
FORCE_STALL: MCU sets this bit for sending stall packet. This flag will not be cleared by SIE. So MCU
should clear this flag for stopping stall condition. Device will send stall until this flag is cleared.
Bit0
IN_PKT_RDY: MCU sets this bit after loading data to FIFO. SIE will clear this flag after sending data to
host. An interrupt is generated when this flag is cleared. If MCU issue UC_FIFO_FLUSH during this flag
s e t t h e n t h i s f l a g i s c l e a r e d a n d g e n e r a t e i n t e r r u p t t o M C U . S o M C U w i l l g e t i n t e rr u p t d i r e c t l y a f t e r s e t t i n g
UC_FIFO_FLUSH flag if this flag was set.
1 1 -1 0
S3C9688/P9688
UNIVERSAL SERIAL BUS
I N T R R U P T E N D P O I N T S S T A T U S R E G I S T E R ( E P 1 C S R , E P 2 C S R )— O U T M O D E
The below is OUT mode configuration.
Bit7
Reserved.
Bit6
CLEAR_OUT_PKT_RDY: MCU writes "1" to this bit to clear OUT_PKT_RDY bit (bit0). This bit is
automatically cleared after clearing OUT_PKT_RDY bit by SIE. So read value will be always "0".
Bit5
Reserved.
Bit4
Reserved.
Bit3
S E N T _ S T A L L : This flag is set by SIE after sending stall packet. And this flag is just for monitoring the
action of SIE so it does not mean any other things. This flag can be cleared by MCU.
Bit2
UC_FIFO_FLUSH: MCU sets this bit for initializing the FIFO. MCU can not clear IN_PKT_RDY so if
MCU want to clear IN_PKT_RDY after set then MCU should issue UC_FIFO_FLUSH for clearing
IN_PKT_RDY.
Bit1
FORCE_STALL: MCU sets this bit for sending stall packet. This flag will not be cleared by SIE. So MCU
should clear this flag for stopping stall condition. Device will send stall until this flag is cleare d.
Bit0
O U T _ P K T _ R D Y : SIE sets this bit, if the device receive valid data from host. An interrupt is generated,
when SIE sets this bit. MCU should download data and clears this bit by writing "1" to
CLEAR_OUT_PKT_RDY bit at the end of execution.
1 1 -1 1
UNIVERSAL SERIAL BUS
S3C9688/P9688
ENDPOINT 0 WRITE COUNT REGISTER (EP0BCNT)
EP0BCNT register contains data count value, some monitoring and flow control flag. EP0BCNT is located at F3H and
is read addressable.
Bit7
D A T A _ T O G G L E : This bit is a read only flag. This flag is just for monitoring the data toggle sequence.
Bit6
T O K E N : This flag is for monitoring. If this value is set then it means the last received token packet is
SETUP token and if the value is "0" then the last received token packet is OUT or IN packet.
Bit5
O V E R _ 8 :. I f d e v i c e r e c e i v e o v e r 8 b y t e s S E T U P o r O U T t r a n s a c t i o n t h e n t h e d e v i c e d o e s n o t a n s w e r t o
these transaction and set this flag as a error indicator.
Bit4
E N A B L E :. M C U s e t t h i s b i t f o r d i s a b l i n g e n d p o i n t 0 . D e v i c e d o e s n o t a n s w e r t o a n y t r a f f i c i f a d d r e s s e d t o
endpoint 0 until this bit is cleared.
Bit3
E P 0 W R T _ C N T [ 3 ].
Bit2
E P 0 W R T _ C N T [ 2 ].
Bit1
E P 0 W R T _ C N T [ 1 ].
Bit0
EP0WRT_CNT[0]: SIE store data count after receive valid data from host. The maximum value is 8. And
if MCU downloading the FIFO then this value also decreased according to remain data count.
1 1 -1 2
S3C9688/P9688
UNIVERSAL SERIAL BUS
ENDPOINT 1 WRITE COUNT REGISTER (EP1BCNT)
EP1BCNT register contains data count value, some monitoring and flow control flag. EP1BCNT is located at FCH
and is read/write addressable.
Bit7
D A T A _ T O G G L E : T h i s b i t i s a r e a d o n ly f l a g . T h i s f l a g i s j u s t f o r m o n i t o r i n g t h e d a t a t o g g l e s e q u e n c e .
Bit6
Reserved.
Bit5
O V E R _ 8 :. I f d e v i c e r e c e i v e o v e r 8 b y t e s S E T U P o r O U T t r a n s a c t i o n t h e n t h e d e v i c e d o e s n o t a n s w e r t o
these transaction and set this flag as a error indicator.
Bit4
E N A B L E :. M C U s e t t h i s b i t f o r d i s a b l i n g e n d p o i n t 1 . D e v i c e d o e s n o t a n s w e r t o a n y t r a f f i c i f a d d r e s s e d t o
endpoint 1 until this bit is cleared.
Bit3
E P 1 W R T _ C N T [ 3 ].
Bit2
E P 1 W R T _ C N T [ 2 ].
Bit1
E P 1 W R T _ C N T [ 1 ].
Bit0
E P 1 W R T _ C N T [ 0 ] : S I E s t o r e d a t a c o u n t a f t e r r e c e i v e va l i d d a t a f r o m h o s t . T h e m a x i m u m v a l u e i s 8 . A n d
if MCU downloading the FIFO then this value also decreased according to remain data count.
1 1 -1 3
UNIVERSAL SERIAL BUS
S3C9688/P9688
ENDPOINT 2 WRITE COUNT REGISTER (EP2BCNT)
EP2BCNT register contains data count value, some monitoring and flow control flag. EP2BCNT is located at FDH
and is read/write addressable.
Bit7
D A T A _ T O G G L E : This bit is a read only flag. This flag is just for monitoring the data toggle sequence.
Bit6
Reserved.
Bit5
O V E R _ 8 :. I f d e v i c e r e c e i v e o v e r 8 b y t e s S E T U P o r O U T t r a n s a c t i o n t h e n t h e d e v i c e d o e s n o t a n s w e r t o
these transaction and set this flag as a error indicator.
Bit4
E N A B L E :. M C U s e t t h i s b i t f o r d i s a b l i n g e n d p o i n t 2 . D e v i c e d o e s n o t a n s w e r t o a n y t r a f f i c i f a d d r e s s e d t o
endpoint 1 until this bit is cleared.
Bit3
E P 1 W R T _ C N T [ 3 ].
Bit2
E P 1 W R T _ C N T [ 2 ].
Bit1
E P 1 W R T _ C N T [ 1 ].
Bit0
EP1WRT_CNT[0]: SIE store data count after receive valid data from host. The maximum value is 8.
And if MCU downloading the FIFO then this value also decreased according to remain data count.
1 1 -1 4
S3C9688/P9688
UNIVERSAL SERIAL BUS
ENDPOINT MODE REGISTER (EPMODE)
EPMODE register contains the field which defines USB reset signal length and the field which defines the direction of
endpoints. EPMODE is located at FBH and is read/write addressable.
Bit7
RESET_LENGTH[1].
Bit6
RESET_LENGTH[0]: This field defines the length of USB reset signal. The reset value is "00". MCU can
control USB reset length through this field. The definition is as below.
—
"00" : 20.954 us.
—
"01" : 10.476 us.
—
"10" : 5.236 us.
—
"11" : 2.664 us.
Bit5
Reserved.
Bit4
Reserved.
Bit3
C H I P _ T E S T _ M O D E : If this value is "1" then Test mode and If this value is "0" then Normal mode. User
must not set this bit. The Reset value is "0"
Bit2
O U T P U T _ E N A B L E _ M O D E : If this value is "1" then Normal mode and If this value is "0" then Enhanced
mode. The Reset value is "0".
Bit1
ENDPOINT_MODE[1]: MCU can defines direction of interrupt transfer. If this value is "1" then endpoint 2
act as a OUT interrupt endpoint and if this value is "0" then endpoint 2 act as a IN interrupt endpoint. The
reset value is "0".
Bit0
ENDPOINT_MODE[0]: MCU can defines direction of interrupt transfer. If this value is "1" then endpoint 1
act as a OUT interrupt endpoint and if this value is "0" then endpoint 1 act as a IN interrupt endpoint. The
reset value is "0".
1 1 -1 5
UNIVERSAL SERIAL BUS
S3C9688/P9688
USB POWER MANAGEMENT REGISTER (PWRMGR)
PWRMGR register interacts with the Host's power management system to execute system power events such as
SUSPEND or RESUME. And this register also contains monitoring field for detail control of MCU. This register is
located at address F8H and is read/write addressable.
Bit7
Reserved.
Bit6
Reserved.
Bit5
Reserved.
Bit4
V P I N _ M O N I T O R : If this value is "1" then DATA - is one and If this value is "0" then DATA+ is zero.
Bit3
V M I N _ M O N I T O R : If this value is "1" then DATA - is one and If this value is "0" then DATA - is one.
Bit2
C L E A R _ S U S P _ C N T : MCU write "1" value to this bit for clearing suspend counter which count 3 ms. And
d u r i n g t h i s v a l u e s t a y " 1 " t h e s u s p e n d c o u n t e r d o e s n o t p r o c ee d . T h a t m e a n s t h e U S B c o n t r o l l e r c a n n o t
go into suspend state during this value stays "1".
Bit1
Reserved.
Bit0
SUSPEND_STATE: Suspend state is set when the MCU sets suspend interrupt. This bit is cleared
automatically when:
—
MCU writes "0" to SEND_RESUME bit to end the RESUME signaling (after SEND_RESUME is set
for 10ms).
—
1 1 -1 6
MCU receives RESUME signaling from the Host while in SUSPEND mode.
S3C9688/P9688
UNIVERSAL SERIAL BUS
USB Power Mangement Register (PWRMGR)
F8H, R/W
MSB
.7
.6
.5
.4
.3
Reserved
.2
.1
.0
LSB
SUSPEND_STATE
VPIN
Reserved
CLEAR_SUSP_CNT
VMIN
F i g u r e 1 1 -8 . U S B P o w e r M a n a g e m e n t R e g i s t e r ( P W R M G R )
1 1 -1 7
UNIVERSAL SERIAL BUS
S3C9688/P9688
CONTROL ENDPOINT FIF O REGISTER (EP0FIFO)
T h i s r e g i s t e r i s b i-d i r e c t i o n a l , 8 b y t e d e p t h F I F O u s e d t o t r a n s f e r C o n t r o l E n d p o i n t d a t a . E P 0 F I F O i s l o c a t e d a t
address F4H and is read/write addressable.
Initially, the direction of the FIFO, is from the Host to the MCU. After a setup token is received for a control transfer,
that is, after MCU unload the setup token bytes, and clears OUT_PKT_RDY, the direction of FIFO is changed
automatically from MCU to the Host.
INTERRUPT ENDPOINT 1 FIFO REGISTER (EP1FIFO)
E P 1 F I F O i s a n b i-d i r e c t i o n 8 -b y t e d e p t h F I F O u s e d t o t r a n s f e r d a t a f r o m t h e M C U t o t h e H o s t o r f r o m t h e H o s t t o t h e
MCU. MCU writes data to this register, and when finished set IN_PKT_RDY. Meanwhile, when USB receives valid
data through this register , it sets OUT_PKT_RDY, after MCU unload Data bytes, and clears OUT_PKT_RDY , This
register is located at address F5H.
INTERRUPT ENDPOINT 2 FIFO REGISTER (EP2FIFO)
E P 2 F I F O i s a n b i-d i r e c t i o n 8 -b y t e d e p t h F I F O u s e d t o t r a n s f e r d a t a f r o m t h e M C U t o t h e H o s t o r f r o m t h e H o s t t o t h e
M C U . M CU writes data to this register, and when finished set IN_PKT_RDY. Meanwhile, when USB receives valid
data through this register , it sets OUT_PKT_RDY, after MCU unload Data bytes, and clears OUT_PKT_RDY , This
register is located at address FAH.
USB INTERRUPT PENDIN G REGISTER (USBPND)
U S B P N D r e g i s t e r h a s t h e i n t e r r u p t b i t s f o r e n d p o i n t s a n d p o w e r m a n a g e m e n t . This register is cleared once read by MCU.
While any one of the bits is set, an interrupt is generated. USBPND is located at address F6H.
Bit7– 6
Not used
Bit5
U S B _ R S T _ P N D : This bit is set, when usb reset signal is received.
Bit4
E N D P T 2 _ P N D : This bit is set, when suspend signaling is received.
Bit3
R E S U M E _ P N D : While in suspend mode, if resume signaling is received this bit gets set.
Bit2
S U S P E N D _ P N D : This bit is set, when suspend signaling is received.
Bit1
E N D P T 1 _ P N D : T h i s b i t i s s e t , w h e n E nd p o i n t 1 n e e d s t o b e s e r v i c e d .
Bit0
E N D P T 0 _ P N D : This bit is set, when Endpoint 0 needs to be serviced. It is set under any one of the
following conditions:
1 1 -1 8
—
OUT_PKT_RDY is set.
—
IN_PKT_RDY gets cleared.
—
SENT_STALL gets set.
—
DATA_END gets cleared.
—
SETUP_END gets set.
S3C9688/P9688
UNIVERSAL SERIAL BUS
USB Interrupt Pending Register (USBPND)
F6H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
Not used
.0
LSB
ENDPT0_PND
USB_RST_PND
ENDPT1_PND
ENDPT2_PND
RESUME_PND
SUSPEND_PND
F i g u r e 1 1 -9 . U S B I n t e r r u p t P e n d i n g R e g i s t e r ( U S B P N D )
1 1 -1 9
UNIVERSAL SERIAL BUS
S3C9688/P9688
USB INTERRUPT ENABLE REGISTER (USBINT)
USBINT is located at address F7H and is read/write addressable. This register serves as an interrupt mask register.
If the corresponding bit = 1 then the respective interrupt is enabled.
By default, all interrupts except suspend interrupt is enabled. Interrupt enables bits for suspend and resume is
combined into a single bit (bit 2).
Bit7– 5
Not used
Bit4
ENABLE_USB_RST_INT:
1: Enable USB RESET INTERRUPT (default)
0: Disable USB RESET INTERRUPT
Bit3
ENABLE_ENDPT2_INT:
1: Enable ENDPOINT 2 INTERRUPT (default)
0: Disable ENDPOINT 2 INTERRUPT
Bit2
ENABLE_SUSPEND_RESUME_INT:
1: Enable SUSPEND and RESUME INTERRUPT
0: Disable SUSPEND and RESUME INTERRUPT (default)
Bit1
ENABLE_ENDPT1_INT:
1: Enable ENDPOINT 1 INTERRUPT (default)
0 : D i s a b l e E N D P O I N T 1 I N T E RR U P T
Bit0
ENABLE_ENDPT0_INT:
1: Enable ENDPOINT 0 INTERRUPT (default)
0: Disable ENDPOINT 0 INTERRUPT
USB Interrupt Enable Register (USBINT)
F7H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
Not used
.0
LSB
ENABLE_ENDPT0_INT
ENABLE_ENDPT1_INT
ENABLE_USB_RST_INT
ENABLE_SUSPEND_RESUME_INT
ENABLE_ENDPT2_INT
F i g u r e 1 1 -1 0 . U S B I n t e r r u p t E n a b l e R e g i s t e r ( U S B I N T )
1 1 -2 0
S3C9688/P9688
UNIVERSAL SERIAL BUS
USB CONTROL REGISTER (USBCON)
USBCON is for the control of USB data line and the control of reset .This register is located at address FEH and is
read/write addressable.
Bit5
DP /DM Control: When this bit is set , DP/DM lines can be controlled by MCU as bellows
Bit4
D P : On the condition of bit5 set, if this bit is 1, DP line is to be high and the other case this bit is 0
DP line is low .
Bit3
D M : On the condition of bit5 set, if this bit is 1, DM line is to be high and the other case this bit is 0
DM line is low .
Bit2
USB_RESET_EN: When this bit is set, it is USB is made reset , which trigger MCU reset
automatically
Bit1
MCU_RESET: When this bit is set, MCU makes USB reset
Bit1
USB_RSTN: USB reset status bit
0: USB is not reset
1: USB is reset
USB Control Register (USBCON)
FEH (Page 0), R/W
MSB
.7
.6
.5
.4
.3
Reserved
.2
.1
.0
LSB
USB_RSTN
MCU_RESET
DP/
DM_CONTROL
USB_RESET_EN
DM
DP
F i g u r e 1 1 -1 1 . U S B C o n t r o l R e g i s t e r ( U S B C O N )
1 1 -2 1
UNIVERSAL SERIAL BUS
S3C9688/P9688
U S B S I G N A L A N D S I G N A L C R O S S O V E R P O I N T C O N T R O L R E G I S T E R ( U S X CO N )
USXCON is located at address D3H and is read/write addressable. You can select protocol mode between USB PS2
and adjust USB signal crossover point.
Bit7
USB/PS2 mode select bit:
0: PS2 mode (Default)
1 : U S B m o d e ( T h i s b i t i s s e t w h e n t h e D + / P S 2 , D -/ P S 2 p o r t s e t t h e D + , D -)
Bit6
U S B P u l l -U p C o n t r o l b i t :
0 : P ull-U p D i s a b l e
1 : P u l l -U p E n a b l e
Bit5
USB signal crossover point control bit:
Edge Delay
Bit 5, (2)
Bit 4, (1)
Bit 3, (0)
Delay Value
Delay Unit
0
0
0
0
0
1
1
(about)
1
0
2
2.5 msec
1
1
4
0
0
0
0
1
1
1
0
2
1
1
4
Control
Rising
Edge
Falling
1
Edge
NOTE:
1 1 -2 2
The value is recommended by chip Vendor.
S3C9688/P9688
12
LVR (LOW VOLTAGE RESET)
LVR (LOW VOLTAGE RESET)
OVERVIEW
The S3C9688/P9688 have a LVR (Low Voltage Reset) for power on reset and voltage reset.
Reference
Start Up
Voltage
Generator
Comparator
Glitch Filter
RESET
Voltage
Divider
F i g u r e 1 2 -1 . L V R A r c h i t e c t u r e
—
L o w V o l t a g e R e s e t g e n e r a t e d RESET s i g n a l .
—
Start Up Circuit: Start up refe rence voltage generator circuit when device is powered.
—
Reference Voltage Generator: Supply Voltage independent reference voltage generator.
—
Voltage Divider: Divide supply voltage by "N"
—
Comparator: Compare reference voltage and divided voltage.
—
Glitch Filter: Remove glitch and noise signal.
1 2 -1
LVR (LOW VOLTAGE RES ET)
Vc (Compare Voltage)
S3C9688/P9688
Divide Voltage
NOTES:
Reference Voltage
1.
LVR Operation Voltage Range: 2.3 V-6.0 V
2.
LVR Detection Voltage Range: 3.4 V
3.
LVR Current Consum ption:
+ 0.4 V
4.
LVR Powered Reset Release Time:
5.
LVR Simulation Conditions (Hspice Simulation)
Less then 10 uA (normally 5 uA)
more then 500 usec (LVR only, typical)
Temp: 0 - 80
V DD (Supply Voltage)
o
C
Process Veriation: Worst to best conditions
Test Voltage: 0.0 V - 7.0 V
Reset Operation
by LVR
Powered Slew Rate: 5 V/1 usec- 5 V/100 msec
Normal Operation
F i g u r e 1 2 -2 . L V R C h a r a c t e r i s t i c s
1 2 -2
S3C9688/P9688
LVR (LOW VOLTAGE RESET)
L V R A N D P O W E R O N RESET O P E R A T I O N S
T2
Normal Operating mode
Oscillation Stabilization Time
V DD
LVD
RESET
T1
Release
LVD RESET Release Time
Internal
RESET
Release
Oscillator
(X OUT)
T3
Oscillator Stabilization Time
BTCNT
clock
10000B
BTCNT
value
00000B
t WAIT = (4096x16)/f
OSC
Basic timer increment and
CPU operations are IDLE mode
NOTES:
1.
T1 = 500 usc (at normal)
2.
T2 = T1 + (4096 x 16)/f
OSC
F i g u r e 1 2 -3 . L V R a n d P o w e r O n RESET O p e r a t i o n
1 2 -3
LVR (LOW VOLTAGE RES ET)
S3C9688/P9688
NOTES
1 2 -4
S3C9688/P9688
13
ELECTRICAL DATA
ELECTRICAL DATA
OVERVIEW
In this section, the following S3C9688/P9688 electrical characteristics are presented in tables and graphs:
—
Absolute maximum ratings
—
D.C. electrical characteristics
—
Input/Output capacitance
—
A.C. electrical characteristics
—
I n p u t t i m i n g f o r e x t e r n a l i n t e r r u p t ( P o r t s 0 , 2 , a n d 4 ) D + / P S 2 , D -/ P S 2 : P S 2 M o d e O n l y
—
Input timing for RESET
—
Oscillator characteristics
—
Oscillation stabilization time
—
Clock timing measurement points at X
—
Data retention supply voltage in Stop mode
—
Stop mode release timing when initiated by a reset
—
Stop mode release timing when initiated by an external interrupt
—
Characteristic curves
IN
1 3 -1
ELECTRICAL DATA
S 3 C9 6 8 8 / P 9 6 8 8
T a b l e 1 3 -1 . A b s o l u t e M a x i m u m R a t i n g s
(T = 2 5 °C )
A
Parameter
Symbol
Supply Voltage
V
Input Voltage
V
Output Voltage
V
Output Current High
I
Output Current Low
Operating Temperature
Storage Temperature
1 3 -2
IN
O
OL
T
T
Rating
Unit
–
– 0.3 to + 6.5
V
DD
OH
I
Conditions
A
STG
All input ports
– 0.3 to V
All output ports
– 0.3 to V
DD
DD
One I/O pin active
– 18
All I/O pins active
– 60
One I/O pin active
+ 30
Total pin current for ports 3
+ 100
Total pin current for ports 0, 1, 2, 4
+ 100
+ 0.3
V
+ 0.3
V
mA
mA
–
– 40 to + 85
°C
–
– 65 to + 150
°C
S3C9688/P9688
ELECTRICAL DATA
T a b l e 1 3 -2 . D . C . E l e c t r i c a l C h a r a c t e r i s t i c s
(T
A
=
– 4 0 °C t o + 8 5 °C , V
= 4.0 V to 5.25 V)
DD
Parameter
Symbol
Operating Voltage
V
DD
Conditions
f
OSC
= 6 MHz
Min
Typ
Max
Unit
4.0
5.0
5.25
V
V
V
(instruction clock = 1 MHz)
Input High Voltage
V
IH1
V
IH2
V
Input Low Voltage
IH3
V
V
V
Output High Voltage
V
IL1
IL2
IL2
OH
All input pins except V
X
IH2
0.8 V
V
IN
DD
DD
– 0.5
All input pins except V
–
IL2
DD
DD
DD
–
0.2 V
DD
V
0.4
IN
0.5V
RESET
I
V
0.5V
RESET
X
–
– 2 0 0 µA ; A l l o u t p u t p o r t s
=
OH
V
DD
DD
– 1.0
–
–
V
–
–
0.4
V
8
15
23
mA
–
–
3
µA
–
–
20
µA
–
–
– 3
µA
–
–
– 20
µA
except ports 0, 1 and 2, D+, D –
Output Low Voltage
V
OL
I
= 1 mA
OL
All output port except D+, D –
Output Low Current
I
OL
V
OL
= 3V
Port 3 only
Input High
I
(3)
LIH1
Leakage Current
V
IN
= V
DD
All inputs except I
LIH2
except D+, D –
I
(3)
LIH2
V
X
Input Low
I
(3)
LIL1
Leakage Current
V
IN
IN,
IN
= V
X
DD
OUT, RESET
= 0 V
All inputs except I
LIL2
except D+, D–
I
(3)
LIL2
V
X
IN
IN,
= 0 V
X
OUT, RESET
1 3 -3
ELECTRICAL DATA
S 3 C9 6 8 8 / P 9 6 8 8
T a b l e 1 3 -2 . D . C . E l e c t r i c a l C h a r a c t e r i s t i c s ( C o n t i n u e d )
(T
A
=
– 4 0 °C t o + 8 5 °C , V
= 4.0 V to 5.25 V)
DD
Parameter
Output High
Symbol
I
(1)
LOH
Leakage Current
Conditions
V
OUT
= V
DD
Min
Typ
Max
Unit
–
–
3
µA
–
–
– 3
µA
25
50
100
kΩ
2
–
5
–
5.5
12
mA
2.2
5
mA
6
15
µA
All I/O pins and output pins
except D+, D –
Output Low
I
(1)
LOL
Leakage Current
V
OUT
= 0 V
All I/O pins and output pins
except D+, D –
P u l l -u p R e s i s t o r s
R
L1
V
IN
= 0 V
P o r t s 0 , 1 , 2 , 4 . 2 -3 , R e s e t
R
Supply Current
(2)
I
L2
DD1
V
IN
= 0 V ; P 4 . 0 -1
Normal operation mode
6 MHz CPU clock
I
I
DD2
DD3
Idle mode; 6 MHz oscillator
Stop mode
NOTES :
1.
Except XIN and XOUT.
2.
Supply current does not include current drawn through internal pull-up resistors or external output current loads.
3.
1 3 -4
When USB Mode Only in 4.2 V to 5.25 V, D+ and D– satisfy the USB spec 1.1.
S3C9688/P9688
ELECTRICAL DATA
T a b l e 1 3 -3 . I n p u t / O u t p u t C a p a c i t a n c e
(T
A
– 4 0 °C t o + 8 5 °C , V
= 0 V)
DD
=
Parameter
Symbol
Input
C
IN
Capacitance
Conditions
Min
Typ
Max
Unit
f = 1 MHz; Unmeasured pins
–
–
10
pF
Min
Typ
Max
Unit
–
200
–
ns
10
–
–
µs
are connected to V
Output
C
SS
OUT
Capacitance
I/O Capacitance
C
IO
T a b l e 1 3 -4 . A . C . E l e c t r i c a l C h a r a c t e r i s t i c s
(T
A
=
– 4 0 °C t o + 8 5 °C , V
Parameter
Interrupt Input
DD
= 4.0 V to 5.25 V)
Symbol
t
INTH
, t
INTL
Conditions
P0, P2 and P4
High, Low Width
RESET Input
Low
t
RSL
RESET
Width
tINTH
tINTL
tRSL
0.8 V
0.2 V
DD
DD
F i g u r e 1 3 -1 . I n p u t t i m i n g f o r E x t e r n a l I n t e r r u p t ( P o r t s 0 , 2 , a n d 4 )
t RSL
RESET
0.5 V
DD
F i g u r e 1 3 -2 . I n p u t T i m i n g f o r RESET
1 3 -5
ELECTRICAL DATA
S 3 C9 6 8 8 / P 9 6 8 8
T a b l e 1 3 -5 . O s c i l l a t o r C h a r a c t e r i s t i c s
(T
– 4 0 °C + 8 5 °C , V
= 4.0 V to 5.25 V)
DD
=
A
Oscillator
Clock Circuit
Test Condition
Min
Typ
Max
Unit
Oscillation frequency
–
6.0
–
MHz
Oscillation frequency
–
6.0
–
Min
Typ
Max
Unit
–
–
10
ms
stop m ode release time by a reset
–
2 16/ f
stop mode release time by an interrupt
–
Main crystal Main
ceramic (f
OSC
XIN
)
XOUT
External clock
XIN
XOUT
T a b l e 1 3 -6 . O s c i l l a t i o n S t a b i l i z a t i o n T i m e
(T
A
– 4 0 °C + 8 5 °C , V
= 4.0 V to 5.25 V)
DD
=
Oscillator
Test Condition
Main Crystal
f
Main Ceramic
(Oscillation stabilization occurs when V
OSC
= 6.0 MHz
DD
is equal to
the minimum oscillator voltage range.)
Oscillator
t
WAIT
–
OSC
Stabilization Wait
Time
t
N O T E:
WAIT
–
(note)
The oscillator stabilization wait time, tWAIT, is determined by the setting in the basic timer control register, BTCON.
T a b l e 1 3 -7 . D a t a R e t e n t i o n S u p p l y V o l t a g e i n S t o p M o d e
(T
A
=
– 4 0 °C t o + 8 5 °C )
Parameter
Data Retention
Symbol
V
DDDR
Conditions
Stop mode
Min
Typ
Max
Unit
2.0
–
6
V
–
–
300
µA
Supply Voltage
Data Retention
Supply Current
1 3 -6
I
DDDR
Stop mode; V
DDDR
= 2.0 V
S3C9688/P9688
ELECTRICAL DATA
Internal Reset
Operation
IDLE Mode
~
(Basic Timer Active)
Stop Mode
Data Retention Mode
~
~
V DD
Normal
V DDDR
Operating
Execution of
Mode
Stop Instrction
RESET
0.5 V
DD
0.5 V
DD
t WAIT
F i g u r e 1 3 -3 . S t o p M o d e R e l e a s e T i m i n g W h e n I n i t i a t e d b y a R e s e t
IDLE Mode
~
~
(Basic Timer Active)
Stop Mode
Data Retention Mode
~
~
V DD
Normal
V DDDR
Operating
Execution Of
External
Mode
Stop Instrction
Interrupt
0.8 V
0.2 V
DD
DD
t WAIT
F i g u r e 1 3 -4 . S t o p M o d e R e l e a s e T i m i n g W h e n I n i t i a t e d b y a n E x t e r n a l I n t e r r u p t
1 3 -7
ELECTRICAL DATA
S 3 C9 6 8 8 / P 9 6 8 8
T a b l e 1 3 -8 . L o w S p e e d U S B E l e c t r i c a l C h a r a c t e r i s t i c s
(T
=
A
– 4 0 °C t o + 8 5 °C , V o l t a g e R e g u l a t o r O u t p u t V
Parameter
= 2.8 V to 3.5 V, typ 3,3 V)
33out
Symbol
Conditions
Min
Max
Unit
CL = 50 pF
75
–
ns
CL = 350 pF
–
300
CL = 50 pF
75
–
CL = 350 pF
–
300
Transition Time:
Rise Time
Tr
Fall Time
Tf
Rise/Fall Time Matching
Trfm
(Tr/Tf) CL = 50 pF
80
120
%
Output Signal Crossover Voltage
Vcrs
CL = 50 pF
1.3
2.0
V
Voltage Regulator Output Voltage
V
with V
2.8
3.5
V
33OUT
33OUT
t o G N D 0 . 1 µF
capacitor
Test
2.8 V
Point
90 %
90 %
Measurement
S/W
Points
R2
10 %
D. U. T
R1
10 %
C2
Tr
Tf
R1 = 15 K Ω
DM: S/W ON
R2 = 1.5 K Ω
DP: S/W OFF
CL = 50 pF - 350 pF
F i g u r e 1 3 -5 . U S B D a t a S i g n a l R i s e a n d F a l l T i m e
3.3 V
DP
MAX: 2.0 V
Vcrs
MIN: 1.3 V
DM
0V
F i g u r e 1 3 -6 . U S B O u t p u t S i g n a l C r o s s o v e r P o i n t V o l t a g e
1 3 -8
S3C9688/P9688
ELECTRICAL DATA
T a b l e 1 3 -9 . L o w S p e e d U S B E l e c t r i c a l C h a r a c t e r i s t i c s
(T
A
=
– 4 0 °C t o + 8 5 °C )
Parameter
Low level detect voltage
Symbol
V
LVD
Conditions
Min
Typ
Max
Unit
–
3.00
3.40
3.80
V
1 3 -9
ELECTRICAL DATA
S 3 C9 6 8 8 / P 9 6 8 8
NOTES
1 3 -1 0
S3C9688/P9688
14
MECHANICAL DATA
MECHANICAL DATA
OVERVIEW
T h e S 3 C 9 6 8 8 / P 9 6 8 8 i s a v a i l a b l e i n a 4 2 -p i n S D I P p a c k a g e ( S a m s u n g : 4 2 -S D I P -6 0 0 ) a n d a 4 4 -p i n Q F P p a c k a g e
( 4 4 -Q F P -1 0 1 0 B ) . P a c k a g e d i m e n s i o n s a r e s h o w n i n F i g u r e s 1 4 -1 a n d 1 4 -2 .
#42
#22
± 0.5
16.30
0.2
5
14.00
42-SDIP-600
+0
.
-0 1
.05
15.24
± 0.2
0-15
NOTE :
1.00
± 0.1
± 0.2
1.78
± 0.3
± 0.1
5.08 MAX
(1.77)
0.50
3.30
39.10
± 0.2
39.50 MAX
3.50
#21
0.51 MIN
#1
Dimensions are in millimeters.
F i g u r e 1 4 -1 . 4 2 -P i n S D I P P a c k a g e M e c h a n i c a l D a t a ( 4 2 -S D I P -6 0 0 )
1 4 -1
MECHANICAL DATA
S 3 C9 6 8 8 / P 9 6 8 8
13.20
+ 0.3
10.00
+ 0.2
0-8
+ 0.10
- 0.05
+ 0.2
44-QFP-1010B
0.10 MAX
0.80 + 0.20
10.00
13.20
+ 0.3
0.15
#44
#1
+ 0.10
0.35
- 0.05
0.80
0.05 MIN
(1.00)
2.05
+ 0.10
2.30 MAX
NOTE : Dimensions are in millimeters.
F i g u r e 1 4 -2 . 4 4 -P i n Q F P P a c k a g e M e c h a n i c a l D a t a ( 4 4 -Q F P -1 0 1 0 B )
1 4 -2
S3C9688/P9688
S3P9688 OTP
15
S3P9688 OTP
OVERVIEW
T h e S 3 P 9 6 8 8 s i n g l e -c h i p C M O S m i c r o c o n t r o l l e r i s t h e O T P ( O n e T i m e P r o g r a m m a b l e ) v e r s i o n o f t h e S 3 C 9 6 8 8
m i c r o c o n t r o l l e r . I t h a s a n o n -c h i p O T P R O M i n s t e a d o f m a s k e d R O M . T h e E P R O M i s a c c e s s e d b y s e r i a l d a t a
format.
The S3P9688 is fully compatible with the S3C9688, both in function and in pin configuration. Because of its simple
programming requirements, the S3P9688 is ideal for use as an evaluation chip for the S3C9688.
1
42
2
41
P3.2
P3.3/CLO
INT0/P2.0
3
40
D+/PS2
INT0/P2.1
4
39
D-/PS2
INT0/P2.2
5
38
INT0/P2.3
INT0/P2.4
INT0/P2.5
6
37
7
36
3.3V OUT
NC
P0.0/INT2
8
35
P0.1/INT2
9
34
P0.2/INT2
10
33
P0.3/INT2
P0.4/INT2
P3.1
P3.0
SDAT /INT0/P2.6
SCLK /INT0/P2.7
VDD/V DD
VSS/V SS
XOUT/X OUT
XIN /X IN
TEST /TEST
32
(42-SDIP)
13
30
P0.5/INT2
P0.6/INT2
14
29
P0.7/INT2
15
28
P1.0
INT1/P4.0
16
27
INT1/P4.1
17
26
12
31
18
25
P1.1
P1.2
P1.3
INT1/P4.2
19
24
P1.4
INT1/P4.3
20
23
P1.5
21
22
P1.6
RESET /RESET
P1.7
NOTE:
S3P9688
11
The TEST pin must be connected to V
SS
(GND) in normal operation mode.
Th pins which used in writing OTP-ROM codes are assigned in bold.
F i g u r e 1 5 -1 . S 3 P 9 6 8 8 P i n A s s i g n m e n t s ( 4 2 -S D I P P a c k a g e )
1 5 -1
S3C9688/P9688
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
P0.0/INT2
P0.1/INT2
P0.2/INT2
P0.3/INT2
P0.4/INT2
P0.5/INT2
P0.6/INT2
P0.7/INT2
S3P9688 OTP
3.3V
OUT
34
D- /PS2
D+/PS2
35
CLO/P3.3
37
P3.2
P3.1
P3.0
38
39
40
41
P2.1/INT0
42
20
P1.0
P1.1
P1.2
19
P1.3
S3P9688
18
44-QFP
17
P1.4
P1.5
(Top View)
16
15
14
43
13
44
12
P1.6
P1.7
P4.3/INT1
P4.2/INT1
RESET/RESET
INT0/P2.4
INT0/P2.5
SDAT /INT0/P2.6
SCLK /INT0/P2.7
V DD /V DD
V SS /V SS
X OUT /X OUT
X IN /X IN
TEST /TEST
INT1/P4.0
INT1/P4.1
1
2
3
4
5
6
7
8
9
10
11
P2.3/INT0
21
36
P2.0/INT0
P2.2/INT0
22
NOTE:
The TEST pin must connect to V
SS
(GND) in the normal operation mode.
The bold is assigned to OTP pin name.
F i g u r e 1 5 -2 . S 3 P 9 6 8 8 P i n A s s i g n m e n t s ( 4 4 -Q F P P a c k a g e )
1 5 -2
S3C9688/P9688
S3P9688 OTP
T a b l e 1 5 -1 . D e s c r i p t i o n s o f P i n s U s e d t o R e a d / W r i t e t h e E P R O M
Main Chip
During Programming
Pin Name
Pin Nam e
P2.6
SDAT
Pin No.
9
I/O
I/O
(3)
Function
Serial Data Pin (Output when reading, Input when
w r i t i n g ) I n p u t a n d P u s h-p u l l O u t p u t P o r t c a n b e
assigned
P2.7
SCLK
10
(4)
I/O
TEST
TEST
15
(9)
I
Serial Clock Pin (Input Only Pin)
Chip Initialization and EPROM Cell Writing Power
Supply Pin (Indicates OTP Mode Entering) When
writing 12.5 V is applied and when reading.
RESET
18
RESET
I
(12)
0 V: OTP write and test mode
5 V: Operating mode
V
DD
NOTE:
/ V
V
SS
DD
/ V
1 1 (5) / 1 2 (6)
SS
–
Logic Power Supply Pin.
( ) means 44 QFP package.
T a b l e 1 5 -2 . C o m p a r i s o n o f S 3 P 9 6 8 8 a n d S 3 C 9 6 8 8 F e a t u r e s
Characteristic
S3P9688
Program Memory
Operating Voltage (V
DD
)
S3C9688
8 -K b y t e E P R O M
8 -K b y t e m a s k R O M
4.0 V to 5.25 V
4.0 V to 5.25 V
OTP Programming Mode
V
Pin Configuration
42 SDIP/44 QFP
42 SDIP/44 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
DD
= 5 V, V
PP
(RESET) = 12.5 V
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the V
PP
( RESET ) p i n o f t h e S 3 P 9 6 8 8 , t h e E P R O M p r o g r a m m i n g m o d e i s e n t e r e d . T h e
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table
1 5 -3 b e l o w .
T a b l e 1 5 -3 . O p e r a t i n g M o d e S e l e c t i o n C r i t e r i a
V DD
5 V
N O T E:
Vpp
REG/
Address
(RESET)
MEM
( A 1 5 –A 0 )
R/W
Mode
5 V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
"0" means Low level; "1" means High level.
1 5 -3
S3P9688 OTP
S3C9688/P9688
START
Address = First Location
V DD = 5V, V
PP
= 12.5V
x=0
Program One 1ms Pulse
Increment X
YES
x = 10
NO
FAIL
Verify Byte
Verify 1 Byte
Last Address
FAIL
NO
V DD = V PP = 5 V
FAIL
Compare All Byte
PASS
Device Passed
Device Failed
F i g u r e 1 5 -3 . O T P P r o g r a m m i n g A l g o r i t h m
1 5 -4
Increment Address
S3C9688/P9688
S3P9688 OTP
T a b l e 1 5 -4 . D . C . E l e c t r i c a l C h a r a c t e r i st i c s
(T
A
=
– 4 0 °C t o + 8 5 °C , V
= 4.0 V to 5.25 V)
DD
Parameter
Supply Current
Symbol
I
DD1
Conditions
Normal mode;
Min
Typ
Max
Unit
–
5.5
12
mA
2.2
5
6
15
6 MHz CPU clock
(note)
I
DD2
Idle mode;
6 MHz CPU clock
I
N O T E:
DD3
Stop mode
µA
Supply current does not include current drawn through internal pull-up resistors or external output current loads.
1 5 -5
S3P9688 OTP
S3C9688/P9688
NOTES
1 5 -6
S3C9688/P9688
16
DEVELOPMENT TOOLS
DEVELOPMENT TOOLS
OVERVIEW
S a m s u n g p r o v i d e s a p o w e r f u l a n d e a s y -t o -u s e d e v e l o p m e n t s u p p o r t s y s t e m i n t u r n k e y f o r m . T h e d e v e l o p m e n t
support system is configured with a host system, debugging tools, and support software. For the host system, any
s t a n d a r d c o m p u t e r t h a t o p e r a t e s w i t h M S -D O S a s i t s o p e r a t i n g s y s t e m c a n b e u s e d . O n e t y p e o f d e b u g g i n g t o o l
i n c l u d i n g h a r d w a r e a n d s o f t w a r e i s p r o v i d e d : t h e s o p h i s t i c a t e d a n d p o w e r f u l i n -c i r c u i t e m u l a t o r , S M D S 2 + , f o r S 3 C 7 ,
S3C9, S3C8 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also
offers support software that includes debugger, assembler, and a program for setting options.
SHINE
S a m s u n g H o s t I n t e r f a c e f o r in -c i r c u i t E m u l a t o r , S H I N E , i s a m u l t i -w i n d o w b a s e d d e b u g g e r f o r S M D S 2 + . S H I N E
p r o v i d e s p u l l -d o w n a n d p o p -u p m e n u s , m o u s e s u p p o r t , f u n c t i o n / h o t k e y s , a n d c o n t e x t-s e n s i t i v e h y p e r-l i n k e d h e l p . I t
h a s a n a d v a n c e d , m u l t i p l e -w i n d o w e d u s e r i n t e r f a c e t h a t e m p h a s i z e s e a s e o f u s e . E a c h w i n d o w c a n b e s i z e d , m o v e d ,
scrolled, highlighted, added, or removed completely.
SAMA ASSEMBLER
The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates object
c ode in standard hexadecimal format. Assembled program code includes the object code that is used for ROM data
and required SMDS program control data. To assemble programs, SAMA requires a source file and an auxiliary
definition (DEF) file with device specific information.
SASM86
T h e S A S M 8 6 i s a n r e l o c a t a b l e a s s e m b l e r f o r S a m s u n g ' s S 3 C 9 -s e r i e s m i c r o c o n t r o l l e r s . T h e S A S M 8 6 t a k e s a s o u r c e
file containing assembly language statements and translates into a corresponding source code, object code and
c o m m e n t s . T h e S A S M 8 6 s u p p o r t s m a c r o s a n d c o n d i t i o n a l a s s e m b l y . I t r u n s o n t h e M S -D O S o p e r a t i n g s y s t e m . I t
produces the relocatable object code only, so the user should link object file. Object files can be linked with other
object files and loaded into memory.
HEX2ROM
HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be
needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by
H E X 2 R O M , t h e va l u e " F F " i s f i l l e d i n t o t h e u n u s e d R O M a r e a u p t o t h e m a x i m u m R O M s i z e o f t h e t a r g e t d e v i c e
automatically.
1 6 -1
DEVELOPMENT TOOLS
S3C9688/P9688
TARGET BOARDS
T a r g e t b o a r d s a r e a v a i l a b l e f o r t h e t e s t o f a l l S 3 C 9 -s e r i e s m i c r o c o n t r o l l e r s . A l l r e q u i r e d t a r g e t s y s t e m c a b l e s a n d
a d a p t e r s a r e i n c l u d e d w i t h t h e d e v i c e-s p e c i f i c t a r g e t b o a r d .
OTPs
One times programmable microcontrollers (OTPs) are under development for S3C9688/P9688 microcontroller.
IBM-PC AT or
Compatible
SMDS2+
RS-232C
Target
PROM/OTP Writer Unit
Application
System
RAM Break/Display Unit
Probe
BUS
Adapter
Trace/Timer Unit
POD
SAM4 Base Unit
TB9688
Target
Board
EVA
Power Supply Unit
Chip
F i g u r e 1 6 -1 . S M D S P r o d u c t C o n f i g u r a t i o n ( S M D S 2 + )
1 6 -2
S3C9688/P9688
DEVELOPMENT TOOLS
TB9688 TARGET BOARD
The TB9688 target board is used for the S3C9688/P9688 microcontrollers. It is supported by the SMDS2+
development systems. The TB9688 target board can also be used for S3C9688/P9688.
TB9688
To User_V
On
Idle
Stop
+
+
GND
U2
RESET
V CC
Off
CC
25
J101
100-Pin
Connector
80
41
40
81
1
50
160 QFP
CN1
S3E9680
EVA Chip
50-Pin
Connector
1
120
160
121
1
U1
SEL0
H
Y2
SEL1
H
EXTTRIG1
EXTTRIG2
SMDS2
L
L
25
26
SMDS2+
F i g u r e 1 6 -2 . T B 9 6 8 8 T a r g e t B o a r d C o n f i g u r a t i o n
1 6 -3
DEVELOPMENT TOOLS
S3C9688/P9688
T a b l e 1 6 -1 . P o w e r S e l e c t i o n S e t t i n g s f o r T B 9 6 8 8
'To User_Vcc' Settings
Operating Mode
Comments
The SMDS2/SMDS2+ supplies
To User_VCC
Off
V
TB9688
Target
V CC
On
CC
to the target board
(evaluation chip) and the target
System
system.
V SS
V CC
SMDS2/SMDS2+
The SMDS2/SMDS2+ supplies
To User_V
Off
CC
TB9688
External
V CC
On
V
Target
CC
only to the target board
(evaluation chip). The target
System
system must have its own
V SS
power supply.
V CC
SMDS2+
N O T E:
The following symbol in the "To User_VCC" Setting column indicates the electrical short (off) configuration:
SMDS2+ Selection (SAM8)
In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for
SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available.
T a b l e 1 6 -2 . T h e S M D S 2 + T o o l S e l e c t i o n S e t t i n g
"SW1" Setting
SMDS2
Operating Mode
SMDS2+
R/W*
R/W*
Target
Board
SMDS2+
SMDS2
SMDS2+
R/W*
Target
R/W* is not
SMDS2+
1 6 -4
available
Board
S3C9688/P9688
DEVELOPMENT TOOLS
T a b l e 1 6 -3 . T h e ' S E L 0 , S E L 1 ' S e l e c t i o n S e t t i n g
'SEL0, SEL1' Settings
H
Comments
H
This 'SEL0, SEL1' Pin is not Used.
(No Connected)
L
L
SEL0
SEL1
T a b l e 1 6 -4 . U s i n g S i n g l e H e a d e r P i n s a s t h e I n p u t P a t h f o r E x t e r n a l T r i g g e r S o u r c e s
Target Board Part
Comments
Connector from
external Trigger
sources of the
EXTTRIG1
CH1
EXTTRIG2
CH2
application System
You can connect an external trigger source to one of the two external
trigger channels (CH1 or CH2) for the SMDS2+ breakpoint and trace
functions.
1 6 -5
DEVELOPMENT TOOLS
S3C9688/P9688
J101
1
42
P3.2
P3.0
2
41
P3.3/CLO
P2.0/INT0
3
40
D+/PS2
P2.1/INT0
4
39
D-/PS2
P2.2/INT0
5
38
P2.3/INT0
P2.4/INT0
6
37
3.3V OUT
N.C
7
36
P0.0/INT2
P2.5/INT0
8
35
P0.1/INT2
P2.6/INT0
P2.7/INT0
V DD
9
34
P0.2/INT2
33
31
P0.3/INT2
P0.4/INT2
P0.5/INT2
42-Pin Connector
P3.1
10
11
32
V SS
12
X OUT
13
30
P0.6/INT2
X IN
14
29
P0.7/INT2
TEST
P4.0/INT1
15
28
16
27
P4.1/INT1
RESET
17
26
P1.0
P1.1
P1.2
18
25
P1.3
P4.2/INT1
19
24
P1.4
P4.3/INT1
P1.7
20
23
P1.5
21
22
P1.6
F i g u r e 1 6 -3 . 4 2 P i n C o n n e c t o r f o r T B 9 6 8 8
Target Board
Target System
1
J101
1
J101
1
50
User System
50
42
50-Pin DIP
Connector
Part Name: (AP42SD-J)
Probe for User
Order Code: SM6524
25
System
21
26
25
22
26
F i g u r e 1 6 -4 . S 3 C 9 6 8 8 P r o b e A d a p t e r C a b l e f o r 4 2 -S D I P P a c k a g e
1 6 -6