RF SIGNAL PROCESSOR S5L1462B INTRODUCTION 80-QFP-1420C The S5L1462B01 is used for CD and DVD playback. It receives optical signal from the optical pick-up to produce the data-generating RF signal, the servo error signal for stable servo control, and the monitor signal. This RF IC can be used in the CD 1x, 2x, or the DVD 1x CLV (Constant Linear Velocity) mode. The DVD mode is compatible with the Single/Dual Layer disc. The CD mode is compatible with the CD-ROM, CD-R and CD-RW disc. FEATURES • Can be used with CD 1x, 2x, and DVD 1x playback mode. • Able to input and handle all optical signal of the CD-R's P/U. • Built-in pre-amp with adjustable gain, compatible with various P/U. • Built-in AGC (Automatic Gain Control) circuit operated by light detection feedback. • Built-in RF AMP & Equalizer compatible with CD 1x, 2x, and DVD 1x. • Built-in Astigmatism Method FE (Focus Error) AMP for CD and DVD use. • Built-in 3-BEAM TE (Tracking Error) AMP for CD. • Built-in 1-BEAM DPD (Differential Phase Detector) TE AMP for DVD. • Built-in RF mirror detection circuit for CD and DVD. • Built-in RF defect detection circuit for CD and DVD. • Built-in FOK (Focus O.K.) signal detection circuit for CD and DVD. • Built-in RF envelope signal generating circuit for CD and DVD. • Built-in interrupt defect detection circuit. • Built-in ALPC (Automatic Laser Power Control) circuit for CD and DVD. • Built-in standard voltage generating circuit for analog circuit use (2.5V, 1.65V). • Built-in defective waveform detection circuit. • Power operating range: 4.5 – 5.5 V, 3.0 – 3.6 V. • 80 PIN, QFP. ORDERING INFORMATION Device Package Temperature Range S5L1462B01-Q0R0 80-QFP-1420C -25 to +70°C 1 S5L1462B RF SIGNAL PROCESSOR RFSUM 1 ADVD BDVD 2 3 DDVD 4 RREFBF RREFEQ 6 7 RREF 8 ADVD1 BDVD1 CDVD1 DDVD1 AVCC 9 16 F 17 19 20 LD0CD PDCD 21 22 AGND 23 FE 24 MIRRI 65 EQVCC EQIN 71 AGC10 RFAGCO 72 66 AGCC 73 AGC1C EOGND 74 GCA EQ VC AMP EQ A+C B+D EQ PDLIMITRES FAULT Defective waveform OUT detection circuit COM + ALPC to DPD Block VREFAOF VREFA + - Interruption Detect MUX CP1 63 CB1 62 RFRP 61 60 CP2 Cpeak 59 RFCT 58 RESET 57 56 STB CLOCK 55 DATA 54 PDLIMITERS 53 VREFDPD 52 DPDGND 51 TE1RES 50 PLLCTL 49 48 FAULTOUT DPDEQ2 47 DPDEQ1 46 MIRR 45 DPDVCC 44 INTER0 43 INTER1 42 PLLDFT 41 DFCT1 TE38 GAIN_TE3 TFOFST TE MUX TE_ SEL INT_ONB INTER_TH FOK_TH DFCTTH1 LPF DFCTTH2 LPF 10dB 10dB ALPC_SEL ENVELOPE FOK DEFECT ANALOG VC1 AMP INTER Detect 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 INTERB TE AVCC1 VREFA1 ABCD ABCDI ENVP ENVB ENV GND FOKB DFCT_CP1 DFCT_CP2 CC1 CC2 DVCC INTER_ONB 2 64 VREFA + GAIN_FE FEOFST DPD VC AMP PLLCTL FLT_CTL HOLD_CTL VREFA1 ANALOG FEOFST VC AMP S/IF Block COM GAIN_ABCD DPDEQ2 ABCDOFST + GCA - 18 LD0DVD PDDVD 67 AGCBO 75 GCA 14 15 68 AGCB 76 AGC1IN AGCP 77 TE1 Front MUX 10 11 12 13 E VBGRO 69 RDPF 78 VREF GAIN_FE - VREFA MUX6 RFRP AGCI RF Equalizer EQ_FREQ. RFSUM $ RF EQ_BOOST RFCT & AGC AMP MUX PLLCTL PD_LIMIT SW_CON MIRR GAIN_RFUM SW_CON1 TBAL DPDMUTE TE10FST AGC_HOLD Cpeak GAIN_TE1 AGC_LVL Phase DPDEQ1 VCPS LPS detector GCA VREFEQ RFEQO VZ0CTL 79 to RF EQ AGC_DET tuning block PD_POL RFSUM_SEL 70 PLLGF 80 BLOCK DIAGRAM RF SIGNAL PROCESSOR S5L1462B PIN DESCRIPTION No. Name I/O 1 RFSUM I 2 ADVD 3 Description Related Blocks Related Parts RF optical's main beam RFSUM AC Coupling input pin PRE AMP P/U I RF optical's main beam A AC Coupling input pin PRE AMP P/U BDVD I RF optical's main beam B AC Coupling input pin PRE AMP P/U 4 CDVD I RF optical's PRE AMP P/U 5 DDVD I RF optical's main beam D AC Coupling input pin PRE AMP P/U 6 RREFBF - RF AMP I/O Buffer Bias resistance connection pin RF AMP - 7 RREFEQ - RF EQ Bias resistance connection pin RF EQ - 8 RREF - ANALOG Block Bias resistance connection pin ANALOG - 9 VREFEQ O RF EQ Center voltage CAP connection pin EQ VC AMP - 10 ADVD1 I SERVO optical's main beam A input pin SERVO AMP P/U 11 BDVD1 I SERVO optical's main beam B input pin SERVO AMP P/U 12 CDVD1 I SERVO optical's main beam C input pin SERVO AMP P/U 13 DDVD1 I SERVO optical's main beam D input pin SERVO AMP P/U 14 AVCC P ANALOG Part power voltage (5 V) input pin ANALOG - 15 VREFA ANA VC AMP SERVO 16 E I SERVO CD optical's sub beam E input pin TE 3B P/U 17 F I SERVO CD optical's sub beam F input pin TE 3B P/U 18 VBGRO ALPC - 19 LDODVD O DVD optical's Laser Diode operating voltage output pin ALPC P/U 20 PDDVD I DVD optical's Laser Monitor Diode voltage input pin ALPC P/U 21 LDOCD O CD optical Laser Diode operating voltage output pin ALPC P/U 22 PDCD I CD optical Laser Monitor Diode voltage input pin ALPC P/U 23 AGND P ANALOG Part power GND pin ANALOG - 24 FE O FE AMP output pin FE AMP DSSP 25 INTERB O Interruption button detection time constant cap. connection INTERRUPTION SERVO 26 TE O TE AMP output pin TE AMP DSSP 27 AVCC1 P ANALOG Part power voltage (3.3 V) input pin ANALOG - 28 VREFA1 ANA VC1 AMP - 29 ABCD O ABCD AMP output pin ABCD AMP - 30 ABCDI I SERVO MONITOR ABCD AC Coupling input pin SERVO MONIT - main beam C AC Coupling input pin -/O ANALOG Part Center voltage CAP connection pin. Uses another block. I/O ALPC Bandgap voltage input and bandgap output pin -/O ANALOG Part Center voltage1 (1.65 V) CAP connection pin 3 S5L1462B RF SIGNAL PROCESSOR PIN DESCRIPTION (Continued) No. Name I/O 31 ENVP - 32 ENVB 33 4 Description Related Blocks Related Parts RF ENVELOPE detecting Peak Hold time constant selection RC connection pin RF ENV - - RF ENVELOPE detecting Bottom Hold time constant selection RC connection pin RF ENV - ENV O RF ENVELOPE Detect output pin RF ENV DSSP 34 DGND P DIGITAL Circuit power GND input pin DIGITAL - 35 FOKB O FOCUS OK Comparator output pin (L: FOCUS OK) FOKB DSSP 36 DFCT_CP1 - SERVO DEFECT maximum time selection Peak Hold time constant connection pin DFCT - 37 DFCT_CP2 - PLL DEFECT minimum time selection Peak Hold time constant connection pin DFCT - 38 CC1 O DEFECT peak detector circuit output pin DFCT - 39 CC2 I DEFECT AC Coupling input pin DFCT - 40 DVCC P DIGITAL circuit power voltage (5 V) input pin DIGITAL - 41 DFCT1 O SERVO DEFECT output pin DEFECT DSSP 42 PLLDFT O PLL DEFECT output pin DEFECT PLL 43 INTERO O INTERRUPT Defect Detection output pin INTERRUPT - 44 INTERI I INTERRUPT Defect Detection input pin INTERRUPT - 45 DPDVCC P DPD TE power voltage (5V) input pin DPD - 46 MIRR O MIRROR output pin MIRR DSSP 47 DPDEQ1 O DPD EQ (A+C) output pin DPD - 48 DPDEQ2 O DPD EQ (B+D) output pin DPD - 49 FAULTOUT O DPD abnormal waveform output pin (MONITOR) DPD - 50 PLLCTL I DPD TE PLL variable input pin DPD SERVO 51 TE1RES I DPD TE PLL variable bias resistance DPD - 52 DPDGND P DPD TE power GND input pin DPD - 53 VREFDPD O DPD TE CENTER voltage CAP connection pin DPD VC AMP - 54 PDLIMITRES - PDLIMITK BIAS resistance connection pin DPD - 55 DATA I DATA input pin Serial Interface MICOM 56 CLOCK I CLOCK input pin Serial Interface MICOM 57 STB I DATA ENABLE input pin Serial Interface MICOM 58 RESET I Serial Register Reset pin Serial Interface MICOM 59 RFCT O MIRROR RF RIPPLE CENTER voltage output pin MIRROR DSSP 60 Cpeak - AGC/AGC1 peaking protection SW control voltage input pin AGC/AGC1 - RF SIGNAL PROCESSOR S5L1462B PIN DESCRIPTION (Continued) No. Name I/O 61 CP2 - 62 RFRP 63 Description Related Blocks Related Parts RFCT generating PEAK HOLD time constant RC connection pin MIRROR - O MIRROR RF RIPPLE AMP output pin MIRROR DSSP CB1 - RFRP generating BOTTOM HOLD time constant RC connection pin MIRROR - 64 CP1 - RFRP generating PEAK HOLD time constant RC connection pin MIRROR - 65 MIRRI I MIRR signal generating input pin MIRROR - 66 EQVCC P RF EQ power voltage input pin RF EQ - 67 AGC1O O RF AGC1 AMP output pin RF AGC1 - 68 AGC1C - AGC1 time constant CAP connection pin RF AGC1 - 69 AGC1IN I RF AGC1 AMP input pin RF AGC1 - 70 RFEQ0 O RF EQ output pin RF EQ PLL 71 EQIN I RF EQ RFAGCO input pin RFEQ RFENV DSSP 72 RFAGCO O RF AGC AMP output pin RF AGC - 73 AGCC - AGC time constant CAP connection pin RF AGC - 74 EQGND P RF EQ power GND input pin RF EQ - 75 AGCBO - RF EQ BIAS resistance connection pin RF EQ - 76 AGCB - RF AGC RF BOTTOM HOLD time constant RC connection pin RF AGC - 77 AGCP - RF AGC RF PEAK HOLD time constant RC connection pin RF AGC - 78 RDPF - RF EQ FREQUENCY selection BIAS resistance connection pin RF EQ - 79 VZOCTL I RF EQ zero control voltage RF EQ DSSP 80 PLLGF I Wide range PLL RF EQ BOOST, PEAK FREQUENCY GAIN control pin (internally designed PLLG, PLLF resistance) RF EQ DSSP 5 S5L1462B RF SIGNAL PROCESSOR ABSOLUTE MAXIMUM RATINGS (Ta = 25°C) Item Power Voltage Operating Temperature Power Expenditure Storage Temperature Item Symbol Standard Value Unit Vs 6 V Temp -25 to +70 °C PD 1100 mW Tstg -40 to +125 °C Symbol Standard Value Unit MIN TYP MAX Power Voltage Vo 4.75 5 5.25 V Operating Current Ic - 120 160 mA 6 Notes Notes RF SIGNAL PROCESSOR S5L1462B ELECTRICAL CHARACTERISTICS (V CC = 5V, VCC1 = 3.3V, GND = 0V, Vc = 2.5V, Vc1 = 1.65V Ta = 25°C, VC is center of standard output voltage.) No Item Symbol Input Measuring point Min. Output Typ. Max. Unit CIRCUIT CURRENT 1 Supply current IccL vdd=4.5V,TE1 BLOCK operation 80 100 120 mA 2 3 Supply current IccT Supply current IccH vdd=5V,TE1 BLOCK operation 100 120 140 mA vdd=5.5V,TE1 BLOCK operation 120 140 160 mA Vrfsum1 RFSUM=1MHz, 1.5Vpp, RFSUM_SEL=0 GAIN_RFSUM=0dB, DVD Mode Vrfsum2 RFSUM=1MHz, 1Vpp,RFSUM_SEL=0 GAIN_RFSUM=0dB, DVD Mode 6 Vrfsum3 RFSUM=1MHz, 0.1Vpp, RFSUM_SEL=0 GAIN_RFSUM=20dB, CD Mode 0.8 1 1.2 Vpp 7 Vrfsum4 (A-D)DVD=1MHz, 0.25Vpp, RFSUM_SEL=1 GAIN_RFSUM=0dB, DVD Mode Frfsum1 RFSUM=Freq. Sweep, 1.0Vpp, RFSUM_SEL=0, GAIN_RFSUM=0dB,DVD Mode 10 - - MHz Frfsum2 RFSUM=Freq. Sweep, 0.1Vpp, RFSUM_SEL=0, GAIN_RFSUM=20dB,CD Mode 5 - - Gagc1 RFSUM=1MHz, 2Vpp, RFSUM_SEL=0 GAIN_RFSUM=0dB, DVD Mode 0.8 1.0 1.2 Gagc2 RFSUM=1MHz, 0.5Vpp, RFSUM_SEL=0 GAIN_RFSUM=0dB, DVD Mode Vagc1 RFSUM=1MHz, 1Vpp, RFSUM_SEL=0 GAIN_RFSUM=0dB, AGC_LVL=00H, DVD Mode 0.3 0.5 0.7 13 Vagc2 RFSUM=1MHz, 1Vpp, RFSUM_SEL=0 GAIN_RFSUM=0dB, AGC_LVL=10H, DVD Mode 0.55 0.75 0.95 14 Vagc3 RFSUM=1MHz, 1Vpp, RFSUM_SEL=0 GAIN_RFSUM=0dB, AGC_LVL=11H, DVD Mode 1.00 1.25 1.50 RF SUM & AGC AMP 4 5 8 RF Sum Amp Voltage Gain RF Sum Amp Unit Gain Bandwidth 9 10 AGC Voltage Gain 11 12 AGC AMP Out. LEVEL Adjust RANGE RFAGCO (AGC_LVL=0 1H,) RFAGCO (AGCHOLD= L) Vpp Vpp 7 S5L1462B RF SIGNAL PROCESSOR ELECTRICAL CHARACTERISTICS (Continued) No Item Symbol Input Measuring Output Unit point Min. Typ. Max. AGC1 15 AGC1 Out. Level Vagc1 AGC1IN:sin 0.5Vpp 5MHz dc 2.5V AGC1_HOLD: 1, AGC1_LVL:01, AGC1_ON:0 AGC10 0.8 1 1.2 Vpp 16 AGC1 Out. Level 1 Vagc11 AGC1IN:sin 0.5Vpp 5MHz dc 2.5V AGC1_HOLD:1, AGC1_LVL:00, AGC1_ON:0 AGC10 0.6 0.75 0.9 Vpp 17 AGC1 Out. Level 2 Vagc12 AGC1IN:sin 0.5Vpp 5MHz dc 2.5V AGC1_HOLD: 1, AGC1_LVL:11, AGC1_ON:0 AGC10 1.15 1.45 1.75 Vpp 18 Band Width (-3dB) Fagc12 AGC1IN:sin 0.5Vpp 5MHz dc 2.5V AGC1_HOLD: 1, AGC1_LVL:01, AGC1_ON:0 AGC10 6 - - MHz 19 AGC1 Normal Gain Aagc1 AGC1IN:sin 0.5Vpp 5MHz dc 2.5V AGC1_HOLD: 1, AGC1_LVL:11, AGC1_ON:0 AGC10 20 dB 20 AGC1 Out. DC Vdcagc1 AGC1IN: dc 2.5V AGC1_HOLD: 1, AGC1_LVL:11, AGC1_ON:0 AGC10 2.5 V Vsum1 (A-D)DVD1=0.5MHz, 250mVpp+Vc, DVD Mode GAIN_ABCD:6dB ABCD 1.8 2.0 2.2 Vpp Vsum2 (A-D)DVD1=200kHz, 20mVpp+Vc, CD Mode GAIN_ABCD:30dB Fsum1 (A-D)DVD1=Freq. Sweep,250mVpp+Vc, DVD Mode, GAIN_ABCD:6dB ABCD 500 - - kHz Fsum2 (A-D)DVD1= Freq. Sweep,125mVpp+Vc, CD Mode, GAIN_ABCD:12dB ABCD SUM AMP 21 ABCD SUM AMP voltage gain 22 23 24 8 RF SUM AMP -3dB Gain Bandwidth RF SIGNAL PROCESSOR S5L1462B Electrical Characteristics (Continued) No Item Symbol Input Measuring point Min. RFEQO 1.5 Output Typ. Max. Unit RF EQUALIZER 25 EQ Standard Output Vrfeqdvd EQIN=100kHz, 1Vpp, 26 EQ Peak Frequency Fpeakdvd EQIN= Freq. Sweep, 250mVpp EQF=80H EQG=83H 27 EQ Out DC Veq_dc EQIN=DC 2.5V RFEQ0 EQF=80H EQG=83H 2 2.5 3 28 2.0 2.3 6.4 MHz F1dvd EQIN =0.4MHz, 250mVpp RFEQO EQ_BOOST =0dB -2 0 2 F2dvd EQIN =3.54MHz, 250mVpp EQG_CEN =9dB 4.0 6.0 8.0 30 F3dvd EQIN =6.4MHz, 250mVpp EQ_FREQ =0% 7.0 9.0 11.0 31 F4dvd EQIN=12.8MHz,250mVpp -30 -10 0 2 4 6 29 32 EQ Peak Frequency DVD Gbg1dvd EQIN=Freq. Sweep 250mVpp EQG=80H 33 Gbg2dvd EQIN=Freq. Sweep 250mVpp EQG=81H 4 6 8 34 Gbg3dvd EQIN=Freq. Sweep 250mVpp EQG=82H 6 8 10 35 Gbg4dvd EQIN=Freq. Sweep 250mVpp EQG=83H 9 11 13 36 F1cd RFSUM=0.1MHz, 250mVpp RFEQO EQ_BOOST =0dB -1 0 +1 F1cd RFSUM=0.5MHz, 250mVpp EQG_CEN =9dB 1.5 3.5 5.5 F1cd RFSUM=0.72MHz, 250mVpp EQ_FREQ =0% 7.0 9.0 11.0 F1cd RFSUM=1.4MHz, 250mVpp -30 -10 0 3 4 5 4 6 8 37 Boost Gain Range DVD EQ peak frequency CD 38 39 40 Boost Gain Range cd RFEQO EQF=80H Gbg1cd EQIN=Freq Sweep 250mVpp EQG=80H 41 Gbg2cd EQIN=Freq Sweep 250mVpp EQG=81H 42 Gbg3cd EQIN=Freq Sweep 250mVpp EQG=82H 6 8 10 43 Gbg4cd EQIN=Freq Sweep 250mVpp EQG=83H 9 11 13 RFEQO EQF=80H Vpp V dB dB dB dB 9 S5L1462B RF SIGNAL PROCESSOR ELECTRICAL CHARACTERISTICS (Continued) No Item Symbol Input Measuring point Output Typ. Max. Min. FE 1.8 2.0 FE 2.8 2.9 Unit FOCUS ERROR AMP 44 Vfedvd1 (A,C)DVD1=1kHz Sine, 630mVpp+Vc (B,D)DVD1=1kHz Sine(I) 630mVpp+Vc GAIN_FE=-2dB, DVD Mode Vfedvd2 (A,C)DVD1=1kHz Sine 63mVpp+Vc (B,D)DVD1=1kHz Sine(I) 63mVpp+Vc GAIN_FE=18dB, DVD Mode 46 Vfecd1 (A,C)DVD1=1kHz Sine 200mVpp+Vc (B,D)DVD1=1kHz Sine(I) 200mVpp+Vc GAIN_FE=8dB, CD Mode 47 Vfecd2 (A,C)DVD1=1kHz Sine 40mVpp+Vc (B,D)DVD1=1kHz Sine(I) 40mVpp+Vc GAIN_FE=22dB, CD Mode 45 Voltage Gain 48 Output Voltage H Vfehdvd (B,D)DVD1=Vc+0.7V, (A,C)DVD1=Vc, GAIN_FE=-2dB, DVD 49 Output Voltage L Vfeldvd (B,D)DVD1=Vc-0.7V, (A,C)DVD1=Vc, GAIN_FE=-2dB, DVD 50 Output Voltage H Vfehcd (B,D)DVD1=Vc+0.7V, (A,C)DVD1=Vc, GAIN_FE=0dB, CD 51 Output Voltage L Vfelcd (B,D)DVD1=Vc-0.7V, (A,C)DVD1=Vc, GAIN_FE=0dB, CD 52 Bandwidth Ffedvd (A,C)DVD1=Sine 63mVpp+Vc (B,D)DVD1=Sine(I) 63mVpp+Vc GAIN_FE=18dB, Freq. Sweep, DVD Mode Ffecd (A,C)DVD1=Sine 63mVpp+Vc (B,D)DVD1=Sine(I) 63mVpp+Vc GAIN_FE=18dB,Freq. Sweep , CD Mode Vosfe (A-D)DVD1=Vc, GAIN_FE=18dB,FEOFST=80H ( -3dB Freq.) 53 54 10 Offset Voltage 0.4 FE FE FE 2.8 2.2 Vpp V 0.5 2.9 V 0.4 0.5 25K 35K 45K Hz 25K 35K 45K Hz -300 0 300 mV RF SIGNAL PROCESSOR S5L1462B ELECTRICAL CHARACTERISTICS (Continued) No Item Symbol Input Measuring point Min. Output Typ. Max. Unit TRACKING ERROR AMP (1-BEAM) 55 DPD EQ Standard Gain 56 57 DPD EQ Gain Characteristics Variable range 58 59 Output Voltage Correspond to Phase Difference 60 61 Tracking Balance Adjustment Range 62 63 Phase Comparator Limit 64 Vdpdeq1 (A-D)DVD= 500mVpp 200kHz Sine+Vc, GAIN_TE1 = 0dB Vdpdeq2 (A-D)DVD= 45mVpp 200kHz Sine+Vc, GAIN_TE1 = 27dB Gdpdeqr (A-D)DVD: 251mVpp Freq. Sweep (INT_ONB=1 Sine+Vc, GAIN_TE1 = 12dB FLT_CNT=1) Vph0 (A-D)DVD: 251mVpp 5MHz Sine+Vc (A,C)DVD, (B,D) DVD's phase difference 0° GAIN_TE1 = 12dB Vph1 (A-D)DVD: 251mVpp 5MHz Sine+Vc When (A,C)DVD's phase difference is 45° ahead of (B,D)DVD, GAIN_TE1 = 12dB Vph2 (A-D)DVD: 251mVpp 5MHz Sine+Vc When (A,C)DVD's phase difference is 45° behind (B,D)DVD GAIN_TE1 = 12dB Vbal1 (A,C)DVD=251mVpp 2.616MHz Sine + Vc (B,D)DVD=251mVpp 2.616MHz Sine + Vc TBAL=00H, GAIN_TE1=12dB Vbal2 (A,C) DVD=251mVpp 2.616MHz Sine + vc (B,D) DVD=251mVpp 2.616MHz Sine + vc TBAL=FFH, Gain TE1=12dB Vphlim1 (A,C)DVD=2MHz, 300mVpp, duty 50% Pulse (B,D)DVD signal with a phase 90° late PD_LIMIT=90ns Vphlim2 (B,D)DVD=2MHz, 300mVpp, duty 50% Pulse (A,C)DVD signal with a phase 90° late PD_LIMIT=90ns (A,C)DVD=251mVpp,100kHz (B,D)DVD=251mVpp,2.616MHz Time measurement from Falling Edge with only (B,D)DVD, to when FAULTO becomes H 65 Abnormal Waveform Detection Circuit Tflt 66 Offset Voltage Voste1 (A,.B)DVD. (B.D) DVD =VC Gain_TE1=27dB TEOFST=80H 1.8 2.0 2.2 Vpp 4 8 11 dB 1.2 1.65 2.1 V 0.05 0.65 1.05 V 2.25 2.65 3.25 V DPDEQ1 DPDEQ2 TE (INT_ONB=1 FLT_CNT=1) TE (INT_ONB=1 FLT_CNT=1) 0.33 V 2.97 TE (INT_ONB=1 FLT_CNT=1) 2.55 3.25 0.05 0.75 (B,D)DVD FAULTO 450 900 ns TE (INT_ONB=1 FLT_CNT=1) -300 300 mV 0 V 11 S5L1462B RF SIGNAL PROCESSOR ELECTRICAL CHARACTERISTICS (Continued) No Item Symbol Input Measuring point Output Typ. Max. Min. 1.8 2.0 2.8 2.9 Unit TRACKING ERROR AMP (3-BEARN) 67 TE3 Voltage Gain 68 Vte31 E=1kHz Sine 316mVpp+Vc F=1kHz Sine(I) 316mVpp+Vc TBAL=80, GAIN_TE3=10dB, TEOFST=80H TE Vte32 E=1kHz Sine 30mVpp+Vc, F=1kHz Sine(I) 30mVpp+Vc, TBAL=80, GAIN_TE3=30dB, TEOFST=80H TE 69 Out. Voltage H Vte3h E=Vc-0.7V,F= Vc,GAIN_FE=10dB TE 70 Out. Voltage L Vte3l E=Vc+0.7V,F=Vc,GAIN_FE=10dB TE 71 Bandwidth (-3dB Freq.) Fte3 E=Sine 316mVpp+Vc, Freq. Sweep F=Sine(I) 316mVpp+Vc, Freq. Sweep TBAL=80H, GAIN_TE3=10dB, TEOFST=80H TE 72 Tracking Balance Range Gte31 E=1kHz Sine 316mVpp+Vc F=1kHz Sine(I) 316mVpp+Vc TBAL=00H, GAIN_TE3=18dB, TEOFST=80H TE Gte32 E=1kHz Sine 316mVpp+Vc F=1kHz Sine(I) 316mVpp+Vc TBAL=FFH, GAIN_TE3=18dB, TEOFST=80H E,F=Vc,TBAL=80, GAIN_TE3 =26dB, TE3OFST=80H 73 2.2 Vpp V 0.4 0.5 45K 60K 75K Hz 3 - - dB - - -3 dB TE -300 0 300 mV 74 Offset Voltage Voste3 75 Tracking Offset Range Voste31 E,F=Vc, TBAL=80, Gain=TE3=26dB TEOFST=00H TE 0 0.5 V Voste32 E,F=Vc, TBAL=80, Gain=TE3=26dB TEOFST=FFH TE 0.3 3.3 V 76 12 RF SIGNAL PROCESSOR S5L1462B ELECTRICAL CHARACTERISTICS (Continued) No Item MIRROR CIRCUIT 77 Output Voltage H 78 Output Voltage L 79 Mirr Hold Frequency 80 81 RFRP Output Level 1 82 83 86 Vmirh Vmirl Fhold1 (DVD) Fhold2 (CD) Vrfrp1 (DVD) Vrfrp2 (CD) RFRP Output Level 2 84 85 Symbol Vrfrp3 (DVD) Vrfrp4 (CD) RFRP Output Variable Range Avorfrp1 Avorfrp2 Input MIRRI=1Vpp 1kHz sine 30% AM fc = 5MHz dc=2.5V RFRPOFST=30 RFRP_FRQ=30kHz Gain_RFRP=14dB Measure the Freq. of No 65 Mirri=1Vpp 1kHz sine 30% AM fc=5MHz dc=2.5V, RFRPOFST=30 RFRP_FRQ=320kHz Gain_RFRP=14dB Mirri=1Vpp 1kHz sine 30% AM fc=5MHz dc=2.5V RFRP_OFST=30 RFRP_FRQ=30kHz Gain_RFRP=12dB Mirri=1Vpp 1kHz sine 30% AM fc=500kHz dc=2.5V RFRP_OFST=30 RFRP_FRQ=30kHz Gain_RFRP=12dB Mirri=1Vpp 20kHz sine 30% AM fc=5MHz dc=2.5V RFRP_OFST=30 RFRP_FRQ=30kHz Gain_RFRP=12dB Mirri=1Vpp 300kHz sine 30% AM fc=5MHz dc=2.5V RFRP_OFST=30 RFRP_FRQ=320kHz Gain_RFRP=12dB Mirri=1Vpp 1kHz sine 30% AM fc=5MHz dc=2.5V RFRP_OFST=30 RFRP_FRQ=30kHz Gain_RFRP=12dB Mirri=1Vpp 1kHz sine 30% AM fc=500kHz dc=2.5V RFRP_OFST=30 RFRP_FRQ=320kHz Gain_RFRP=14dB Measuring point Min. Output Typ. Max. MIRR 4.5 - - - - 0.4 990 1000 1010 Hz 99 100 101 kHz RFRP 1.0 1.15 1.30 Vpp RFRP 700 850 1000 mVpp 300 450 600 4.5 6 7.5 6.5 8 9.5 MIRR RFRP Unit V dB 13 S5L1462B RF SIGNAL PROCESSOR ELECTRICAL CHARACTERISTICS (Continued) No Item MIRROR CIRCUIT 87 RFRP Bandwidth (-3dB) 88 14 Symbol Frfrp1 Frfrp2 Input Mirri=1Vpp 60kHz sine 30% AM fc=5MHz dc=2.5V RFRP_OFST=30 RFRP_FRQ=30kHz Gain_RFRP=12dB Mirri=1Vpp 120kHz sine 30% AM fc=5MHz dc=2.5V RFRP_OFST=30 RFRP_FRQ=30kHz Gain_RFRP=12dB Measuring point RFRP Min. Output Typ. 60 120 Unit Max. kHz RF SIGNAL PROCESSOR S5L1462B ELECTRICAL CHARACTERISTICS (Continued) No Item Symbol Input Measuring point Min. Output Typ. Max. Unit DEFECT DETECT CIRCUIT 89 Output Voltage H Vdefh (A-D)DVD1=1kHz 250mVpp+Vc Gain_ABCD=0dB ABCDOFST=80 90 Output Voltage L Vdefl (A-D)DVD1=1kHz 250mVpp+Vc Gain_ABCD=0dB ABCDOFST=80 91 Min Operation Frequency Fdef1 (A-D)DVD1=1kHz 250mVpp+Vc Gain_ABCD=0dB ABCDOFST=80 DFCT DFTP_TH 92 Max Operation Frequency Fdef2 (A-D)DVD1=5kHz 250mVpp+Vc Gain_ABCD=0dB ABCDOFST=80 =300mV DFT_TH 93 Minimum Input Operation Voltage Vdefin1 (A-D)DVD1=5kHz 150mVpp+Vc Gain_ABCD=0dB ABCDOFST=80 =100mV 94 Maximum Input Operation Voltage Vdefin2 (A-D)DVD1=5kHz 600mVpp+Vc Gain_ABCD=0dB ABCDOFST=80 95 High Speed Peak Hold Time Constant Range Tphr1 (A-D)DVD1: 250mVpp+Vc Square 5kHz Gain_ABCD=0dB DFCT_CNST=5.6us/V 5.7 Tphr2 (A-D)DVD1: 250mVpp+Vc Square 5kHz Gain_ABCD=0dB DFCT_CNST=60us/V 60 96 4.5 V 0.4 1.0 kHz 0.5 Vpp 5.0 1.8 us/V FOK DETECT CIRCUIT 97 Output Voltage H Vfokh (A-D)DVD1=250mVpp 1kHz Sine 98 Output Voltage L Vfokl wave, GAIN_ABCD=0dB FOK_TH=80 99 Maximum Operation Frequency Ffok (A-D)DVD1=250mVpp 45kHz GAIN_ABCD=0dB, FOK_TH=80 Venv FOKB 4.5 V 0.4 FOKB 45K ABCDI : 2Vpp,Sine 1MHz ENV 1.66 4.5 Hz RF ENVELOPE AMP 100 Output Voltage 1.86 2.06 V ALPC CIRCUIT 101 Output Voltage H Valpch1 PDdvd: +600V LDONB=1 (LDO) dvd 102 Output Voltage L Valpcl1 PDdvd: +0V LDONB=1 (LDO) dvd 103 Output Voltage H Valpch2 PDcd: +600mV LDONB=1 (LDO) cd 104 Output Voltage L Valpcl3 PDcd: +0mV LDONB=1 (LDO) cd 105 Input PD Voltage Vinpd PDdvd: DC Sweep LDONB=1 PD Value When LDdvd: 3.5V LDO dvd V 0.5 4.5 V 0.5 158 178 198 mV 15 S5L1462B RF SIGNAL PROCESSOR ELECTRICAL CHARACTERISTICS (Continued) No Item Symbol Input Measuring Output point Min. INTERO 4.5 Typ. Unit Max. INTERRUPT DETECT CIRCUIT 106 Output Voltage1 H Vinth1 INTERI=1Vpp 1kHz INTER_TH=80 Gain_INT=3.5dB INT_SEL=1, 107 Output Voltage1 L Vintl1 INT_ONB=0 108 Output Voltage2 H Vinth2 (A-D)DVD1=1kHz, 250mVpp+Vc, DVD mode Gain_ABCD:6dB INTER_TH=80 109 Output Voltage2 L Vintl2 Gain_INT=3.5dB, INT_SEL=0, INT_ONB=0 110 Minimum Operation Frequency 1 Fint11 INTERI=1Vpp, 1kHz INTER_TH=80 Gain_INT=3.5dB INT_SEL=1, INT_ONB=0 111 Maximum Operation Frequency 1 Fint21 INTERI=1Vpp, 5kHz INTER_TH=80 Gain_INT=3.5dB INT_SEL=1, INT_ONB=0 112 Minimum Operation Frequency 2 Fint12 (A-D)DVD1=1kHz, 250mVpp+Vc, DVD mode INTER_TH=80, Gain_INT=3.5dB INT_SEL=0, INT_ONB=0 113 Maximum Operation Frequency 2 Fint22 (A-D)DVD1=5kHz, 250mVpp+Vc, DVD mode INTER_TH=80, Gain_INT=3.5dB INT_SEL=0, INT_ONB=0 114 Minimum Input Operation Frequency Vintin1 INTERI=0.5Vpp, 5kHz Pulse Symmrtry=90%, INTER_TH=80 Gain_INT=9.5dB, INT_SEL=1, INT_ONB=0 115 Maximum Input Operation Frequency Vintin2 INTERI=1.8Vpp, 5kHz Pulse Symmrtry=90%, INTER_TH=80 Gain_INT=3.5dB, INT_SEL=1, INT_ONB=0 0.4 INTERO 4.5 INTERO 1.0 kHz 1.0 kHz 0.5 Vpp 5.0 INTERO 5.0 INTERO 1.8 Frequency = Fin1,DUTY=25% 16 V 0.4 INPUT1 300mVpp INPUT2 300mVpp Frequency = Fin1*2,DUTY=50% V RF SIGNAL PROCESSOR S5L1462B SERIAL INTERFACE • • The serial interface controls the disc type, speed, AGC, and the on/off of the laser diode. The serial interface's timing diagram is as follows. STB DATA Address, 8-bit Data, 8-bit CLOCK A7 A0 D7 D0 Serial Port Data Transfer Format • CLOCK : Clock synchronous to the data transmitted from MICOM. DATA : Address and data transmitted from MICOM. STB : Signal showing that data is enabled. Address : 00H DATA Function Initial Value D7 D6 D5 D4 D3 D2 AGC_HOLD TE_SEL RFSUM_SEL BUF_SEL LDONB AGC_HOLD 0 0 0 0 0 0 D1 D0 SPEED_SEL 0 0 AGC1_HOLD(D7): RF AGC Peaking protection selection 0: unuse 1: use TE_SEL(D6): TRACKING ERROR selection 0: DPD 1: TE3 RFSUM_SEL(D5): RFSUM PORT selection 0: RFSUM input 1: (A, B, C, D) input BUF_SEL(D4): Input buffer selection (RFSUM port polarity selection) 0: Buffer Bypass 1: Buffer use LDONB(D3): LASER,ON/OFF control pin 0:LASER OFF 1:LASER ON AGC1_HOLD: AGC1 peaking protection selection 0: unuse 1: use SPEED_SEL (D1 - D0) : speed selection D1 0 1 1 D0 0 0 1 MODE DVD CD CD SPEED_SEL 1X 1X 2X 17 S5L1462B • RF SIGNAL PROCESSOR Address 01H : TRACKING BALANCE Adjustment DATA D7 D6 D5 D4 Function • • 1 0 D0 0 0 0 0 0 0 TBAL F GAIN 00 +4dB 80 0dB FF -4dB DPD TE: The change in the TE output voltage following the change in the TBAL value. TBAL TE Output Voltage 00 80 FF -1.2V 0V +1.2V Address 02H : GAIN_RFSUM, GAIN_TE3 GAIN selection D7 D6 Function D5 D4 D3 D2 GAIN_RFSUM Initial Value 18 D1 3 BEAM TE: F's relative change in gain compared to E, following the value change of TBAL. DATA • D2 TBAL Initial Value • D3 0 0 0 D1 D0 GAIN_TE3 1 0 0 1 0 GAIN_RFSUM (D4 - D7) : RF SUM input pin GAIN selection D7 D6 D5 D4 MODE (Value of RFAGCO compared to the input voltage) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -6dB -4dB -2dB 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB 16dB - RF SIGNAL PROCESSOR • S5L1462B GAIN_TE3 (D0 - D3) : TE3 GAIN selection D3 D2 D1 D0 GAIN 0 0 0 0 6dB 0 0 0 1 8dB 0 0 1 0 10dB 0 0 1 1 12dB 0 1 0 0 14dB 0 1 0 1 16dB 0 1 1 0 18dB 0 1 1 1 20dB 1 0 0 0 - 1 0 0 1 - 1 0 1 0 - 1 0 1 1 - 1 1 0 0 - 1 1 0 1 - 1 1 1 0 - 1 1 1 1 - 19 S5L1462B • RF SIGNAL PROCESSOR Address 03H : GAIN_FE, GAIN_ABCD GAIN selection DATA D7 Function D4 D3 D2 0 0 1 D1 D6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D0 GAIN_FE 0 0 0 GAIN_ABCD (D4 - D7) : ABCD GAIN selection D7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 20 D5 GAIN_ABCD Initial Value • D6 GAIN 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB 16dB 18dB 20dB 22dB 24dB 26dB 28dB 30dB 1 1 RF SIGNAL PROCESSOR • GAIN_FE (D0 - D3) : FE GAIN selection D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 • S5L1462B D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 GAIN -2dB 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB 16dB 18dB 20dB 22dB 24dB 26dB 28dB Address 04H - 06H : Various offset adjustment data ADDRESS Data Initial Value 04H TE(1,3) Offset 80H 05H FE Offset 80H 06H ABCD Sum Offset 80H The output OFFSET is at its minimum at 00H, maximum at FFH, and 2.5 V at 80H. 21 S5L1462B • RF SIGNAL PROCESSOR Address 07H: DPD PD LIMIT GAIN_TE1 HOLD_CTL selection DATA D7 Function DPD_MUTE Initial Value 0 D6 D5 D4 D3 D2 GAIN_TE1 0 1 D1 D0 0 0 PD_LIMIT 0 0 0 DPD_MUTE (D7): DPD TE input pin GAIN selection 0: DPD MUTE OFF 1: DPD MUTE ON GAIN_TE1 (D4 - D6): DPD TE input pin GAIN selection D6 D5 D4 MODE (Relative value of DPDEQ1, 2 compared to the voltage) 0 0 0 6dB 0 0 1 9dB 0 1 0 12dB 0 1 1 15dB 1 0 0 18dB 1 0 1 21dB 1 1 0 24dB 1 1 1 27dB PDLIMIT (D0 - D3): DPD PHASE DETECTOR's limit of output width D3 D2 D1 D0 Limit of Width 0 0 0 0 160ns ≈ 1 22 1 ≈ 1 1 10ns RF SIGNAL PROCESSOR • S5L1462B Address 08H: Offset Adjustment ADDRESS Data Initial Value 08H RFRP Offset 80H The output OFFSET is at its minimum at 00H, maximum at FFH, and 2.5V at 80H. • Address 0AH: DATA D7 D6 D5 D4 Function Initial Value D3 D2 D1 D0 0 0 0 EQ_FREQ 1 0 0 0 0 EQ_FREQ (D0 - D7): EQ frequency characteristic's minute adjustment selection EQ_FREQ Amount of PEAK frequency change 22 +60% ≈ ≈ 80 0% ≈ ≈ DB -60% 23 S5L1462B • RF SIGNAL PROCESSOR Address 0BH : DATA Function D7 Initial Value 1 D6 D5 D4 D3 EQ_BOOST 0 D2 D1 EQG_CEN ga-Mux-TE 0 0 0 D0 0 1 0 EQ_BOOST(D4 – D7) : GAIN minute adjustment selection from the EQ_BOOST GAIN chosen by EQG_CEN D7 D6 D5 D4 CENTER GAIN change in width 0 0 1 0 -4dB - - 0 1 1 1 -0.5dB 1 0 0 0 0dB 1 0 0 1 +0.5dB 1 1 0 0 4dB ga-Mux-TE(D2 - D3) : TE output gain control D3 D2 0 0 0 1 1 0 1 1 CENTER_BOOST GAIN 10dB 12dB 14dB 16dB EQG_CEN(D0 - D1) : EQ_BOOST GAIN's CENTER GAIN minute adjustment selection D1 D0 CENTER_BOOST GAIN 0 0 3dB 0 1 5dB 1 0 7dB 1 1 9dB • Address 0CH : DATA Function D7 Initial Value 0 D6 RFRP_FRQ D5 D4 D3 GAIN_RFRP 0 0 0 D2 RFRP-LPF 0 0 D1 D0 SW-CON SW_CON1 0 0 RFRP_FRQ (D6 - D7) : RFRP's PEAK-BOTTOM HOLD circuit output frequency, LPF frequency selection D7 0 0 1 1 24 D6 0 1 0 1 RFRP FREQ. 30 kHz 80 kHz 160 kHz 320 kHz RFRP LPF fc 60 kHz 160 kHz 320 kHz 640 kHz RF SIGNAL PROCESSOR S5L1462B GAIN_RFRP (D4 - D5) : RFRP's output GAIN selection D5 D4 GAIN_RFRP 0 0 6dB 0 1 9.5dB 1 0 12dB 1 1 14dB RFRP_LPF (D3 - D2): RFRP's output gain selection D3 D2 RFRP_LPF 0 0 60kHz 0 1 80kHz 1 0 100kHz 1 1 120kHz SW_CON (D1): Defect signal selection when RF AGC/AGC1 peaking protection selection 0: Un use 1: use SW_CON1 (D0): Cpeak signal selection when RF AGC/AGC1 peaking protection selection 0: unuse 1: use • Address 0DH DATA Function D7 Initial Value 0 D6 D5 AGC_LVL D4 D3 D2 DFTP_TH 1 0 0 D1 D0 DFT_TH 0 0 0 0 AGC_LVL(D6 - D7) : RFAGC LEVEL selection D7 D6 AGC LEVEL Output Vpp 0 0 3.25V 0.50Vpp 0 1 3.5V 0.75Vpp 1 0 3.75V 1.00Vpp 1 1 4.0V 1.25Vpp DFTP_TH(D3 - D5) : PLL DEFECT SLICE LEVEL selection D5 D4 D3 SLICE LEVEL 0 0 0 300mV 0 0 1 400mV 0 1 0 500mV 0 1 1 600mV 1 0 0 700mV 1 0 1 800mV 1 1 0 900mV 25 S5L1462B RF SIGNAL PROCESSOR 1 26 1 1 1000mV RF SIGNAL PROCESSOR S5L1462B DFT_TH(D0 - D2) : DEFECT SLICE LEVEL selection • D2 D1 D0 SLICE LEVEL 0 0 0 100mV 0 0 1 200mV 0 1 0 300mV 0 1 1 400mV 1 0 0 500mV 1 0 1 600mV 1 1 0 700mV 1 1 1 800mV Address 0EH: Interrupt Threshold Level selection DATA Function D7 Initial Value 1 D6 D5 D4 D3 D2 D1 D0 INTER_TH 0 0 0 0 0 0 0 D4 D3 D2 D1 D0 0 0 0 0 Interrupt Level selection by the 8-Bit DAC • Address 0FH :FOK Threshold LEVEL selection DATA Function D7 Initial Value 1 D6 D5 FOK_TH 0 0 0 FOKB Level selection by the 8-Bit DAC 27 S5L1462B • RF SIGNAL PROCESSOR Address 10H DATA Function D7 D6 INT_ONB FLT_CTL Initial Value 0 0 D5 D4 DFCT_CNST 0 D3 D2 LD_SEL INT_SEL 0 0 0 D1 D0 AGC1_LVL 0 0 AGC1_LVL(D0 - D1) : AGC1 output LEVEL adjustment selection D1 D0 AGC1_LVL Output LEVEL 0 0 2.9V 0.7V 0 1 3.0V 1.0V 1 0 3.1V 1.4V 1 1 - - INT_SEL (D2): Interruption input selection 0: Internal input 1: External input LD_SEL(D3) : LD output selection 0 : Select LDDVD 1 : Select LDCD DFCT_CNST(D4 - D5) : PEAK HOLD time constant selection for deciding the DEFECT circuit's DEFECT minimum detection width D5 D4 DEFECT 0 0 60us/V 0 1 25us/V 1 0 12.5us/V 1 1 5.6us/V FLT_CTL(D6) : Fault out output selection. 0: Fault out output ON 1: Fault out output OFF INT_ONB(D7) : Interruption on/off selection. 0 : Interrupt Detect ON 1 : Interrupt Detect OFF 28 RF SIGNAL PROCESSOR • S5L1462B Address 11H DATA Function D7 D6 D5 D4 D3 D2 RVSN Vdc25_sel VBGO_ SEL DVCTL_ SEL Vdc125_ sel AGC1_ON Initial Value 0 0 0 0 0 0 D1 D0 GAIN_INT 0 0 GAIN_INT(D0 - D1) : Interruption GAIN adjustment selection D1 D0 GAIN Drainage 0 0 3.5dB X1.5 0 1 6dB X2 1 0 9.5dB X3 1 1 12dB X4 AGC1_ON (D2) : AGC1 BLOCK ON/OFF adjustment selection 0 : AGC1 ON 1 : AGC1 OFF Vdc125_sel (D3): 1.25V reference voltage selection 0: Bandgap voltage use 1: Reference voltage use DVCTL_SEL (D4): TE1 input selection 0: (A+B), (B+D) 1: (A+D), (C+D) VBGO_SEL (D5): ALPC reference voltage input selection 0: Internal bandgap reference voltage 1: External voltage vdc25_sel (D6): 2.5V reference voltage selection 0: Bandgap voltage 1: Reference voltage 29 S5L1462B RF SIGNAL PROCESSOR BLOCK DESCRIPTION RF MULTIPLEXER BUF_SEL RFSUM_SEL RFSUM RFP1 ADVD BDVD RFP2 CDVD RFP3 DDVD RFP4 VREFO RF MUX • The RF Multiplexer is a block that inputs into the RF SUM AMP the I/V signals which are output differently according to each pickup, in order to get the RF AUM signal. The RFSUM generates RF signals by compensating according to the I/V polarity using the ADDRESS 00H's BUF_SEL. The RF MUX's operation is selected by ADDRESS 00H's RFSUM_SEL REGISTER, and the RF MUX output value for each RFSUM_SEL are as follows. → RFSUM_SEL (D3): Inputs and selects RFSUUM AMP's operation mode by Address 00H's (D5). (ABCD MUX & RFSUM) 30 D3 RFP1 RFP2 RFP3 RFP4 0 RFSUM VREFO VREFO VREFO 1 ADVD BDVD CDVD DDVD RF SIGNAL PROCESSOR S5L1462B RF SUM & AGC AMP BLOCK GAIN_RFSUM RFP1 RFP2 RFP3 RFP4 + + RF SUM + AGC AMP + RFAGCO EQIN - + VCC AGCB AGCC SW - BOTTOM + PEAK COMP + AGCP Control on/off AGC_LVL GND GND • The RF SUM AMP either adds or subtracts the input signal selected in the RF Multiplexer by the RFSUM_SEL and compensates according to the I/V polarity using ADDRESS 00H's BUF_SEL, to produce the RF signal. Also, the RF SUM AMP is able to adjust the LEVEL by the gain selected by GAIN_RFSUM (-6 – -16dB). • The RF AGC circuit makes the signal whose gain was adjusted by the RFSUM AMP into a regular size. The AGC circuit's output size is selected according to the value of AGC_LVL (3.2V – 3.75V), between 0.5Vpp -1.25Vpp in increments of 0.25Vpp STEP. The AGC's response time constant is decided by the resistance capacity of the Capacitor connected to the external connection PIN (AGCP, AGCB, AGCC). • SW is prohibited the peaking by hold the AGC voltage when meet the defect or interruption 31 S5L1462B RF SIGNAL PROCESSOR RF EQUALIZER RFEQ_SEL EQ_FREQ EQ_BOOST EQG_CEN RF Equalizer H(s)=K(S2 -A2) EQIN RFEQO Order 9 Bessel LPF Symmetric Zero HPF PLLGF from D.R EQCTL • The RF Equalizer receives the RF AGC AMP's output signal and corrects the gain and frequency characteristics according to disc type and speed. Our RF is used in common with the RF EQ that has similar frequency characteristics. The RF EQ has 3 independent EQ characteristics, namely that of DVD 1X, CD 1X, and CD 2X. • The RF Equalizer is composed of the SYMMETRIC ZERO HPF and the 9th degree BESSEL LPF. The SYMMETRIC ZERO HPF's transmission function is: H(s) = K(S 2-A 2), and is combined with BESSEL LPF to make RF EQ characteristics. • The RF EQ has predetermined frequency characteristics according to disc type and speed mode. The minute adjustments of frequency and BOOST gain are carried out by Add 0CH's EQ_FREQ and Add 0BH's EQ_BOOST and EQG_CEN. The gain adjustment of the Peaking frequency is carried out by the combination of GAIN (3-9dB, 2dB/STEP) selected by EQG_CEN, and GAIN (-4.0-+4.0dB, 0.5dB/STEP) selected by EQ_BOOST. The selection of the Peaking frequency is made by the EQ_FREQ. • Of the RF EQ characteristics from SPEED_SEL selection, the characteristics when EQ_FREQ=0%, EQG_CEN=5dB, and EQ_BOOST=+1dB have been shown below. 32 RF SIGNAL PROCESSOR S5L1462B Gain GPEAK EQ Range F PEAK Frequency Characteristics of RF EQ EQ_FREQ=0%, EQG_CEN=7dB, EQ_BOOST=0dB SPPED_SEL RF EQ FPEAK GPEAK 00 RF EQ1 6.4MHz +7dB 10 RF EQ2 1.3MHz +7dB 11 RF EQ3 2.6MHz +7dB The RF EQ's PEAK frequency is the same as shown in the above RF EQ characteristics. It is therefore able to adjust to the optimal EQ characteristics demanded by the SYSTEM by EQ_FREQ's minute tuning. 33 S5L1462B RF SIGNAL PROCESSOR DPD TRACKING ERROR AMP DPDEQ1 SPEED_SEL DPD_MUTE PLLCTL INTERO PD_LIMIT GAIN_TE1 ADVD BDVD CDVD DDVD TE1 Front Mux + GCA + + GCA + PDMIMITRES TBAL EQ comp VCPS EQ comp Phase Detecter Abnormal Waveform Detection Circuit FLT_CTL HOLD_CTL DPD TE BLOCK LPF DPDTE to MUX5 TE1OFST FAULTO DPDEQ2 TE1RES GND • The (A-D)DVD signal's gain is adjusted in the DPD input GAIN adjustment block by the gain selected by Address 07H's GAIN_TE1 register. The signal is then compensated in the DPD EQUALIZER and input into the COMPARATOR. • The signal by passing through the COMPARATOR circuit is then adjusted for tracking balance by the VCPS (Voltage Controlled Phase Shift) circuit, whose Delay Time is adjusted by Address 01H's register TBAL. • The signal, after passing through the VCPS circuit, detects the phase difference between two signals through the phase detector. The maximum width of the phase detector's output is limited by the output width limit set by Add 07H's PD_LIMIT register. • The abnormal waveform detection circuit compensates for a small or unstable input signal. It executes mute when an abnormal waveform is detected, and turns the detection/compensation On or Off. The following are qualified as abnormal waveforms: When the A+C COMPARATOR output is maintained for longer than 16T. When the - B+D COMPARATOR output is maintained for longer than 16T When the output of the abnormal waveform detection circuit goes "H". When the output of the abnormal waveform detection circuit goes 'H', then goes back to "L" at the next RISING or FALLING EDGE. • The output of the phase detector is output through the low pass filter. It is input into the MUX5 then output to the TE block. • The DPD TE OFFSET is a function to correct the circuit OFFSET after phase comparison. It eliminates any OFFSET existing within the LPF block. • The DPD MUTE mutes the DPD TE while correcting the DPD Offset. Mute is carried out when Add 07H's DPD_MUTE register is "H", the external DPDMUTE block's input voltage is "H", and the INTERRUPT output is "H". • When TE_SEL is not in DPD MODE, the DPD BLOCK's power is turned off. 34 RF SIGNAL PROCESSOR S5L1462B 3B TE AMP AND TE OUTPUT SELECTION + E F - GCA TBAL GAIN_TE3 TEOFST TE3B TEDPD TE_SEL M U X ga_Mux_TE LPF 10dB 16dB TE • Tracking Balance is carried out in the following manner. The GAIN of the F signaling AMP is adjusted by the T_BAL (Tracking Balance) so that the AC level of the E, F signal input becomes the same. • After the BALANCE has been adjusted, the E,F signal is operated on in the 3-Beam Tracking Error Amp by TE = k (E-F). Then the GAIN is compensated by Address 02H's GAIN_TE3 from 6dB - 20dB to compensate for the difference in disc reflectivity according to disc type. The OFFSET is compensated by TE0FST, and the signal is output as a TE3B signal. • The TE3B signal is output when the TE_SEL selects either the DPD TE or the 3B TE output. • The MUX TE output signal is output through the LPF (fc=20.4kHz) and the 10dB Amp. • The Servo Control voltage output is compatible with the 3.3V Supply. FOCUS ERROR AMP A C B GAIN_FE FEOFST INV AMP LPF INV AMP FE + D VC • The (A+C), (B+D) input signal is operated on in the FOCUS Error Amp by FE = -k((A+C)-(B+D)). The gain is compensated by Address 03H's FE_GAIN from -2dB - +28dB to account for the difference in disc reflectivity according to disc type. When the OFFSET is adjusted by FEOFST, the signal is output as an FE signal after passing through the LPF (fc=34.7kHz) and the Inversion AMP. • The output is a Servo Control voltage and is compatible with the 3.3V Supply. 35 S5L1462B RF SIGNAL PROCESSOR ABCD SUM AMP A GAIN_ABCD C - B INV AMP D 15dB ABCD + ABCD_OFST • The input signals A, B, C, D are operated as ABCD = A+B+C+D in the ABCD SUM Amp. The gain is compensated by Address 03H's GAIN_ABCD from 0dB - +30dB to account for the difference in disc reflectivity according to disc type. The OFFSET is adjusted by the BACDOFST, then the signal is output as ABCD. • The frequency characteristics of the output AMP are fc = 4MHz when in CD 2x mode, and fc=10MHz in DVD mode. FOK DETECT CIRCUIT ABCD - ABCDI + COMP FOK_TH FOKB + • This circuit generates the FOCUS OK signal for the SERVO. It consists of a circuit that detects the PEAK of the ABCD SUM signal, and the circuit that outputs the FOKB signal. • It compares and outputs the ABCD SUM signal's output signal and the comparison LEVEL(FOK_TH). 36 RF SIGNAL PROCESSOR S5L1462B MIRROR CIRCUIT VCC RFRP_FRQ CB1 RFCT BOTTOM - PEAK + MIRRI GCA LPF PEAK CP2 + COMP MIRR - CP1 GAIN_RFRP RFRP_OFST GND GND RFRP • The RFRP circuit is a block that detects signals crossing the TRACK. • The circuit receives AC-COUPLED RFAGCO signals and calculates the difference between two signals through the PEAK HOLD and BOTTOM HOLD. The response time constant of the PEAK HOLD and BOTTOM HOLD is set by Add 0CH's RFRP_FRQ, and the standard CAPACITOR value is set by the CP1 block and CAPACITOR connected to the CB1 block. (Standard value: 100pF) • The AMP that produces the RFRP signal by calculating the PEAK HOLD output and the BOTTOM HOLD output receives the RFRP_OFST, and corrects the difference in DC value in the PEAK HOLD output and BOTTOM HOLD output to guarantee a DYNAMIC RANGE and adjust the gain by GAIN_RFRP from 0dB-12dB. • The RFRP signal is output through the R, C 1st LPF, and the LPF's BW is decided by Address 0CH's RFRP_FRQ value. • The CENTER voltage of the two signals that passed through the PEAK HOLD and BOTTOM HOLD is output to the RFCT block. The response time constant of the PEAK HOLD and BOTTOM HOLD is decided by the CAPACITOR value and resistance connected to CP2 and CB2. • The MIRR signal is found by comparing the RFCT and RFRP signal, and the polarity is HIGH in the MIRROR while LOW in the PIT. Also, the amount of HYSTERISIS can be adjusted by inserting resistance between the RFCT and MIRR. 37 S5L1462B RF SIGNAL PROCESSOR RF ENVELOPE CIRCUIT VCC ENVB BOTTOM ABCDI PEAK 3.5dB + LEVEL SHIFT ENV ENVP GND • This circuit detects the RF ENVELOPE RF signal's ENVELOPE. It has the ENVELOPE detection output for adjusting the SERVO's FOCUS BIAS. • The PEAK HOLD and BOTTOM HOLD's response time constant is decided by the CAPACITOR value connected to the external block ENVP, ENVB, and the standard response frequency is 10 kHz (when C = 0.01uF). • The LEVEL SHIFT circuit is to make sure ENVOUT starts near 0Volts instead of at Vc LEVEL when there is no RF signal. • During Focus Un-locking, the circuit outputs to the ENV output block after 3.5dB GAIN UP. • The ENV signal is output to the ENV output block during Focus Un-locking after 3.5dB GAIN UP. 38 RF SIGNAL PROCESSOR S5L1462B DEFECT DETECT CIRCUIT GND RFRP_FRQ CC1 PEAK DFCT ABCD CC2 COMP DFCT_CP2 GND DFTP _TH PEAK LONG DFCT1 + INTERO DFT _TH COMP DFCT2 PLLDFT + DFCT_CP1 GND • The DEFECT circuit detects the signal defects from damage to the reflective surface. The defects are detected in ABCD through high speed PEAK HOLD and low speed PEAK HOLD. DC is added to the high speed PEAK HOLD output, then compared with the low speed PEAK HOLD output. • The high speed PEAK HOLD's response time constant is set to Add 0CH's RFRP_FRQ when a DEFECT is detected. The low speed PEAK HOLD time constant is set by the CAPACITOR connected to the RFRP_FRQ and CB_DFT block. The rate of change is same for high and low speed PEAK HOLD. • The DEFECT detecting level for SERVO is set by Add 0DH's DFT_TH, and the DEFECT detecting level for PLL is set by DFTP_TH. The output of the SERVO's DEFECT is ORING with the INTERRUPT output. INTERRUPT DEFECT CIRCUIT - INTERI + VREFA INTER_ TH COMP INTERO + GAIN_INT GND INT_ONB VREFA • The Interrupt DEFECT circuit detects signal defects from insulation layer damage during CD/DVD Mode operation. The ABCDSUM output passes through the external LPF, is amplified by the AMP, then comparatively output with the Comparator's standard voltage (INTER_TH). The AMP's GAIN is adjusted by the GAIN_INT, and this interrupt signal's use is determined by INT_ONB. 39 S5L1462B RF SIGNAL PROCESSOR ALPC CIRCUIT VCC PDDVD - + 20k LD_SEL VCC MUX + LDODVD - PICK-UP + VBGO + 3.5k GND GND LD_SEL + PDCD 20k VCC VCC LDOCD + MUX PICK-UP 3.5k GND + GND • This circuit is for controlling the Laser Diode's amount of light. It sets the amount of light that is output during playback, and stabilizes it by detecting the fluctuation in Laser Power for voltage or temperature change using the Monitor Photo Diode's output current change. • ALPC for CD and DVD are separate. ALPC circuit selection and On/Off are controlled by Add 00H's LDONB. The unselected ALPC maintains Off status. • The ALPC reacts to the P-SUB LASER DIODE. Its standard voltage can be changed by the value of the external ZENER DIODE connected to the VREFLP_BGI block. • PD's standard input voltage range is 100mV -- 0.5V. 40 RF SIGNAL PROCESSOR S5L1462B TEST CIRCUIT DPDVCC INTERI PLLDFT DFCT1 INTERO BNC MIRR DPDEQ1 DPDEQ2 PLLCTL VREFDPD RESET STB CLOCK DATA RFCT Cpeak RFRP FAULTOUT Electrolytic DPDGND C100 R11 C15 BNC R7 R6 R13 R14 R12 : 100k R13 : 100k R14 : 5k R15 : 20K 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 C1 C2 C3 C4 C5 C1: 224 C2 - C5: 0.1u ABCD R1: 12K SW1 R2: 12K R3: 12K BNC BNC BNC RFSUM A B R1 R2 R3 Electrolytic VREFA Electrolytic E F C12 : 100n (104) C13 : 50n C14 : 50n C15 : 0.1u R6 : 12K R7 : 12K R8 : 27K R9 : 33K R10 : 100K R11 : 100K C16 : 100p R12 : 1K C100: 104 40 39 C11 38 37 C10 C9 36 35 34 33 32 C8 31 C7 30 29 28 27 26 25 C6_1 VFEFPL_ BGI LD PD FE C22 LDODVD PDDVD LDOCD PDCD AGND FE VZOCTL PLLGF C17 : 0.01u C18 : 0.1u C19 : 0.47u C20 : 0.01u C21 : 0.01u C22 : 0.01u EQVGND EQVCC Electrolytic R12 VREFLP_BGI C21 R15 BNC C20 DVCC CC2 CC1 DFCT_CP DFCT_CP1 FOKB DGND ENV ENVB ENVP ABCDI ABCD VREFA1 AVCC1 TE CE S5L1462B BNC C19 MIRRI EQVCC AGC1O AGC1C AGC1IN RFEQO EQIN RFAGCO AGCC EQGND AGCBO AGCB AGCP RDPF VZOCTL PLLGF ADVD BDVD CDVD DDVD RREFBF RREFEQ RREF VREFEQ ADVD1 BDVD1 CDVD1 DDVD1 AVCC VREFA E F C17 SW4 SW5 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 DFCT1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PLLDFT AGC1IN BNC EQIN CP1 CB1 RFRP CP2 CB2 RFCT RESET STB CLOCK DATA PDLIMITRES VREFDPD DPDGND TE1RES PLLCTL FAULTOUT DPDEQ2 DPDEQ1 MIRR DPDVCC INTERO INTERI RFAGCO AGCC AGCBO SW3 C12 R8 C16 MIRRI RFSUM AGC1C AGC1O RFEQO BNC R100 R9 C14 DVCC Electrolytic DGND DFCT_CP DFCT_CP1 FOKB R4 SW2 ENV BNC ABCDI ABCD VREFA1 TE C6_1:102 C6 :103 C7 :473 C8 :473 C9 :224 C10 :100p C11 :224 R4 :100k R5 :100k AGND Electrolytic Cap AVCC 41 S5L1462B RF SIGNAL PROCESSOR PACKAGE DIMENSION 23.90 + 0.30 0-8 20.00 + 0.10 14.00 0.80 #80 + 0.20 0.10 MAX (1.00) 17.90 + 0.30 0.15 - 0.05 #1 0.80 0.35 + 0.10 0.05 MIN 0.15 MAX (0.80) 2.65 + 0.10 3.00 MAX 0.80 + 0.20 NOTE: Dimensions are in millimeters. 42 RF SIGNAL PROCESSOR S5L1462B NOTES 43