LOW POWER DTMF RECEIVER S5T3170 INTRODUCTION 18−DIP−300A The S5T3170 is a complete Dual Tone Multiple Frequency (DTMF) receiver that is fabricated by low power CMOS and the SwitchedCapacitor Filter technology. This LSI consists of band split filters, which separates counting section which verifies the frequency and duration of the received tones before passing the corresponding code to the output bus. It decodes all 16 DTMF tone pairs into a 4bits digital code. The externally required components are minimized by on chip provision of a differential input AMP, clock oscillator and latched three state interface. The on chip clock generator requires only a low cost TV crystal as an external component. 20−SOP−375 FEATURES • Detects all 16 standard tones. • Low power consumption: 15mW (Typ) • Single power supply: 5V • Uses inexpensive 3.58MHz crystal • Three state outputs for microprocessor interface • Good quality and performance for using in exchange system • Power down mode/input inhibit ORDERING INFORMATION Device Package Operating S5T3170X01-D0B0 18−DIP−300A S5T3170X01-S0B0 20−SOP−375 − 25°C — + 75°C APPLICATIONS • • • • • PABX Central Office Paging Systems Remote Control Credit Card Systems • • • • • Key Phone System Answering Phone Home Automation System Mobile Radio Remote Data Entry 1 S5T3170 LOW POWER DTMF RECEIVER PIN CONFIGURATION IN+ 1 18 VDD IN+ 1 20 VDD IN- 2 17 SI/GTO IN- 2 19 SI/GTO GS 3 16 ESO GS 3 18 ESO VREF 4 15 DSO VREF 4 17 DSO IIN 5 14 Q4 IIN 5 16 NC PDN 6 13 Q3 PDN 6 15 Q4 OSC1 7 12 Q2 NC 7 14 Q3 OSC2 8 11 Q1 OSC1 8 13 Q2 GND 9 10 OE OSC2 9 12 Q1 GND 10 11 OE S5T3170 S5T3170 (18-DIP) (20-SOP) PIN DESCRIPTION 2 Pin No Symbol Description 1 IN + Non inverting input of the internal amp. 2 IN − Inverting input of the internal amp. 3 GS Gain Select. The output used for gain adjustment of analog input signal with a feedback resistor. 4 VREF Reference Voltage output (VDD/2, Typ) can be used to bias the internal amp input of VDD/2. 5 IIN 6 PDN Input inhibit. High input states inhibits the detection of tones. This pin is pulled down internally. Control input for the stand-by power down mode. Power down occurs when the signal on this input is in high states. This pin is pulled down internally. LOW POWER DTMF RECEIVER S5T3170 PIN DESCRIPTION (Continued) Pin No Symbol Description 7, 8 OSC1 OSC2 Clock input/output. A inexpensive 3.579545MHz crystal connected between these pins completes internal oscillator. Also, external clock can be used. 9 GND Ground pin. 10 OE 11 - 14 Q1 - Q4 15 DSO Delayed Steering Output. Indicates that valid frequencies have been present for the required guard time, thus constituting a valid signal. Presents a logic high when a received tone pair has been registered and the output latch is updated. Returns to logic low when the voltage on SI/GTO falls below VTH. 16 ESO Early Steering Outputs. Indicates detection of valid tone output a logic high immediately when the digital algorithm detects a recognizable tone pair. Any momentary loss of signal condition will cause ESO to return to low. 17 SI/GTO 18 VDD Output Enable input. Outputs Q1-Q4 are CMOS push-pull when OE is High and open circuited (High impedance) when disabled by pulling OE low. Internal pull up resistor built in. Three state data output. When enabled by OE, these digital outputs provide the hexadecimal code corresponding to the last valid tone pair received. Steering Input/Guard Time Output. A voltage greater the VTS detected at SI causes the device to register the detected tone pair and update the output latch. A voltage less than VTS frees the device to accept a new tone pair. The GTO output acts to reset the external steering time constant, and its state is a function of ESO and the voltage on SI Power Supply (+5V, Typ) ABSOLUTE MAXIMUM RATINGS Characteristics Symbol Value Unit Power Supply Voltage VDD 6 V Analog Input Voltage Range VI (A) − 0.3 — VDD + 0.3 V Digital Input Voltage Range VI (D) − 0.3 — VDD + 0.3 V VO − 0.3 — VDD + 0.3 V II 10 V Operating Temperature TOPR − 40 — + 85 mA Storage Temperature TSTG − 60 — + 150 °C Output Voltage Range Current On Any Pin 3 S5T3170 LOW POWER DTMF RECEIVER ELECTRICAL CHARACTERISTICS (VDD = 5V, Ta = 25°C, unless otherwise noted) Characteristic Symbol Test Conditions Min. Typ. Max. Unit Operating Voltage VDD − 4.75 − 5.25 V Operating Current IDD − − 3.0 9.0 mA Power Dissipation PD − − 15 45 mW Input Voltage Low VIL − − − 1.5 V Input Voltage High VIH − 3.5 − − V VIN = GND or VDD − 0.1 − m Input Leakage Current II (LKG) Pull Up Current On OE Pin IPU OE = GND − 7.5 15 µA Analog Input Impedance RI fIN = 1KHz 8 10 − MΩ 2.2 − 2.5 V − Steering Input Threshold Voltage VTH Output Voltage Low VOL No Load − − 0.03 V VOH No Load 4.97 − − V 1 2.5 − mA IO (SOURCE) VOH = 4.6V 0.4 0.8 − mA Output Current (Sinking) Output Current (Sourcing) IO (SINK) VOL = 0.4V VREF Output Voltage VO (REF) − 2.4 − 2.8 V VREF Output Resistance RO (REF) − − 10 − KΩ VIO − − 25 − mV Power Supply Rejection Ratio PSRR Gain Setting Amp at 1KHz − 60 − dB Common Mode Rejection Ratio CMRR − 3.0V < VIN < 3.0V − 60 − dB Open Loop Voltage Gain GV Gain Setting Amp at 1KHz − 65 − dB Open Loop Unit Gain Bandwidth BW − − 1.5 − MHz RL = 100K − 4.5 − VP-P Analog Input Offset Voltage Analog Output Voltage Swing VO (P-P) Acceptable Capacitive Load CL GS − 100 − pF Acceptable Resistive Load RL GS − 50 − KΩ No Load − 3.0 − VP-P Analog Input Common Mode Voltage Range VCM VI(VAL) − −29 − 1.0 dBm TW − − ±10 − dB Acceptable Frequency Deviation ∆f − − − ±1.5% ± 2Hz − Frequency Deviation Reject ∆fR − ±3.5% − − − Valid Input Signal Range (each tone of composite signal) Dual Tone Twist Accept 4 LOW POWER DTMF RECEIVER S5T3170 ELECTRICAL CHARACTERISTICS (Continued) (VDD = 5V, Ta = 25°C, unless otherwise noted) Characteristic Symbol Test Conditions Min. Typ. Max. Unit T3rd − −25 −16 − dB Noise Tolerance TN − − −12 − dB Dial Tone Tolerance DT − 18 22 − dB Crystal Clock Frequency fCK − Third Tone Tolerance 3.5759 3.5795 3.5831 MHz Maximum Clock Input Rise Time tR(MAX) External Clock − − 110 nS Maximum Clock Input Fall Time tF(MAX) External Clock − − 110 nS DCK External Clock 40 50 60 % OSC2 PIN − − 30 pF Acceptable Clock Input Duty Cycle Acceptable Capacitive Load DL Tone Present Detect Time tDET(P) − 5 11 14 mS Tone Absent Detect Time tDET(A) − 0.5 4 8.5 mS Minimum Tone Duration Accept tTDA(MIN) User Adjustable − − 40 mS Minimum Tone Duration Reject tTDR(MAX) User Adjustable 20 − − mS Acceptable Interdigit Pause tIDP(A) User Adjustable − − 40 mS Rejectable Interdigit Pause tIDP(R) User Adjustable 20 − − mS Propagation Delay Time SI to Q tD(SI-Q) OE = High − 8 11 µS Propagation Delay Time SI to DSO tD(SI-D) OE = High − 12 16 µS tSU OE = High − 3.4 − µS Output Data Setup Q to DSO Propagation Delay Time OE to Q (Enable) tD(QE-Q)EN RL = 10K, CL = 50pF − 50 60 nS Propagation Delay Time OE to Q (Disable) tD(QE-Q)DIS RL = 10K, CL = 50pF − 300 − nS NOTES: 1. Digit sequence consists of all 16 DTMF tones. 2. Tone duration = 40mS, Tone pause = 40mS. 3. Nominal DTMF frequencies are used. 4. Both tones in the composite signal have an equal amplitude. 5. Tone pair is deviated by ± 1.5% ± 2Hz. 6. Bandwidth limited (3KHz) Gaussian Noise. 7. The precise dial tone frequencies are (350Hz and 440Hz) ± 2%. 8. For an error rate of better than 1 in 10000. 9. Referenced to lowest level frequency component in DTMF signal. 10. Minimum signal acceptance level is measured with specified maximum frequency deviation. 11. This item also applies to a third tone injected onto the power supply. 12. Referenced to Fig. 1 Input DTMF tone level at -28dBm. 5 3 15 14 13 12 11 10 R1 VCC 100K R2 100K 0.1µF X - tal 2 1 2 3 4 5 6 7 9 8 6 18 2 1 5 17 1 9 2 4 8 # 13 14 C1 300K 1 8 9 10 11 12 2 7 6 5 4 3 LED R3 VCC 18 17 16 15 14 13 12 11 10 HL74HCTLS02 Fig. 2 VCC VCC 1 c b g f 14 15 VCC 16 2 LT 3 RDO c 10 11 9 d 12 13 HL74LS47 a 4 ABI GND d 5 6 7 8 VCC R10 R9 R8 R7 R6 R5 R4 10 g 8 7 6 f com a b 9 3 4 5 a d com c dp 1 2 VCC Figure 1. Test Circuit 16 4 5 6 9 8 7 X - tal 1 7 0 LTS542R 3 KS58006 S5T5820C * 6 LOW POWER DTMF RECEIVER S5T3170 TEST CIRCUIT KT3170 S5T3170 LOW POWER DTMF RECEIVER S5T3170 TIMING DIAGRAM tTDR (MAX) tTDA (MIN) tIDP (A) DTMF #n tIDP (R) DTMF #n + 1 DTMF #n + 1 DTMF INPUT tDET (P) tDET (A) ESO tPGT tAGT VTH SI/GTO tSU DECODED TONE # (n - 1) Q1 - Q4 tD (SI-D) DSO tD (OE-Q) EN tD (OE-Q) DIS OE Figure 2. Timing Diagram 7 S5T3170 LOW POWER DTMF RECEIVER DIGITAL OUTPUT Outputs Q1-Q4 are CMOS push pull when enabled (EO = High) and open circuited (high impedance) when disabled by pulling EO = Low. These digital outputs provide the hexadecimal code corresponding to the DTMF signals. The table below describes the hexadecimal. NO Low Frequency High Frequency OE Q4 Q3 Q2 Q1 1 697 1209 H 0 0 0 1 2 697 1336 H 0 0 1 0 3 697 1477 H 0 0 1 1 4 770 1209 H 0 1 0 0 5 770 1336 H 0 1 0 1 6 770 1477 H 0 1 1 0 7 852 1209 H 0 1 1 1 8 852 1336 H 1 0 0 0 9 852 1477 H 1 0 0 1 0 941 1336 H 1 0 1 0 * 941 1209 H 1 0 1 1 # 941 1477 H 1 1 0 0 A 697 1633 H 1 1 0 1 B 770 1633 H 1 1 1 0 C 852 1633 H 1 1 1 1 D 941 1633 H 0 0 0 0 ANY - - L Z Z Z Z NOTE: Z : High Impedance H : High Logic Level L : Low Logic Level 8 LOW POWER DTMF RECEIVER S5T3170 APPLICATION CIRCUIT 0.1uF IN+ VDD IN- SI/GTO GS ESO 0.1uF +5V 100K 100K VREF 300K DSO 10nF C1 100K IN+ INGS IIN Q4 PDN Q3 OSC1 Q2 OSC2 Q1 GND OE 3.58MHz All resistors are 1% tolerance All capacitors are 5% tolerance Figure 3. Single Ended Input Configuration 10nF C2 1 + R1 100K R2 R5 R3 37.5K R2 60K 100K VREF 2 _ 3 4 S5T3170 R3 = R2R5/(R2+R5), VOLTAGE GAIN = R5/R1 2 INPUT IMPEDANCE :2 R1 + (1/wC)2 All resistors are 1% tolerance All resistors are 1% tolerance All capacitors are 5% tolerance Figure 4. Differential Ended Input Configuration 9 S5T3170 LOW POWER DTMF RECEIVER VDD C C SI/GTO SI/GTO R1 R1 R2 R2 ESO ESO tPGT = (R1C) In (VDD/VDD-VTH) tPGT = (RPC) In (VDD/VDD-VTH) tAGT = (RPC) In (VDD/VTST) tAGT = (R1C) In (VDD/VTH) R P = R1R2/(R1 + R2) RP = R1R2 (R1 + R2) Decreasing tAGT (tPGT > tAGT) Decreasing tPGT (tPGT< tAGT) Figure 5. Guard Time Adjustment S5T3170 S5T3170 30pF OSC1 OSC1 3.579545MHz OSC2 OSC2 TO OSC1 of next S5T3170 Figure 6. Oscillator Connection 10