Order this document by MC145446A/D SEMICONDUCTOR TECHNICAL DATA Product Preview # %" !$ The MC145446A is a silicon gate CMOS frequency shift keying (FSK) modem intended for use with telemeter systems or remote control systems over the telephone network. It replaces the MC145446. This device is compatible with CCITT V.21 and contains the entire circuit that provides a full–duplex or half–duplex 300–baud data communication over a pair of telephone lines. This device also includes the DTMF generator/receiver and call progress tone detector (CPTD). The differential line driver has the capability of driving 0 dBm into a 600 Ω load with a single 5 V power supply. The transmit level is controlled by the programmable attenuator in 1 dB steps. This device also includes a serial control interface and internal control and status registers that permit a CPU to exercise the following built–in features: • • • • • • • • • • • Single 5 V Power Supply Compatible with CCITT V.21 DTMF Generator and Receiver for All 16 Standard Digits Capable of Driving 0 dBm into a 600 Ω Load (VCC = 5 V) AGC (Auto Gain Control) Amplifier for DTMF Receiver Imprecise Call Progress Tone (400 Hz) Detector A Transmit Attenuator Programmable in 1 dB Steps 2100 Hz Answer Tone Generator Serial Control Interface Analog Loopback Configuration for Self Test Power–Down Mode, Less than 1 µA FW SUFFIX SOP CASE 751M 28 1 ORDERING INFORMATION MC145446AFW SOP PIN ASSIGNMENT VCC 1 28 FTLC1 GND 2 27 RxBO Vref 3 26 RxGC CDA 4 25 RxA DTMF IN 5 24 TxA1 AGC OUT 6 23 TxA2 FTLC2 7 22 DSI FTLC3 8 21 VCC X1 9 20 E X2 10 19 SCK TLA 11 18 DATA I/O GND 12 17 TxD VCC 13 16 RxD R/W 14 15 SD/CD/DV This document contains information on a new product. Specifications and information herein are subject to change without notice. REV 1 7/96 Motorola, Inc. 1996 MOTOROLA MC145446A 1 BLOCK DIAGRAM AGC OUT DTMF IN FLTC2 LOW–BAND BPF NOISE FILTER AGC FLTC1 FLTC3 FREQUENCY DETECTER RxBO + RxA HIGH–BAND BPF NOISE FILTER – CODE CONVERTER (DECODER) 4 STATUS REGISTER TIMING CIRCUIT SD/CD/DV RxGC 30 k 65 k FSK/DTMF LOOPBACK PATH TxD TLA FSK MODULATOR LEVEL CONTROL DTMF GENERATOR LOW–BAND BPF MUX HIGH–BAND BPF MUX/ MIXING CARRIER/CPT DETECTOR CDA FSK DEMODULATOR RxD MUX MODE CONTROL LOGIC DATA I/O DSI SMOOTHING FILTER CONTROL SHIFT REGISTER –1 _ + STATUS SHIFT REGISTER TxA2 TxA1 R/W E SCK POWER–ON RESET VCC MC145446A 2 ANALOG GROUND GENERATOR GND Vref CLOCK GENERATOR X1 X2 MOTOROLA ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSS) Rating Symbol Value Unit VCC – 0.5 to 7.0 V DC Input Voltage Vin – 0.5 to VCC + 0.5 V DC Output Voltage Vout – 0.5 to VCC + 0.5 V IIK, IOK ± 20 mA Iout ± 25 mA DC Supply Voltage Clamp Diode Current per Pin DC Current per Pin Power Dissipation PD 500 mW Storage Temperature Range Tstg – 65 to 150 °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications of any voltage higher than the maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or VDD). RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit VCC 4.5 5 5.5 V DC Input Voltage Vin 0 — VCC V DC Output Voltage Vout 0 — VCC V tr 0 — 500 ns DC Supply Voltage Input Rise Time Input Fall Time Crystal Frequency Operating Temperature Range tf 0 — 500 ns fosc — 3.579545 — MHz TA – 20 25 70 °C DC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = – 20 to 70°C) Symbol Characteristic Input Voltage Output Voltage Conditions Min Typ Max Unit V H Level VIH 3.15 — — L Level VIL — — 1.1 H Level VOH IOH = 20 µA VCC – 0.1 VCC – 0.01 — L Level VOL IOL = 20 µA IOL = 2 mA — — 0.01 — 0.1 0.4 Vin = VCC or GND — ± 1.0 ± 10.0 µA FSK Mode — 8 — mA DCMF Receive Mode — 10 — Power–Down Mode 1 — — 500 µA Power–Down Mode 2 — — 1 µA Conditions Min Typ Max Unit Crystal Frequency 3.579545 MHz 974 980 986 Hz 1174 1180 1186 Input Current TxD, E, SCK, DATA I/O, R/W Quiescent Supply Current Iin ICC ICC Power–Down Supply Current V TRANSMIT CARRIER CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = – 20 to 70°C) Symbol Characteristic Carrier Frequency Channel 1 Carrier Frequency Channel 2 Answer Tone Mark ‘‘1’’ f1M Space ‘‘0’’ f1S Mark ‘‘1’’ f2M 1644 1650 1656 Space ‘‘0’’ f2S 1844 1850 1856 2090 2100 2110 — 7 — dBm — – 46 — dBm fans Transmit Carrier Level VO* Second Harmonic Energy V2h* Out–of–Band Energy VOE* Attenuator = 0 dB RTLA = ∞, RL = 1.2 kΩ, VTxA1 – VTxA2 Figure 2 dBm * VTxA1 – VTxA2, RL = 1.2 kΩ MOTOROLA MC145446A 3 TRANSMIT ATTENUATOR CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = – 20 to 70°C) Characteristic Symbol Attenuator Range Attenuator Accuracy 1 dB – 5 dB Min Typ Max Unit ARNG Conditions 0 — 15 dB AACC – 0.5 — 0.5 dB –1 — 1 – 1.7 — 1 6 dB – 9 dB 10 dB – 15 dB RECEIVER CHARACTERISTICS (INCLUDES HYBRID, DEMODULATOR, AND CARRIER DETECTOR) (VCC = 5.0 V ± 10%, TA = – 20 to 70°C) Symbol Characteristic Input Impedance RIRX Receiver Carrier Amplitude VIRX Carrier Detect Threshold OFF to ON VCDON ON to OFF VCDOF Hysterisis (VCDON – VCDOF) Carrier Detect Timing Conditions Min Typ Max Unit 50 — — kΩ – 48 — – 12 dBm — – 44 — dBm — – 47 — 2 — — dB CD1 = 0, CD0 = 0 — 450 — ms CD1 = 0, CD0 = 1 — 10 — CD1 = 1, CD0 = 0 — 10 — CD1 = 1, CD0 = 1 — 70 — CD1 = 0, CD0 = 0 — 35 — CD1 = 0, CD0 = 1 — 35 — CD1 = 1, CD0 = 0 — 20 — CD1 = 1, CD0 = 1 — 15 — Min Typ Max Unit RxA Pin CDA = 1.2 5V fin = 1.0 kHz HYS OFF to ON ON to OFF TCDON TCDOFF CPTD CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = – 20 to 70°C) Symbol Characteristic Conditions Bandpass Filter Center Frequency fc — 400 — Hz Bandpass Filter – 3 dB Band Width ∆ BW — 140 — Hz — – 44 — dBm — – 47 — Tone Detect Level Tone Detect Timing CDA = 1.25 V fin = 400 Hz OFF to ON VTDON ON to OFF VTDOF OFF to ON TTDON — 10 — ON to OFF TTDOF — 25 — Min Typ Max Unit — 2.5 — dBm — 3.5 — 0 — 3 dB — 5 — % –1 — 1 % — ms ms DTMF TRANSMIT CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = – 20 to 70°C) Symbol Characteristic Tone Output Level High Group Pre–Emphasis DTMF Distortion Low Group Vfl High Group Vfh PE DIST DTMF Frequency Variation ∆fV Out–of–Band Energy VOE Setup Time tosc MC145446A 4 Conditions Attenuator = 0 dB RTLA = ∞ Crystal Frequency 3.579545 MHz Single Tone Mode VTxA1 – VTxA2, RL = 1.2 kΩ Figure 1 — 4 dB MOTOROLA DTMF RECEIVER CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = – 20 to 70°C) Characteristic Symbol Conditions Min Typ Max Unit 50 — — kΩ Detect Signal Level (Each Tone) – 48 — 0 dBm Twist (High Group Tone/Low Group Tone – 10 — 10 dB Frequency Detect Band Width (Figure 4) ± 1.5% ± 2 Hz — — — — — ± 3.5 % CD1 = 0, CD0 = 1 — 25 — ms CD1 = 1, CD0 = 0 — 30 — CD1 = 1, CD0 = 1 — 40 — CD1 = 0, CD0 = 1 — 25 — CD1 = 1, CD0 = 0 — 35 — CD1 = 1, CD0 = 1 — 25 — Typ Max Input Impedance Frequency No–Detect Band Width (Figure 4) DTMF Detect Timing OFF to ON ON to OFF TCDON TCDOFF DEMODULATOR CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = – 20 to 70°C) Characteristic Bit Bias Bit Error Rate (CCITT Line Simulation, 511–Bit Pattern) Symbol Conditions Min ID Input Level = – 24 dBm S/N = 4 dB — 5 — % — 0.00001 — — BER Unit SWITCHING CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = – 20 to 70°C) Symbol Timing Diagram Reference No. Min Typ Max Unit Input Pulse Width (H) E, SCK twh 1 50 — — ns Input Pulse Width (L) E, SCK twl 2 50 — — ns Clock Cycle tc 3 100 — — ns Input Rise Time tr 4 — — 2 µs Input Fall Time tf 5 — — 2 µs trec 6, 18 50 — — ns tsu 7 50 — — ns R/W↓ to DATA 9 100 — — ns R/W↑ to DATA 12 50 — — ns 8 50 — — ns E to R/W 10 50 — — ns DATA to R/W 14 50 — — ns R/W to DATA 15 50 — — ns 13 — — 50 ns 17 — — 50 ns Characteristic Recovery Time E to SCK Setup Time Hold Time Read Data Delay Time DATA to SCK SCK to DATA E to DATA th td SCK to DATA Enable Minimum Interval twe 11 — — 450 ns Mode Switch Minimum Interval twm 16 — — 600 ns MOTOROLA MC145446A 5 CONTROL REGISTER 1 (NOTE 1) E* (NOTE 6) 6 SCK 1 2 7 3 4 5 2 8 9 DATA 7 3 CD1 CD0 6 7 SQ T3 9 10 11 12 13 14 15 16 (LSB CLOCK) 5 1 CH 8 4 T2 T1 T0 A3 A2 A1 A0 M3 M2 M1 M0 10 R/W * The enable signal corresponds to preceding data format. STATUS REGISTER 11 E 1 2 (NOTE 7) 18 12 (NOTE 5) 4 3 SCK 5 1 2 3 13 0 2 2 1 (NOTE 3) 5 4 1 (NOTE 2) 17 DATA 1 D0 D1 D2 D3 D0 D1 D2 D0 D1 14 16 (HIGH–IMPEDANCE) 15 (NOTE 4) R/W NOTES: 1. The data in front of the enable signal pulse will be latched. 2. The latched data will be repeated until there is an enable pulse. 3. The detected data will be updated with the next enable pulse. 4. After the R/W pin becomes INACTIVE, the data will be lost. 5. D1 corresponds to Clock1. 6. The enable and the SCK signals need to be set at the logic low level when the R/W signal changes. 7. The SCK must be held at low level when the enable signal is at high level. Figure 1. Serial Data Input Timing MC145446A 6 MOTOROLA TRANSMIT CARRIER LEVEL (dBr) 0 3.4 k 4 k 16 k 256 k f (Hz) 0 – 25 – 15 dB/OCT. – 55 Figure 2. Out–of–Band Energy Von Voff RxA, DTMF IN ton toff SD/DV/CD Figure 3. FSK, DTMF Carrier Detect Timing ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ NO–DETECT DETECT MINIMUM WIDTH – 3.5% ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ NO–DETECT + 3.5% – 1.5% – 2 Hz fo + 1.5% + 2 Hz Figure 4. DTMF Frequency Detect Bandwidth MOTOROLA MC145446A 7 PIN DESCRIPTIONS VCC Positive Power Supply (Pins 1, 13, 21) TxD Transmit Data Input (Pin 17) The digital supply pins, which are connected to the positive power supply (5 V). This pin is the transmit data input. When the device is in FSK mode, the mark frequency is generated when this pin is at the logic high level. The space frequency is generated when the pin is at a logic low. GND Ground Pins (Pins 2, 12) RxD Receive Data Output (Pin 16) The ground pins are connected to the system ground. Vref Reference Analog Ground (Pin 3) This pin provides the analog ground voltage, which is internally regulated to VCC/2. It should be decoupled to the GND with 0.1 µF and 100 µF capacitors. X1 Crystal Oscillator Output (Pin 9) A 3.579545 MHz ± 0.1% crystal oscillator is tied to this pin with the other end connected to X2. X2 Crystal Oscillator Input (Pin 10) A 3.579545 MHz ± 0.1% crystal oscillator is tied to this pin with the other end connected to X1. X2 may also be driven directly from an appropriate external source. SCK Serial Clock Input (Pin 19) This pin is the clock input for the 16–bit control resistor and the 4–bit status resistor. The serial data is captured into the control register, or is shifted out of the status register on the rising edge of SCK. DATA I/O Serial Data Input/Output (Pin 18) This pin is the 16–bit control register input, which determines the operation mode, DTMF tone, transmit attenuation (receiver gain), carrier detect time, channel, and transmit squelch. This pin is also the four–bit status register output which indicates the received DTMF tone (hexadecimal codes). E Enable Input (Pin 20) When the R/W pin is at logic low, high level on the E pin makes the 16–bit control register data transparent to the mode control logic so that the device operation is changed. While this pin is at logic low, the control register and the mode control logic are isolated. The E pin must NOT be held high while the control register data is being changed. When the R/W pin is at logic high, the rising edge of E transfers the four–bit DTMF data from the DTMF decoder to the status register. Then the first bit (LSB = D0) is presented at the Data I/O pin. R/W Read/Write Data Switch (Pin 14) This pin is used for controlling the I/O direction of the Data I/O pin. MC145446A 8 This pin is the receive data output. When the device is in the FSK mode, a high logic level of this pin indicates that the mark carrier frequency has been received, and a low logic level indicates the space carrier frequency has been received. SD/CD/DV Carrier/Call Progress Tone Detect/DTMF Data Valid Detect (Pin 15) This pin works as a carrier detector in the FSK mode, whereas it works as the call progress tone detector in the CPTD mode and as the receive DTMF detector in the DTMF Rx mode. The output goes to a logic low level when the input signal reaches the minimum threshold of the detect level that is adjusted by the CDA voltage. When this pin is logic high, the receive data output (RxD) is clamped high to avoid the error that may occur with the loop noise. In DTMF Rx mode, the logic low on this pin indicates that the valid DTMF frequencies are detected. The received tone is decoded to four–bit data, then stored in the DTMF decoder by the falling edge of DV. TxA1 Non–Inverting Transmit Analog Carrier Output (Pin 24) This pin is the line driver non–inverting output. A 7 dBm (typ) differential output voltage can be obtained by connecting a 1.2 kΩ load resistor between Tx1 and Tx2. Attention must be paid so as not to exceed this level when an external input is added to the DSI pin. A telephone line (600 Ω) is driven through an external 600 Ω resistor (see the Application Circuit). In this case, the output level becomes about a half of the differential output. TxA2 Inverting Transmit Analog Carrier Output (Pin 23) This pin is the line driver inverting output. The signal is equal in magnitude, but 180° out of phase with the TxA1 (refer to TxA1). RxA Receive Signal Input (Pin 25) This pin is the carrier signal input, and is enabled when the device is in FSK or CPTD mode. RxGC Receive Gain Adjust (Pin 26) This pin is used to adjust the receive buffer gain. To adjust the gain, a resistor may be added between this pin and the RxBO pin (refer to the Block Diagram). This pin may be held open when the gain adjustment is not needed. RxBO Receive Buffer Output (Pin 27) This pin is the receive buffer output. MOTOROLA DTMF IN DTMF Receive Input (AGC Amp Input) (Pin 5) This pin is the receive DTMF signal input. It is enabled when the device is in the DTMF receive mode. AGC OUT AGC Output (Pin 6) This pin is used by the manufacturer to test the auto gain control amplifier. It should be held open in normal operation. DSI Driver Summing Input (Pin 22) This pin is the inverting input of the line driver. An external signal may be transmitted through an external series resistor RDSI. The differential gain GDSI = (VTxA1 – VTxA2)/VDSI is determined by the following equation: GDSI = – 2Rf / RDSI, Rf X 20 kΩ Note that the programmable transmit attenuator does not affect in this case. The DSI pin should be held open when not in use. CDA Carrier Detect Level/CPTD Level Control (Pin 4) The carrier/call progress tone detect level is adjusted by the CDA pin voltage. When this pin is held open, the CDA voltage is set to 1.25 V (VCC = ± 5 V) by an internal divider. Then the detect level is set at – 44 dBm (typ) for off to on, and – 47 dBm (typ) for on to off, and the hysteresis is set minimum 2 dB. This pin has a very high input impedance so it should be connected to GND with a 0.1 µF capacitor to keep it under the regulations. An external voltage may be applied to this pin to adjust the carrier detect threshold. The following equations may be used to find the CDA voltage required for a given threshold voltage: VCDA = 245 × Von VCDA = 347 × Voff TLA Transmit Carrier Level Adjust (Pin 11) This pin is used to adjust the transmit carrier level that is determined by the value of the resistor (RTLA) connected between this pin and the GND. The maximum level can be obtained when this pin is shorted to GND (RTLA = 0). FTLC1 FSK Filter Test (Pin 28) This pin is a high–impedence filter output. It may be used for testing the FSK filter characteristics, and is reserved for manufacturer’s use only. In normal operation, this pin should be decoupled to Vref with a 0.1 µF capacitor. MOTOROLA FTLC2 DTMF Receive Low Group Filter Test (Pin 7) This pin is a high–impedence filter output. It may be used for testing the DTMF receive high goup bandpass filter characteristics, and is reserved for manufacturer’s use only. In normal operation, this pin should be decoupled to Vref with a 0.1 µF capacitor. FTLC3 DTMF Receive High Group Filter Test (Pin 8) This pin is a high–impedence filter output. It may be used for testing the DTMF receive high group bandpass filter characteristics, and is reserved for manufacturer’s use only. In normal operation, this pin should be decoupled to Vref with a 0.1 µF capacitor. SERIAL CONTROL INTERFACE The following six functions are determined by the 16 bits of serial data in the control register. CONTROL REGISTER FUNCTION MODE : M3 M2 M1 M0 TRANSMIT ATTENUATOR : A3 A2 A1 A0 TRANSMIT TONE FREQUENCY : T3 T2 T1 T0 TRANSMIT SQUELCH : SQ CHANNEL : CH CARRIER DETECT TIME : CD1 CD0 The received DTMF tones are indicated by the four bits of data in the status register. STATUS REGISTER RECEIVE TONE FREQUENCY : D3 D2 D1 D0 Figure 1 presents the timing diagram of 16–bit control register input and four–bit status output. When the R/W pin is in logic low, the 16–bit data is captured into the control register at the rising edge of SCK and latched in the mode control logic to update the function mode at logic high input to the E pin. When the R/W pin is in logic high, the status register is selected to read out the received DTMF data, the four–bit data in the DTMF decoder is loaded into the status register, and the first bit (D0) is presented at the Data I/O on the rising edge of E. The following bits are repeatedly shifted out as D1–D2–D3–D0–D1–... by the rising edges of SCK. CONTROL REGISTER BIT MAP DESCRIPTION FUNCTION MODE (M3 to M0) One of the following modes is selected from the four–bit data (M3 to M0) shown in Table 1. Table 2 presents each output status; the functions are described below. MC145446A 9 DTMF Receive Mode Table 1. Function Mode Truth Table M3 M2 M1 M0 0 0 0 0 FSK Function Mode 0 0 0 1 FSK Analog Loopback 0 0 1 0 CPTD DTMF Analog Loopback Mode 0 0 1 1 Answer Tone 0 1 0 0 DTMF Transmit 0 1 0 1 Single Tone The transmitter, working as a DTMF tone generator, is internally connected to the receiver working as DTMF tone receiver. The DV goes low when the receiver detects a valid DTMF tone. This feature is used for the device self test. 0 1 1 0 Power–Down 1 0 1 1 1 Power–Down 2 1 0 0 0 DTMF Receive 1 0 0 1 DTMF Analog Loopback The receiver works as a DTMF tone receiver. The DV goes low when a valid DTMF tone is detected. The transmitter is disabled. Single Tone Mode The transmitter generates one of the eight frequencies of the DTMF tone. The receiver is disabled. Power–Down Mode 1 FSK Mode Whole internal circuits, except the oscillator, are disabled and all outputs except the X1 pin go to the high–impedance state. The supply current decreases to 500 µA (max). The transmitter and the receiver work as an FSK modulator/demodulator. The SD pin goes low when a valid FSK signal is detected. Power–Down Mode 2 DTMF Transmit Mode The transmitter works as a DTMF tone generator. The receiver is disabled. CPTD (Call Progress Tone Detect) Mode The receiver works as a 400 Hz call progress tone detector. The CD pin goes low when a valid call progress tone is detected. Answer Tone Mode The transmitter works as a 2100 Hz answer tone generator. The receiver is disabled. FSK Analog Loopback Mode The transmitter, working as the FSK modulator, is internally connected to the receiver working as the FSK demodulator. This feature is used for the device self test. Whole internal circuits, including the oscillator, are disabled and all outputs go to the high–impedance state. The supply current decreases to 1.0 µA (max). Transmit Attenuator/AGC Gain Set (A3 to A0) Four–bit serial data (A3 – A0) sets up the analog transmit level in the FSK, answer tone, DTMF, analog loopback, and single tone mode. The range of the transmit attenuator is 0 to 15 dB in 1 dB steps. The attenuator, however, does not affect the external signal input from the DSI. These bits also determine the AGC amplifier gain in the DTMF receive mode. In normal operation, “Automatic” may be selected so that the gain is automatically adjusted corresponding to the input signal level. See Table 3 for a detailed description. Transmit Tone Frequency (T3 to T0) These four bits (T3 to T0) determine the DTMF tone frequencies in DTMF transmit and DTMF analog loopback mode, and determine the single tone frequency in the single tone mode. Tone frequency assignments with reference to T3 – T0 are shown in Table 4. Table 2. Output Status Output Pin Function Mode RxD SD/CD/DV TxA1, TxA2 Receive Digital Data Carrier Detect Signal FSK Call Progress Tone H CPTD Signal VCC/2 Answer Tone H H Answer Tone DTMF Transmit H H DTMF Tone Single Tone H H Single Tone High Impedance High Impedance High Impedance H DV Signal VCC/2 FSK FSK Loopback Power–Down 1, 2 DTMF Receive DTMF Loopback MC145446A 10 DTMF Tone MOTOROLA Table 3. Transmit Attenuator/AGC Gain Set Truth Table A3 A2 A1 A0 Attenuation (dB) AGC Gain Step (dB) 0 0 0 0 0 – 5.0 0 0 0 1 1 – 2.5 0 0 1 0 2 0.0 0 0 1 1 3 2.5 0 1 0 0 4 5.0 0 1 0 1 5 7.5 0 1 1 0 6 10.0 0 1 1 1 7 12.5 1 0 0 0 8 15.0 1 0 0 1 9 17.5 1 0 1 0 10 20.0 1 0 1 1 11 Clamp 1 1 0 0 12 Automatic 1 1 0 1 13 — 1 1 1 0 14 — 1 1 1 1 15 — Table 4. Tone Frequency Truth Table Tone Frequency (Hz) DTMF Mode MOTOROLA T3/D3 T2/D2 T1/D1 T0/D0 Low Group High Group Keyboard Equivalent Single Tone Mode 0 0 0 0 941 1633 D 941 0 0 0 1 697 1209 1 697 0 0 1 0 697 1336 2 697 0 0 1 1 697 1477 3 697 0 1 0 0 770 1209 4 770 0 1 0 1 770 1336 5 770 0 1 1 0 770 1477 6 770 0 1 1 1 852 1209 7 852 1 0 0 0 852 1336 8 1336 1 0 0 1 852 1477 9 1477 1 0 1 0 941 1336 0 1336 1 0 1 1 941 1209 * 1209 1 1 0 0 941 1477 # 1477 1 1 0 1 697 1633 A 1633 1 1 1 0 770 1633 B 1633 1 1 1 1 852 1633 C 1633 MC145446A 11 Transmit Squelch Table 7. Carrier/DTMF Detect Time Truth Table The 1–bit serial data (SQ) controls the transmit analog squelch. The FSK signal, DTMF tones, single tone, and answer tone are disabled, then TxA1 and TxA2 will be clamped to VCC/2 when the transmit squelch goes to the Enable (SQ = 1) state. The transmit squelch does not affect the external signal from the DSI. Table 5. Transmit Squelch Truth Table SQ Squelch 1 Enable 0 Disable FSK Mode Carrier Detect Time (typ) DTMF Receive Mode Carrier Detect Time (typ) ton (ms) CD1 CD0 ton (ms) toff (ms) 0 0 450 35 0 1 10 35 25 25 1 0 10 20 30 35 1 1 70 15 40 25 toff (ms) Reserved Power–On Reset Channel When the function mode is either on the FSK or analog loopback mode, the transmit and receive channel is set up with a 1–bit serial data (CH). Table 6. Channel Truth Table CH Channel 1 1 (Originate) 0 2 (Answer) Carrier Detect Time The carrier and DTMF tone detect timing are determined by two–bit serial data (CD1, CD0). The timing diagram is shown in Figure 3. MC145446A 12 When the power is switched on, this device is entered into Power–Down Mode 2 by the internal power–on reset circuit. STATUS REGISTER BIT MAP DESCRIPTION Received Tone Frequency (D3 to D0) This four–bit data (D3 to D0) indicates the received DTMF tones. The first bit (D0) is presented at Data I/O on the rising edge of E, and the following bits (D1–D2–D3–D0–D1– ...) are shifted out and presented on the next rising edge of SCK. The data configuration corresponding to each tone is shown in Table 4. MOTOROLA 100 µF 0.1 µF 10 Ω 600 : 600 TxA2 VREF TIP * 600 Ω TxA1 FTLC1 RING RxA 0.1 µF DTMF IN RxGC FTLC2 0.1 µF RxBO MC145446A TxD RxD FTLC3 0.1 µF I/O PORT SD/CD/DV R/W MCU DATA I/O CDA 0.1 µF SCK TLA E DSI 0.1 µF 100 µF VCC +5V GND * LINE PROTECTION CIRCUIT SYSTEM GROUND REFERENCE ANALOG GROUND Figure 5. Application Circuit MOTOROLA MC145446A 13 PACKAGE DIMENSIONS FW SUFFIX SOP CASE 751M–01 VIEW AB A -Y- 28 15 B -Z- 1 E V X 45_ " 5_ 14 D 28X 0.25 (0.010) M T Z 0.18 (0.007) M T S Y 0.18 (0.007) S M T Y S Z S VIEW AB CL NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.65 (0.026). MILLIMETERS MIN MAX 17.80 18.03 7.40 7.62 2.65 2.25 2.45 0.35 0.51 10.00 10.60 0.40 0.70 1.27 BSC 0.10 0.25 0.635 BSC 8_ 0.25 0.75 0.05 0.20 1.40 REF DIM A B C C1 D E F G J L θ V W X INCHES MIN MAX 0.701 0.710 0.291 0.300 0.104 0.090 0.096 0.014 0.020 0.394 0.414 0.016 0.028 0.050 BSC 0.004 0.010 0.025 BSC 8_ 0.010 0.030 0.002 0.008 0.110 REF 0.10 (0.004) T C J C1 -T- SEATING PLANE W L G 4X 24X W REF F θ Z Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MC145446A 14 ◊ *MC145446A/D* MC145446A/D MOTOROLA