KT3170 LOW POWER DTMF RECEIVER INTRODUCTION 18-DIP-300A The KT3170 is a complete Dual Tone Multiple Frequency (DTMF) receiver that is fabricated by low power CMOS and the Switched-Capacitor Filter technology. This LSI consists of band split filters, which seperates counting section which verifies the frequency and duration of the received tones before passing the corresponding code to the output bus. It decodes all 16 DTMF tone pairs into a 4bits digital code. The externally required components are minimized by on chip provision of a differential input AMP, clock oscillator and latched three state interface. The on chip clock generator requires only a low cost TV cystal as an external component. FEATURES • • • • • • Detects all 16 standard tones. Low power consumption : 15mW (Typ) Single power supply : 5V Uses inexpensive 3.58MHz crystal Three state outputs for microprocessor interface Good quality and performance for using in exchange system • Power down mode/input inhibit APPLICATIONS • • • • • • • • • • PABX Central Office Paging Systems Remote Control Credit Card Systems Key Phone System Answering Phone Home Automation System Mobile Radio Remote Data Entry ORDERING INFORMATION Device Package Operating KT3170N 18-DIP-300A - 25°C ~ + 75°C PIN CONFIGURATION IN+ 1 18 VDD IN- 2 17 SI/GTO GS 3 16 ESO VREF 4 15 DSO IIN 5 14 Q4 PDN 6 13 Q3 OSC1 7 12 Q2 OSC2 8 11 Q1 GND 9 10 OE KT3170 Fig. 1 KT3170 LOW POWER DTMF RECEIVER PIN DESCRIPTION Pin No Symbol 1 IN + Non inverting input of the op amp. 2 IN - Inverting input of the op amp. 3 GS 4 VREF 5 IIN Description Gain Select. The output used for gain adjustment of analog input signal with a feedback resistor. Reference Voltage output (VDD/2, Typ) can be used to bias the op amp input of VDD/2. Input inhibit. High input states inhibits the detection of tones. This pin is pulled down internally. Control input for the stand-by power down mode. Power down occurs 6 PDN when the signal on this input is in high states. This pin is pulled down internally. 7, 8 OSC1 OSC2 9 GND 10 OE Clock input/output. A inexpensive 3.579545MHz crystal connected between these pins completes internal oscillator. Also, external clock can be used. Ground pin. Output Enable input. Outputs Q1-Q4 are CMOS push pull when OE is High and open circuited (High impedance) when disabled by pulling OE low. Internal pull up resistor built in. Three state data output. When enabled by OE, these digital outputs 11 - 14 Q1 - Q4 provide the hexadecimal code corresponding to the last valid tone pair received. Delayed Steering Output. Indicates that valid frequencies have been present for the required guard time, thus constituting a valid signal. 15 DSO Presents a logic high when a received tone pair has been registered and the output latch is updated. Returns to logic low when the voltage on SI/GTO falls below VTH. Early Steering Outputs. Indicates detection of valid tone output a 16 ESO logic high immediately when the digital algorithm detects a recognizable tone pair. Any momentary loss of signal condition will cause ESO to return to low. Steering Input/Guard Time Output. A voltage greater the VTS detected at SI causes the device to register the detected tone pair 17 SI/GTO and update the output latch. A voltage less than VTS frees the device to accept a new tone pair. The GTO output acts to reset the external steering time constant, and its state is a function of ESO and the voltage on SI 18 VDD Power Supply (+5V, Typ) KT3170 LOW POWER DTMF RECEIVER ABSOLUTE MAXIMUM RATINGS Characteristics Symbol Value Unit Power Supper Voltage VDD 6 V Analog Input Voltage Range VI (A) - 0.3 ~ VDD + 0.3 V Digital Input Voltage Range VI (D) - 0.3 ~ VDD + 0.3 V VO - 0.3 ~ VDD + 0.3 V II 10 mA Output Voltage Range Current On Any Pin Operating Temperature T OPR - 40 ~ + 85 °C Storage Temperature T STG -60 ~ + 150 °C ELECTRICAL CHARACTERISTICS Characteristic (VDD = 5V, Ta = 25°C, unless otherwise noted) Symbol Test Conditions Min Typ Max Unit Operating Voltage VDD - 4.75 - 5.25 V Operating Current IDD - - 3.0 9.0 mA Power Dissipation PD - - 15 45 mW Input Voltage Low VIL - - - 1.5 V Input Voltage High VIH - 3.5 - - V - 0.1 - µA Input Leakage Current II (LKG) VIN = GND or VDD Pull Up Current On OE Pin IPU OE = GND - 7.5 15 µA Analog Input Impedance RI fIN = 1KHz 8 10 - MΩ Steering Input Threshold Voltage VTH 2.2 - 2.5 V Output Voltage Low VOL No Load - - 0.03 V VOH No Load 4.97 - 1 2.5 - - Output Current IO (SINK) VOL = 0.4V Output Current IO (SOURCE) VOH = 4.6V V - mA mA 0.4 0.8 - VREF Output Voltage VO (REF) - 2.4 - 2.8 VREF Output Resistance RO (REF) - - 10 - KΩ - - 25 - mV - 60 - dB Analog Input Offset Voltage VIO Power Supply Rejection Ratio PSRR Common Mode Rejection Ratio CMRR Open Loop Voltage Gain Open Loop Unit Gain Bandwidth Analog Output Voltage Swing GV Gain Setting Amp at 1KHz - 3.0V < VIN < 3.0V - 60 - dB Gain Setting Amp at 1KHz - 65 - dB BW VO (P-P) V - 1.5 - MHz RL = 100K - - 4.5 - VP-P Acceptable Capacitive Load CL GS - 100 - pF Acceptable Resistive Load RL GS - 50 - KΩ VCM No Load - 3.0 - VP-P Analog Input Common Mode Voltage Range KT3170 LOW POWER DTMF RECEIVER AC ELECTRICAL CHARACTERISTICS Characteristic Valid Input Signal Range (VDD = 5V, Ta = 25°C, fCK = 3.579545MHz) Symbol Test Conditions Min Typ Max Unit VI (VAL) - -29 - 1.0 dBm TW - - ± 10 - dB - ± 1.5% - (each tone of composite signal) Dual Tone Twist Accept Acceptable Frequency Deviation ∆f - - ± 2Hz ∆fR - ± 3.5% - - - T3rd - -25 -16 - dB Noise Tolerance TN - - -12 - dB Dial Tolerance DT - 18 22 - dB Crystal Clock Frequency fCK - 3.5759 3.5795 3.5831 MHz Frequency Deviation Reject Third Tone Tolerance Maximum Clock Input Rise Time tR (MAX) External Clock - - 110 nS Maximum Clock Input Fall Time tF (MAX) External Clock - - 110 nS Acceptable Clock Input Duty Cycle DCK External Clock 40 50 60 % Acceptable Capacitive Load CL OSC2 PIN - - 30 pF Tone Present Detect Time tDET (P) - 5 11 14 mS Tone Absent Detect Time tDET (A) - 0.5 4 8.5 mS Minimum Tone Duration Accept tTDA (MIN) User Adjustable - - 40 mS Maximum Tone Duration Reject tTDR (MAX) User Adjustable 20 - - mS Acceptable Interdigit Pause tIDP (A) User Adjustable - - 40 mS Rejectable Interdigit Pause tIDP (R) User Adjustable 20 - - mS Propagation Delay Time SI to Q tD (SI-Q) OE = High - 8 11 µS Propagation Delay Time SI to DSO tD (SI-D) OE = High - 12 16 µS tSU OE = High - 3.4 - µS tD (QE-Q) EN RL = 10K, CL = 50pF - 50 60 nS tD (OE-Q) DIS RL = 10K, CL = 50pF - 300 - nS Output Data Setup Q to DSO Propagation Delay Time OE to Q (Enable) Propagation Delay Time OE to Q (disable) Notes : 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. Digit sequence consists of all 16 DTMF tones. Tone duration = 40mS, Tone pause = 40mS. Nominal DTMF frequencies are used. Both tones in the composite signal have an equal amplitude. Tone pair is deviated by ± 1.5% ± 2Hz. Bandwidth limited (3KHz) Gaussian Noise. The precise dial tone frequencies are (350Hz and 440Hz) ± 2%. For an error rate of better than 1 in 10000. Referenced to lowest level frequency component in DTMF signal. Minimum signal acceptance level is measured with specitied maximum frequency deviation. This item also applies to a third tone injected onto the power supply. Referenced to Fig. 1 Input DTMF tone level at -28dBm. LOW POWER DTMF RECEIVER KT3170 TEST CIRCUIT 6 3 18 14 13 12 11 10 R1 VCC 100K R2 100K 0.1µF X - tal 2 1 2 3 4 5 6 7 9 8 2 9 1 14 C1 LED 300K 8 9 10 11 12 13 7 6 5 4 3 2 R3 VCC 18 17 16 15 14 13 12 11 10 HL74HCTLS02 Fig. 2 VCC VCC 1 b 16 14 15 g f LT 13 c 10 11 9 d 12 a VCC HL74LS47 c 3 RDO 2 4 ABI GND d 5 6 7 8 VCC R9 R10 R8 R7 R6 R5 R4 10 g 8 7 6 f com a b 9 3 4 5 a d com c dp 1 2 VCC LTS542R 1 5 17 1 8 2 4 # 16 7 0 3 * 15 KS58006 4 5 6 X - tal 1 9 8 7 KT3170 KT3170 LOW POWER DTMF RECEIVER TIMING DIAGRAM tT D R tTDA (MAX) tI D P (MIN) tI D P (A) DTMF #n DTMF #n + 1 (R) DTMF #n + 1 DTMF INPUT tD E T tD E T (P) (A) ESO tPGT tAGT V TH SI/GTO t SU DECODED TONE # (n - 1) Q1 - Q4 tD (SI-D) DSO tD (OE-Q) EN tD (OE-Q) DIS OE Fig. 3 DIGITAL OUTPUT Outputs Q1-Q4 are CMOS push pull when enabled (EO = High) and open circuited (high impedance) when disabled by pulling EO = Low. These digital outputs provide the hexadecimal code corresponding to the DTMF signals. The table below describes the hexadecimal. NO LOW HIGH FREQUENCY FREQUENCY OE Q4 Q3 Q2 Q1 1 697 1209 H 0 0 0 1 2 697 1336 H 0 0 1 0 3 697 1477 H 0 0 1 1 4 770 1209 H 0 1 0 0 5 770 1336 H 0 1 0 1 6 770 1477 H 0 1 1 0 7 852 1209 H 0 1 1 1 8 852 1336 H 1 0 0 0 9 852 1477 H 1 0 0 1 0 941 1336 H 1 0 1 0 * 941 1209 H 1 0 1 1 # 941 1477 H 1 1 0 0 A 697 1633 H 1 1 0 1 B 770 1633 H 1 1 1 0 C 852 1633 H 1 1 1 1 D 941 1633 H 0 0 0 0 ANY - - L Z Z Z Z Z : High Impedance H : High Logic Level L : Low Logic Level KT3170 LOW POWER DTMF RECEIVER APPLICATION CIRCUIT 0.1uF IN+ V DD IN- SI/GTO 0.1uF +5V 100K 100K GS ESO VREF DSO IIN Q4 PDN Q3 10nF 100K C1 10nF 100K R2 3.58MHz Q2 OSC2 Q1 GND OE 1 + R1 INGS C2 OSC1 IN+ 300K R5 R3 37.5K R2 60K _ 2 3 100K VREF KT3170 4 R3 = R2R5/(R2+R5), VOLTAGE GAIN = R5/R1 2 2 INPUT IMPEDANCE : 2 √R1 + (1/wC) All resistors are 1% tolerance All capacitors are 5% tolerance All resistors are 1% tolerance All capacitors are 5% tolerance Fig. 4 Single Ended Input Configuration Fig. 5 Differential Ended Input Configuration VDD C C SI/GTO SI/GTO R1 R1 R2 R2 ESO ESO tPGT = (R1C) In (VDD/VDD-VTH) tAGT = (RPC) In (VDD/VTST) RP = R1R2/(R1 + R2) (a) Decreasing tAGT (tPGT > tAGT) tPGT = (RPC) In (VDD/VDD-VTH) tAGT = (R1C) In (VDD/VTH) RP = R1R2 (R1 + R2) (a) Decreasing tPGT (tPGT< tAGT) Fig. 6 Guard Time Adjustment KT3170 KT3170 30pF OSC1 OSC1 3.579545MH z OSC2 OSC2 T O O S C 1 o f n ex t K T 3 1 7 0 Fig. 7 Oscillator Connection