10 CH PLL S5T8803A INTRODUCTION The S5T8803A is designed to select 10 channels of a cordless phone, whose frequency band is 46/49MHz. It has a reference frequency generator, programmable divider for Transmit and Receive section, and phase detector. 16−DIP−300A FEATURES • Able to select 10 Channels: S5T8803A (both transmit/receive) • Include oscillation circuit with external x-tal (10.24MHz) • 5KHz output for guard tone • Unlock detector (phase difference more than 6.25us) • Standby function for power saving 16−SOP−225 ORDERING INFORMATION Device Package S5T8803A01-D0B0 16−DIP−300A S5T8803A01-S0B0 16−SOP−225 Operating Temperature −30°C to +75°C 1 S5T8803A 10 CH PLL BLOCK DIAGRAM OSCI 16 OSCO 1 PDT 11 TIF 9 VDD VSS 15 12 + VDD 4 F1 REFERENCE DIVIDER PHASE DETECTOR (Tx) PHASE DETECTOR (Rx) PROGRAMMABLE DIVIDER (Tx) PROGRAMMABLE DIVIDER (Rx) 13 PDR 14 RIF 10 LDT + UNLOCK DETECTOR DECODER 3 5 6 7 8 2 SB D0 D1 D2 D3 MODE PIN CONFIGURATION OSCO 1 16 OSCI MODE 2 15 VDD SB 3 14 RIF F1 4 13 PDR D0 5 12 VSS D1 6 11 PDT D2 7 10 LDT D3 8 9 TIF S5T8803A 2 10 CH PLL S5T8803A PIN DESCRIPTION Pin No Symbol Description 1 OSCO This output generates the reference frequency when it is connected to Pin 16 with the external OSC, whose frequency is 10.24MHz. 2 MODE Base/Remote Unit Selection Pin. “High”: Base Unit “Low” : Remote Unit 3 SB Standby pin. This input controls Tx PLL for reducing the power dissipation “High”: Normal operation “Low”: Standby 4 F1 5KHz output 5, 6 7, 8 D0, D1 D2, D3 9 TIF Input to programmable divider of Tx. AC coupling with VCO In case of a larger signal, It needs DC−coupling. Minimum input voltage is 0.1 Vrms 10 LDT Unlocked signal out pin (see output characteristics) 11 PDT Phase detector output for Tx. PDT detects the phase error from Tx PLL and its output is connected to the external low pass filter 12 VSS This pin is the negative supply of the IC. It is usually grounded 13 PDR Phase detector output for Rx. PDR detects the phase error from Rx PLL and its output is connected to the external low pass filter 14 RIF Input of programmable divider for Rx. AC coupling with VCO In case of a larger signal (standard CMOS logic), it needs DC coupling. Minimum input voltage is 0.1Vrms 15 VDD This pin is the positive supply of the IC Its reference is VSS, and normally + 3.0V ~ + 5.5V more positive than VSS 16 OSCI Channel selection pins The Combinations of these inputs select one channel among the 10 channels X-TAL OSC connection pin This input generates the reference frequency when it is connected to pin 1 with the external OSC ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Value Unit VDD −0.5 ~ +6.0 V Input Voltage VI −0.3 ~ VDD + 0.5 V Power Dissipation PD 350 mW Operating Temperature TOPR −30 ~ + 75 °C Storage Temperature TSTG −40 ~ + 125 °C Supply voltage 3 S5T8803A 10 CH PLL ELECTRICAL CHARACTERISTICS (Ta = 25°C, VDD = 5 V, unless otherwise specified) Characteristic Symbol Test Conditions Min. Typ. Max. Unit − 3 − 5.5 V Supply Voltage VDD Input Voltage VIH1 D0 - D3, SB 0.7 VDD − VDD V VIL1 D0 - D3, SB − − 0.3VDD V VIH2 MODE 0.9 VDD − VDD V VIL2 MODE − − 0.1VDD V fI1 VTIF = 0.15Vrms 10 − 52 MHz fl2 VRIF = 0.15Vrms 30 − 42 MHz fI3 OSCIN = 0.3Vrms 5 10.24 11 MHz VI(AMP)1 fTIF = 52MHz 0.1 − 0.3VDD Vrms VI(AMP)2 fRIF = 42MHz 0.1 − 0.3VDD Vrms VI(AMP)3 OSCIN = 11MHz 0.3 − 0.3VDD Vrms IIH VIN = VDD − − 40 µA IIL VIN = VSS − − 40 µA VOH1 PDT, RDR: IO = 0.5mA VDD-1.0 − − V VOL1 PDT, RDR : IO = 0.5mA − − 1.0 V VOH2 LDT: IO = 1mA VDD-1.0 − − V VOL2 F1: IO = 1mA − − 1.0 V Output OFF Leakage Current ILKG1 PDT, PDR : VO = VDD/VSS − 0.01 1.0 µA ILKG2 LDT: VO = VSS − − 5.0 µA Standby Current ISB1 VDD = 3V (Note 2) − 1.0 2.0 mA ISB2 VDD = 3V (Note 2) 3.5 4.0 − mA IDD1 VDD = 3V (Note 1) − 2.0 3.0 mA IDD2 VDD = 5V (Note 1) − 6.0 7.0 mA Input Frequency Input Amplitude Input Current Output Voltage Operating Current NOTES: 1. OSC IN: 10.24MHz X-tal Connection TIF: 27MHz 150 mVrms RlF: 42MHz 150 mVrrns MODE: VDD, SB = VDD, others are opened 2. OSC IN: 10.24MHz X-tal Connection TlF: 27MHz 150rnVrms RIF: 42MHz 150mVrms MODE: VDD, SB = VSS, others are opened Capacitor more than 2000pF should be connected between VDD & VSS 4 10 CH PLL S5T8803A OUTPUT CHARACTERISTICS LOCK tPD tPD tPD : Phase Difference ( 6.25µs ) Reference Divider VDD VSS VDD Programmable Divider VSS LDT Floating 2) UNLOCK VDD Reference Divider VSS VDD Programmable Divider VSS 6.4ms LDT VDD Floating Figure 1. 5 S5T8803A 10 CH PLL Channel & Frequency table to Base/Remote Input Data for S5T8803A (10-CH) BASE (MODE = 1) INPUT D0 D1 D2 D3 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 Rx (fREF = 5kHz) Tx (fREF = 5kHz) CH fRX(MHz) fVCO(MHz) N fTX(MHz) fVCO(MHz) N 1 2 3 4 5 6 7 8 9 10 10 10 10 10 10 10 49.670 49.845 49.860 49.770 49.875 49.830 49.890 49.930 49.990 49.970 49.970 49.970 49.970 49.970 49.970 49.970 38.975 39.150 39.165 39.075 39.180 39.135 39.195 39.235 39.295 39.275 39.275 39.275 39.275 39.275 39.275 39.275 7795 7830 7833 7815 7836 7827 7839 7847 7859 7855 7855 7855 7855 7855 7855 7855 46.610 46.630 46.670 46.710 46.730 46.770 46.830 46.870 46.930 46.970 46.970 46.970 46.970 46.970 46.970 46.970 46.610 46.630 46.670 46.710 46.730 46.770 46.830 46.870 46.930 46.970 46.970 46.970 46.970 46.970 46.970 46.970 9322 9326 9334 9342 9346 9354 9366 9374 9386 9394 9394 9394 9394 9394 9394 9394 REMOTE (MODE = 0) INPUT D0 D1 D2 D3 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 6 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 Rx (fREF = 5kHz) Tx (fREF = 5kHz) CH fRX(MHz) fVCO(MHz) N fRX(MHz) fVCO(MHz) N 1 2 3 4 5 6 7 8 9 10 10 10 10 10 10 10 46.610 46.630 46.670 46.710 46.730 46.770 46.830 46.870 46.930 46.970 46.970 46.970 46.970 46.970 46.970 46.970 35.915 35.935 35.975 36.015 36.035 36.075 36.135 36.175 36.235 36.275 36.275 36.275 36.275 36.275 36.275 36.275 7183 7187 7195 7203 7207 7215 7227 7235 7247 7255 7555 7255 7255 7255 7255 7255 49.670 49.845 49.860 49.770 49.875 49.830 49.890 49.930 49.990 49.970 49.970 49.970 49.970 49.970 49.970 49.970 49.670 49.845 49.860 49.770 49.875 49.830 49.890 49.930 49.990 49.970 49.970 49.970 49.970 49.970 49.970 49.970 9934 9969 9972 9954 9975 9966 9978 9986 9998 9994 9994 9994 9994 9994 9994 9994 10 CH PLL S5T8803A APPLICATION CIRCUIT ANT BPF BPF 46.610MHz (R) 49.670MHz (B) 1st 10.695MHz MIX 2nd MIX 455KHz 10.24MHz 49.670MHz (R) 46.610MHz (B) 39.915MHz 38.975MHz (B) (R) : REMOTE UNIT (B) : BASE UNIT RX VCO Tx VCO VDD 16 to MICOM (Unlock Detect) 15 14 PROGRAMMABLE DIVIDER (Rx) 13 12 11 10 9 PHASE DETECTOR (Tx) PHASE DETECTOR (Rx) PROGRAMMABLE DIVIDER (Tx) REF. DIVIDER DECODER 1 2 3 4 5 7 8 to MICOM (D0, D1, D2, D3) X-TAL 10.24MHz VDD 6 5.0KHz BASE VDD : TX PLL ENABLE VSS : TX PLL DISABLE REMOTE 7 S5T8803A 10 CH PLL NOTES 8