PLL FREQUENCY SHNTHESIZER FOR PAGER INTRODUCTION S5T8808 16−SSOP−0044 S5T8808 is a superior low-power-programmable PLL frequency synthesizer which can be used in a high performance Wide Area Pager system. KS8808 consists of 2 kinds of divider block including a 17-bit Shift register, 16-bit Latch, 14/16-bits Counter, Prescaler, and a phase detector block including a Phase detector, Lock detector and a Charge pump. (Magnification = 1 : 4) FEATURES • Maximum operating frequency: 150MHz @ 500mVP-P, VDD1 = 0.95V 180MHz @ 500mVP-P, VDD1 = 1.0V • On-chip reference oscillator supports external crystal which oscillates up to 18MHz • Superior supply current: (VDD1 = VDD2 = 1.0V, VDD3 = 3.0V) — FFIN = 90MHz, IDD1 = 0.6mA (Typ.) — FFIN = 150MHz, IDD1 = 0.9mA (Typ.) — FFIN = 180MHz, IDD3 = 1.1mA (TyP.) • Operating voltage: VDD1 = 0.95 ~ 2.0V and VDD2 = 0.95V ~ 2.0V and VDD3 = 2.0V ~ 3.3V • Reference frequency counter divider range: 1 / 28 ~ 1 / 65532 (Multiple 4) But, the Divider range with FRC_High state: 1 / 7 ~ 1 / 16383 • RX frequency counter divider range: 1 / 28 ~ 1 / 65535 • Package type: 16-SSOP (0.8mm) ORDERING INFORMATION Device Package Operating Temperature S5T8808X01-V0B0 16−SSOP−0044 −25°C to +75°C 1 S5T8808 PLL FREQUENCY SHNTHESIZER FOR PAGE BLOCK DIAGRAM VDD 2 FRC VDD1 VDD3 NC 16 Lock Detector 14 ¡ Ü FnFr ¢ º15 Fr ¢ º10 LDT 16-Bit Latch ¢º VDD3 3 ¡ Ü ¢º 2 14-Bit Divider ( R - counter ) ¡ Ü ¢º OSCO ¡ Ü Amp ¢º 1 ¢º OSCI ¢º 16 Phase Detector EN CLK ¢º Schmitt Trigger 13 ¢ º ¢ º 12 ¢ º ¢ º 11 ¢ º ¢ º Shift Register * 17- Bit ¢ º4 PDA ¢ º5 PDP Charge Pump 16 ¢º VSS 6 16-Bit Latch 16 FnFr ¢º 9 VDD2 ¢º 2 Fin 7 VDD1 8 ¡ Ü VDD1 Amp ¡ Ü 16-Bit Divider ( N - counter ) ¢ º 14 VDD2 Fn PLL FREQUENCY SHNTHESIZER FOR PAGER S5T8808 PIN CONFIGURATION OSCI 1 16 NC OSCO 2 15 Fr VDD3 3 14 Fn PDA 4 13 EN PDP 5 12 DATA VSS 6 11 CLK Fin 7 10 LDT VDD1 8 9 VDD2 S5T8808 KS8808D 3 S5T8808 PLL FREQUENCY SHNTHESIZER FOR PAGE PIN DESCRIPTION Pin No Symbol I/O Description 1 OSCI I 2 OSCO O These input / output pins generate the reference frequency. In case of an OSCI pin, external reference frequency can be input through an AC coupling. 3 VDD3 − The highest potential supply terminal that can be supplied up to 2.0V ~ 3.3V, except for VDD1 and VDD2. 4 PDA O The Output of RX Phase detector terminal for active loop filter. There are 3-kinds of output signal states according to Rx Loop Error − If Fr < Fn (Fr is leading), the output negative pulse state − If Fr > Fn (Fr is lagging), the output positive pulse state − If Fr = Fn (the same phase), the output is high impedance state 5 PDP O The Output of RX Phase detector terminal for active loop filter. There are 3-kinds of output signal states according to Rx Loop Error − If Fr < Fn (Fr is lagging), the output negative pulse state − If Fr > Fn (Fr is leading), the output positive pulse state − If Fr = Fn (the same phase), the output is high impedance state 6 VSS − Ground terminal 7 Fin I Input terminal for 16-bit Divider from VCO. Mostly, VCO output should be input through an AC coupling and the minimum input level is 500mVP-P (in case of 90MHz) 8 VDD1 I Voltage supply terminal for Oscillator and Fin block. This pin can be supplied up to 0.95 ~ 2.0V from VSS. 9 VDD2 I Voltage supply terminal for each Divider block (N & R counter). This pin can be supplied up to 0.95V ~ 2.0V. 10 LDT O Lock detector is also an output of the Phase Detector. The Low state of this output shows the unlock status, which is the error width between the Ref. signal and the VCO output signal. 11 CLK I 12 DATA I 13 EN I These pins are controlled by µ-controller and it also has Schmitt Trigger architecture. The features of these pins are as follows; Clock input for 17-bit Shift Register, Serial data input (it include FnFr-on / off and FRC), Latch enable input (User selectable EN1 or EN2) 14 Fn O Output terminal for divider value of N-counter. To control the output On/Off, the FnFr bit of the Reference register can be programmed. When FnFr bit set to High, this output shows low level. 15 Fr O Output terminal for divider value of N-counter. To control the output On/Off, the FnFr bit of Reference register can be programmed. When FnFr bit set to High, this output shows low level. 16 NC − No Connection. (Internally biased Pull-up) 4 PLL FREQUENCY SHNTHESIZER FOR PAGER S5T8808 ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Value Unit VDD ~ VDD2 −0.3 ~ +4.0 V Input Voltage VI VSS - 0.3 ~ VDD + 0.3 V Power Dissipation PD 350 mW Operating Temperature TOPR −25 ~ +75 °C Storage Temperature TSTG −40 ~ +125 °C Supply Voltage ELECTRICAL CHARACTERISTICS (Ta = 25°C, VDD1 = VDD2 = 1.0V, VDD3 = 3.0V, unless otherwise specified) Characteristic Operating voltage Operating current Symbol Test Conditions Min. Typ. Max. Unit VDD1 − 0.95 1.0 2.0 V VDD2 − 2.0 3.0 3.3 FFIN = 90MHz − 0.6 − FFIN = 150MHz − 0.9 − FFIN = 180MHz − 1.1 − − − 10 µA V IDD1 IDD3 FOSCI = 12.8MHz @ 0.5VP-P VDD1 = VDD2 = 1.0V VDD3 = 1.0V Standby current ISB VDD1 = VDD2 = 0V, VDD2 = 3.0V Input Voltage (DATA, CLK, EN, BS) VIL − − − 0.3 VIH − VDD3-0.3 − − Input current (Fin, Xin) VIH VIH = VDD1 − − 20 VIL VIL = 0V − − 20 FFIN FFIN = 0.5VP-P VDD1 = 0.95V − − 150 VDD1 = 1.0V − − 180 7 − 18 IDD2 Input frequency mA µA MHz FOSCI VOSCI = 0.5VP-P Output current (PDA, PDP) IOH1 VOH = 0.4V 1.0 − − IOL1 VOL = VDD1 − 0.4V 1.0 − − Output current (Fr, Fn, LDT) IOH2 VOH = 0.4V 0.1 − − IOL2 VOL = VDD1 − 0.4V 0.1 − − Setup-time (DATA-CLK, CLK-EN) ts − 2 − − µS Hold time tH − 2 − − µS mA mA 5 S5T8808 PLL FREQUENCY SHNTHESIZER FOR PAGE FUNCTIONAL DESCTRIPTION Table 1. Rx Register (17 bits) Bit Bit 16 (ND 15) ~ Bit 1 (ND 0) Bit 0 (LSB) Name RxD PMC Description Rx. Program Data (ND 15 ~ ND 0) Program Mode Control Function 16 Bit Programmable Rx. N-Counter Data 0: Rx. N-Counter 1: Ref. R-Counter Table 2. Reference Register (17 bits) Bit Bit 16 (RD 13) ~ Bit 3 (RD 0) Name RefD Description Ref. Program Data (RD 13 ~ RD 0) Function 14 Bit Programmable Ref. R-Counter Bit 2 Bit 1 FRC Bit 0 (LSB) FnFr PMC Control Mode 0: No FRC (OSCI/4R) 1: FRC (OSCI/R) Program mode control 0: Fn, Fr function 1: Fn, Fr Low 0: Rx. N-Counter 1: Ref. R-Counter Table 3. Control Mode 6 FRC FnFr Fn (Pin 14) Fr (Pin 15) 0 0 Fn out (Fin / N counter) Fr out (OSCI / 4 x R) 0 1 LOW LOW 1 0 Fn out (Fin / N-counter) Fr out (OSCI / R) 1 1 LOW LOW PLL FREQUENCY SHNTHESIZER FOR PAGER S5T8808 PMC = 0 → 16-bit N_Counter PMC Rx.16Bit N_Counter Data ( ND15 ~ ND0 ) DATA MSB 1 LSB 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK positive edge triggered EN1 or EN2 Figure 1. Rx. Register Programming Timing PMC = 1 → 14-bit R_Counter, FRC, FnFr FRC FnFr PMC Ref .14Bit R_Counter Data ( RD13 ~ RD0 ) DATA MSB 1 LSB 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK positive edge triggered EN1 or EN2 Figure 2. Ref. Register Programming Timing • It is possible to use an optional selection of EN1, EN2 (when used EN) 7 S5T8808 PLL FREQUENCY SHNTHESIZER FOR PAGE ~ ~ Serial DATA Input Timing & Phase Detector / Lock Detector Output Waveforms ~ ~ DATA º ¢ ¢ º ¢ º tH ~ ~ tsu º ¢ 50% CLK º ¢ ¢ º EN 1 50% ~ ~ tsu Figure 3. Serial Data Input Timing The architecture of R-Count Divider OSCI OSCO Fin ÷4 14Bit Ref. Prog. Div. Fr Phase Detector FRC 16Bit Rx. Prog. Div. PDP LDT Fn Figure 4. Phase Detector / Lock Detector Block Diagram 8 PDA PLL FREQUENCY SHNTHESIZER FOR PAGER S5T8808 Fr Fn PDP PDA LDT Figure 5. Phase Detector / Lock Detector Output Waveforms 9 S5T8808 PLL FREQUENCY SHNTHESIZER FOR PAGE APPLICATION CIRCUIT From Antenna 1st MIXer X To IF IC S5T8808 KS8808D Multiplier 3V VCO 10 1 OSCI NC 16 2 OSCO Fr 15 Monitoring 3 VDD3 Fn 14 Monitoring 4 PDA EN 13 5 PDP DATA 12 6 Vss CLK 11 7 Fin LDT 10 8 VDD1 VDD2 9 MICOM Monitoring 1V