FUJITSU MB15E03

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21340-2E
ASSP
Single Serial Input
PLL Frequency Synthesizer
On-Chip 1.2 GHz Prescaler
MB15E03
■ DESCRIPTION
The Fujitsu MB15E03 is serial input Phase Locked Loop (PLL) frequency synthesizer with a 1.2 GHz prescaler. A
64/65 or a 128/129 can be selected for the prescaler that enables pulse swallow operation.
The latest BiCMOS process technology is used, resuItantly a supply current is limited as low as 3.5 mA typ. This
operates with a supply voltage of 3.0 V (typ.).
Furthermore, a super charger circuit is included to get a fast tuning as well as low noise performance. As a result
of this, MB15E03 is ideally suitable for digital mobile communications, such as GSM (Global System for Mobile
Communications).
■ FEATURES
•
•
•
•
•
•
•
High frequency operation: 1.2 GHz max
Low power supply voltage: VCC = 2.7 to 3.6 V
Very Low power supply current : ICC = 3.5 mA typ. (VCC = 3 V)
Power saving function : IPS = 0.1 µA typ.
Pulse swallow function: 64/65 or 128/129
Serial input 14-bit programmable reference divider: R = 5 to 16,383
Serial input 18-bit programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 5 to 2,047
• Wide operating temperature: Ta = –40 to 85°C
• Plastic 16-pin SSOP package (FPT-16P-M05) and 16-pin BCC package (LCC-16P-M02)
■ PACKAGES
16-pin, Plastic SSOP
16-pin, Plastic BCC
(FPT-16P-M05)
(LCC-16P-M02)
This device contains circuitry to protect the inputs against damage due to high static voltages or electroc fields. However, it is advised that normal precautions
be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
MB15E03
■ PIN ASSIGNMENTS
SSOP-16 pin
OSCin
1
16
φR
OSCout
2
15
φP
Vp
3
14
LD/fout
Vcc
4
TOP 13
VIEW
5
12
ZC
GND
6
11
LE
Xfin
7
10
Data
fin
8
9
Clock
Do
PS
(FPT-16P-M05)
BCC-16 pin
φR
OSCin
OSCout
1
VP
2
VCC
3
Do
4
GND
5
Xfin
6
16
15
TOP
VIEW
7
8
fin
Clock
(LCC-16P-M02)
2
14
φP
13
LD/fout
12
ZC
11
PS
10
LE
9
Data
MB15E03
■ PIN DESCRIPTIONS
Pin no.
SSOP
BCC
Pin
name
I/O
Descriptions
1
16
OSCIN
I
Programmable reference divider input.
Oscillator input.
Connection for an crystal or a TCXO.
TCXO should be connected with a coupling capacitor.
2
1
OSCOUT
O
Oscillator output.
Connection for an external crystal.
3
2
VP
–
Power supply voltage input for the charge pump.
4
3
VCC
–
Power supply voltage input.
5
4
DO
O
Charge pump output.
Phase of the charge pump can be reversed by FC bit.
6
5
GND
–
Ground.
7
6
Xfin
I
Prescaler complementary input, and should be grounded via a
capacitor.
8
7
fin
I
Prescaler input.
Connection with an external VCO should be done with AC coupling.
9
8
Clock
I
Clock input for the 19-bit shift register.
Data is shifted into the shift register on the rising edge of the clock.
(Open is prohibited.)
10
9
Data
I
Serial data input using binary code.
The last bit of the data is a control bit. (Open is prohibited.)
Control bit = ”H” ; Data is transmitted to the programmable
reference
counter.
Control bit = ”L” ; Data is transmitted to the programmable
counter.
11
10
LE
I
Load enable signal input (Open is prohibited.)
When LE is high, the data in the shift register is transferred to a
latch, according to the control bit in the serial data.
I
Power saving mode control. This pin must be set at ”L” at PowerON.
(Open is prohibited.)
PS = ”H” ; Normal mode
PS = ”L” ; Power saving mode
I
Forced high-impedance control for the charge pump (with internal
pull up resistor.)
ZC = ”H” ; Normal Do output.
ZC = ”L” ; Do becomes high impedance.
12
13
11
12
PS
ZC
14
13
LD/fout
O
Lock detect signal output(LD)/phase comparator monitoring
output (fout).
The output signal is selected by LDS bit in the serial data.
LDS = ”H” ; outputs fout (fr/fp monitoring output)
LDS = ”L” ; outputs LD (”H” at locking, ”L” at unlocking.)
15
14
φP
O
Phase comparator output for an external charge pump. Nch open
drain output.
16
15
φR
O
Phase comparator output for an external charge pump. CMOS
output.
3
MB15E03
■ BLOCK DIAGRAM
OSCIN 1
fr
Crystal
Oscillator
circuit
fp
Programmable
reference divider
OSCOUT 2
Lock
detector
fr
Intermittent
mode control
(power save)
16 φR
15 φP
LD
Binary 14-bit
reference counter
PS 12
Phase
comparator
SW
LDS
17-bit latch
FC
14-bit latch
LD/fr/fp
selector
3-bit latch
LE
14 LD/fout
fp
LE 11
1-bit
control
latch
19-bit shift register
C
N
T
Data 10
Charge
pump
19-bit shift register
3 VP
Super
charger
Clock 9
LE
18-bit latch
7-bit latch
11-bit latch
SW
Programmable divider
XfIN 7
fIN 8
Prescaler
64/65,
128/129
Binary 7-bit
swallow
counter
Binary 11-bit
programmable counter
GND 6
VCC 4
Note: SSOP-16 pin
4
MD
13 ZC
Control Cir-
fp
5 DO
MB15E03
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
VCC
–0.5 to +4.0
V
VP
VCC to +6.0
V
Input voltage
VI
–0.5 to VCC +0.5
V
Output voltage
VO
–0.5 to VCC +0.5
V
Storage temperature
Tstg
–55 to +125
°C
Power supply voltage
Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Min.
Typ.
Max.
VCC
2.7
3.0
3.6
V
VP
VCC
–
6.0
V
Input voltage
VI
GND
–
VCC
V
Operating temperature
Ta
–40
–
+85
°C
Power supply voltage
Remark
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always yse semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with repect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
5
MB15E03
■ ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
Power supply current*1
ICC
fin = 1200 MHz,
fosc = 12 MHz
–
3.5
–
mA
Power saving current
Ips
PS = “L”, ZC = ”H” or open
–
0.1*2
10
µA
Operating frequency
fin
100
–
1200
MHz
Crystal oscillator operating frequency
fOSC
min. 500 mVp-p
3
–
40
MHz
fin
Vfin
50 Ω system
(Refer to the test circuit.)
–10
–
+2
dBm
OSCin
VOSC
500
–
VCC
mVp-p
Data, Clock,
LE, PS, ZC
VIH
Vcc × 0.7
–
–
VIL
–
–
Vcc × 0.3
Data, Clock,
LE, PS
IIH
–1.0
–
+1.0
IIL
–1.0
–
+1.0
IIH
–1.0
–
+1.0
–100
–
0
IIH
0
–
+100
IIL
–100
–
0
–
–
0.4
Vcc – 0.4
–
–
–
–
0.4
Vp – 0.4
–
–
Input sensitivity
Input voltage
Input current
ZC
OSCin
Output voltage
High impedance
cutoff current
IIL
Pull up input
V
µA
µA
µA
φP
VOL
Open drain output
φR,
LD/fout
VOH
VCC = 3 V, IOH = –1 mA
VOL
VCC = 3 V, IOL = 1 mA
VDOH
VCC = 3 V, IDOH = –1 mA
VDOL
VCC = 3 V, IDOL = 1 mA
–
–
0.4
Do
IOFF
VCC = 3 V, Vp = 6 V
Voop = GND to 6 V
–
–
1.1
µA
φP
IOL
1.0
–
–
mA
φR,
LD/fout
IOH
–
–
–1.0
IOL
1.0
–
–
IDOH
VCC = 3.0 V,
Vp = 5 V,
VDOH = 4.0 V
Ta = 25°C
–
–10.0
–
IDOL
VCC = 3.0 V,
Vp = 5 V,
VDOL = 1.0 V
Ta = 25°C
–
Do
Output current
Do
*1: Conditions; VCC = 3.0 V, Ta = 25°C, in locking state.
*2: Conditions; VCC = 3.0 V, Ta = 25°C, fOSC = 12 MHz (–2 dB)
6
(VCC = 2.7 to 3.6 V, Ta = –40 to +85°C)
Value
Unit
Min.
Typ.
Max.
V
V
V
mA
mA
10.0
–
MB15E03
■ FUNCTION DESCRIPTIONS
Pulse Swallow Function
The divide ratio can be calculated using the following equation:
fVCO = [(M x N) + A] x fOSC ÷ R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
N
: Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
A
: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
fOSC : Output frequency of the reference frequency oscillator
R
: Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
M
: Preset divide ratio of modules prescaler (64 or 128)
Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the clock. When the load enable pin is high,
stored data is latched according to the control bit data as follows:
Table.1 Control Bit
Control bit (CNT)
Destination of serial data
H
17 bit latch (for the programmable reference divider)
L
18 bit latch (for the programmable divider)
Shift Register Configuration
Programmable Reference Counter
MS
Data
LS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
C
N
T
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
R
14 SW FC LDS
16
CNT : Control bit
R1 to R14: Divide ratio setting bit for the programmable reference counter (5 to 16,383)
SW : Divide ratio setting bit for the prescaler (64/65 or 128/129)
FC : Phase control bit for the phase comparator
LDS : LD/fout signal select bit
17
18
[Table. 1]
[Table. 2]
[Table. 5]
[Table. 7]
[Table. 6]
Note: Start data input with MSB first
7
MB15E03
Programmable Reference Counter
MS
Data
LS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C
N
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
10
N
11
T
CNT: Control bit
N1 to N11: Divide ratio setting bits for the programmable counter (5 to 2,047)
A1 to A7: Divide ratio setting bits for the swallow counter (0 to 127)
[Table. 1]
[Table. 3]
[Table. 4]
Note: Start data input with MSB first
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide
ratio
(R)
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
5
0
0
0
0
0
0
0
0
0
0
0
1
0
1
6
0
0
0
0
0
0
0
0
0
0
0
1
1
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 5 is prohibited.
Table.3 Binary 11-bit Programmable Counter Data Setting
Divide
ratio
(N)
N
11
N
10
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
5
0
0
0
0
0
0
0
0
1
0
1
6
0
0
0
0
0
0
0
0
1
1
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
2047
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 5 is prohibited.
• Divide ratio (N) range = 5 to 2,047
8
MB15E03
Table.4 Binary 7-bit Swallow Counter Data Setting
Divide
ratio
(A)
A
7
A
6
A
5
A
4
A
3
A
2
A
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
127
1
1
1
1
1
1
1
Note: • Divide ratio (A) range = 0 to 127
Table. 5 Prescaler Data Setting
SW
Prescaler Divide ratio
H
64/65
L
128/129
Table. 6 LD/fout Output Select Data Setting
LDS
LD/fout output signal
H
fout signal
L
LD signal
Relation between the FC input and phase characteristics
The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output level
(DO) and the phase comparator output (φR, φP) are reversed according to the FC bit. Also, the monitor pin (fOUT)
output is controlled by the FC bit. The relationship between the FC bit and each of DO, φR, and φP is shown below.
Table. 7 FC Bit Data Setting (LDS = ”H”)
FC = High
FC = Low
Do
φR
φP
LD/fout
Do
φR
φP
LD/fout
fr > fp
H
L
L
(fr)
L
H
Z*
(fp)
fr < fp
L
H
Z*
(fr)
H
L
L
(fp)
fr = fp
Z*
L
Z*
(fr)
Z*
L
Z*
(fp)
* : High impedance
9
MB15E03
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
∗: When the LPF and VCO characteristics are
(1)
similar to (1), set FC bit high.
∗: When the VCO characteristics are similar to
(2), set FC bit low.
VCO
Output
Frequency
PLL
LPF
VC
(2)
LPF Input Voltage
Power Saving Mode (Intermittent Mode Control Circuit)
Setting a PS pin to Low, the IC enters into power saving mode resultatly current sonsumption can be limited to
10µA (max.). Setting PS pin to High, power saving mode is released so that the IC works normally.
In addition, the intermittent operation control circuit is included which helps smooth start up from the power saving
mode. In general, the power consumption can be saved by the intermittent operation that powering down or waking
up the synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator output signal
is unpredictable due to an undefined phase relation between reference frequency (fr) and comparison frequency
(fp) and may in the worst case take longer time for lock up of the loop.
To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector
during power up, thus keeping the loop locked.
During the power saving mode, the corresponding section except for indispensable circuit for the power saving
function stops working, then current consumption is reduced to 10 µA (max.).
At that time, the Do and LD become the same state as when a loop is locking. That is, the Do becomes high
impedance.
A VCO control voltage is naturally kept at the locking voltage which defined by a LPF”s time constant. As a result
of this, VCO’s frequency is kept at the locking frequency.
Note: • While the power saving mode is executed, ZC pin should be set at ”H” or open. If ZC is set at ”L”
during power saving mode, approximately 10 µA current flows.
• PS pin must be set ”L” at Power-ON.
• The power saving mode can be released (PS : L → H) 1µs later after power supply remains stable.
• During the power saving mode, it is possible to input the serial data.
Table.8 PS Pin Setting
PS pin
10
Status
H
Normal mode
L
Power saving mode
MB15E03
ON
V
CC
Clock
Data
LE
PS
i1j
i2j
i3j
(1) PS = L (power saving mode) at Power-ON.
(2) Set serial data after power supply remains stable.
(3) Release saving mode (PS: LfiH) after setting serial data.
Table.9 ZC Pin Setting
ZC pin
Do output
H
Normal output
L
High impedance
11
MB15E03
■ SERIAL DATA INPUT TIMING
Data
MSB
LSB
Clock
LE
t2
t4
t3
t1
t5
t7
t6
On rising edge of the clock, one bit of the data is transferred into the shift register.
12
Parameter
Min.
t1
20
t2
Typ.
Max.
Unit
Parameter
–
–
ns
t5
100
20
–
–
ns
t6
t3
30
–
–
ns
t7
t4
30
–
–
ns
Min.
Typ.
Max.
Unit
–
–
ns
20
–
–
ns
100
–
–
ns
MB15E03
■ PHASE COMPARATOR OUTPUT WAVEFORM
fr
fp
tWU
tWL
LD
[ FC = ”H” ]
φP
φR
H
Do
Z
L
[ FC = ”L” ]
φP
φR
H
Do
L
Z
Notes: 1. Phase error detection range: –2π to +2π
2. Pulses on Do output signal during locked state are output to prevent dead zone.
3. LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL
or less and continues to be so for three cysles or more.
4. tWU and tWL depend on OSCin input frequency.
tWU > 8/fosc (e. g. tWU > 625ns, foscin = 12.8 MHz)
tWL < 16/fosc (e. g. tWL < 1250ns, foscin = 12.8 MHz)
5. LD becomes high during the power saving mode (PS = ”L”.)
13
MB15E03
■ TEST CIRCUIT (FOR MEASURING INPUT SENSITIVITY FIN/OSCIN)
VCC
VP
0.1µF
1000pF
1000pF
P•G
P•G
0.1µF
50 Ω
1000pF
8 7 6 5 4 3 2 1
50 Ω
9 10 11 12 13 14 15 16
Oscilloscope
Controller
(setting divide ratio)
Note: SSOP-16 pin
14
Vcc
MB15E03
■ APPLICATION EXAMPLE
Output
LPF
VCO
10kΩ
12kΩ
To a lock detect.
12kΩ
φR
16
φP
15
10kΩ
From
a controller
LD/FOUT ZC
14
PS
13
12
LE
Data
Clock
11
10
9
6
7
8
MB15E03
1
2
3
OSCIN OSCOUT
4
VP
5
VCC
DO
GND
XfIN
1000pF
X’ tal
C1
fIN
1000pF
C2
0.1µF 0.1µF
C1, C2
:
Depend on the crystal parameters
Note: SSOP-16 pin
15
MB15E03
■ TYPICAL CHARACTERISTICS
Do Output Current
[Ta = +25°C]
[VCC = 3 V, Vp =3 V, 5 V]
Vp = 3 V
5.0
4.0
4.0
3.0
3.0
2.0
1.0
Vp = 3 V
5.0
Vp = 5 V
VOL (V)
VOH (V)
[Ta = +25°C]
[VCC = 3 V, Vp =3 V, 5 V]
Vp = 5 V
2.0
1.0
0
0
–5
0
–10
IOH (mA)
–15
–20
0
fin Input Sensitivity
5
10
IOL (mA)
15
20
Main. counter div. ratio = 4104
Swallow="ON"
VCC = Vp
Xfin = 1000 pF pull down
[Ta = +25°C]
+10
0
Vfin (dBm)
SPEC
–10
–20
VCC=2.7 V
–30
VCC=3.0 V
VCC=3.6 V
–40
0
500
OSCin Input Characteristics
1000
fin (MHz)
1500
2000
Ref. counter div. ratio = 2048
VCC = Vp
fin = 1.2 GHz (–10 dBm)
[Ta = +25°C]
+10
SPEC
Vfosc (dBm)
0
–10
–20
VCC=2.7 V
VCC=3.0 V
–30
VCC=3.6 V
–40
0
50
100
fosc (MHz)
150
200
(Continued)
16
MB15E03
(Continued)
fin Input Impedance
4: 9.0039 Ω
–19.444 Ω 6.821 pF
1 200.000 000 MHz
1:
fin
232.63 Ω
–556.66 Ω
100 MHz
2:
22.031 Ω
–150.96 Ω
400 MHz
3:
9.8965 Ω
–59.148 Ω
800 MHz
1
4
2
3
START
100.000 000 MHZ
STOP 1 200.000 000 MHZ
OSCin Input Impedance
2: 694.75 Ω
–5.339 kΩ
2.981 pF
10.000 000 MHz
2
3
41
OSCin
START
3.000 000 MHZ
STOP
1:
4.094 kΩ
–15.619 kΩ
3 MHz
3:
437.5 Ω
–2.7839 kΩ
20 MHz
4:
163.81 Ω
–1.508 kΩ
40 MHz
40.000 000 MHZ
17
MB15E03
■ REFERENCE INFORMATION
Typical plots measured with the
test circuit are shown below.
Each plot shows lock up time,
phase noise and reference
leakage.
•
•
•
•
•
Test Circuit
S.G
OSCin
Do
fin
LPF
fvco = 1018 MHz
Kv = 20 MHz/v
fr = 200 kHz
fosc = 13 MHz
LPF:
15 kΩ
Spectrum
Analyzer
2.2 kΩ
VCO
2000 pF
PLL Lock Up Time = 440 µs
(1005.000 MHz → 1031.000 MHz, within ± 1kHz)
∆ MKr x : 439.89783 µs
y : 25.94979 MHz
20000 pF
330 pF
PLL Phase Noise
@ within loop band = 76.2 dBc/Hz
REF
–10.0 dBm
ATT 10 dB
10dB/
MKR ∆12.40 kHz
–51.2 dB
30.00300
MHz
1.000
kHz/div
RBW
300 Hz
VBW
300 Hz
29.99800
MHz
10.2702 µs
1.9902702 ms
SPAN 50.0 kHz CENTER 1.0180000 GHz
PLL Lock Up Time = 400 µs
(1031.000 MHz → 1005.000 MHz, within ± 1kHz)
∆ MKr x : 400.00973 µs
y : –25.094747 MHz
PLL Reference Leakage
@ 200 kHz offset = 79.0 dBc
REF
10dB/
–10.0 dBm
ATT 10 dB
MKR ∆ 204 kHz
–79.0 dB
30.00300
MHz
1.00
kHz/div
RBW
10 kHz
VBW
10 kHz
29.99800
MHz
10.1432 µs
18
1.9901432 ms
SPAN 1.00 MHz CENTER
1.01800 GHz
MB15E03
■ ORDERING INFORMATION
Part number
Package
MB15E03 PFV1
16 pin, Plastic SSOP
(FPT-16P-M05)
MB15E03 PV
16 pin, Plastic BCC
(LCC-16P-M02)
Remarks
19
MB15E03
■ PACKAGE DIMENSIONS
* : These dimensions do not include resin protrusion.
16 pins, Plastic SSOP
(FPT-16P-M05)
+0.20
* 5.00±0.10(.197±.004)
1.25 –0.10
+.008
.049 –.004
0.10(.004)
INDEX
*4.40±0.10
(.173±.004)
0.65±0.12
(.0256±.0047)
4.55(.179)REF
C
1994 FUJITSU LIMITED F16013S-2C-4
+0.10
0.22 –0.05
+.004
.009 –.002
6.40±0.20
(.252±.008)
5.40(.213)
NOM
"A"
+0.05
0.15 –0.02
+.002
.006 –.001
Details of "A" part
0.10±0.10(.004±.004)
(STAND OFF)
0
10°
0.50±0.20
(.020±.008)
Dimensions in mm (inches).
(Continued)
20
MB15E03
16-pin, Plastic BCC
(LCC-16P-M02)
4.55±0.10
(.179±.004)
14
0.80(.032)MAX
9
3.40(.134)TYP
(Mounting height)
0.65(.026)TYP
9
14
0.40±0.10
(.016±.004)
2.45(.096)
TYP
3.40±0.10
(.1339±.0039)
45˚
"A"
1.15(.045)TYP
"B"
0.80(.032)
TYP
1
E-MARK
6
0.40(.016)
0.325±0.10
(.013±.004)
6
0.085±0.04
(.003±.002)
(STAND OFF)
Details of "A" part
0.05(.002)
1996 FUJITSU LIMITED C16013S-1C-1
1
Details of "B" part
0.75±0.10
(.030±.004)
0.40±0.10
(.016±.004)
C
1.725(.068)
TYP
0.60±0.10
(.024±.004)
0.60±0.10
(.024±.004)
Dimensions in mm (inches)
21
MB15E03
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3763
Fax: (044) 754-3329
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 432-9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281 0770
Fax: (65) 281 0220
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
F9704
 FUJITSU LIMITED
22
Printed in Japan