SAMSUNG S6A0078

S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
June. 2000.
Ver. 0.0
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
written permission of LCD Driver IC Team.
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
INTRODUCTION
S6A0078 is a dot matrix LCD driver & controller IC which is fabricated by low power CMOS technology. It can
display 1, 2, or 4 lines with 5 x 8 or 6 x 8 dots format.
FUNCTIONS
•
Character type dot matrix LCD driver & controller
•
Internal driver: 34 common and 120 segment signal output
•
Easy interface with 4-bit or 8-bit MPU
•
Clock synchronized serial interface
•
5 x 8 dots matrix possible
•
6 x 8 dots matrix possible
•
Bi-directional shift function
•
All character reverse display
•
Display shift per line
•
Voltage converter for LCD drive voltage: 13V max (2 times/3 times)
•
Various instruction functions
•
Automatic power on reset
FEATURES
• Internal Memory
- Character Generator ROM (CGROM): 9,600 bits (240 characters x 5 x 8 dot)
- Character Generator RAM (CGRAM): 64 x 8 bits (8 characters x 5 x 8 dot)
- Segment Icon RAM (SEGRAM): 16 x 8 bits (96 icons max.)
- Display Data RAM (DDRAM): 96 x 8 bits (96 characters max.)
•
Low power operation
Power supply voltage range: 2.7 - 5.5V (VDD)
LCD drive voltage range: 3.0 - 13.0V (VDD - V5)
•
CMOS process
•
Programmable duty cycle: 1/17, 1/33
•
Internal oscillator with an external resistor
•
Bare chip available
2
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
PROGRAMMABLE DUTY CYCLES
5-dot Font Width
Display Line
Numbers
Duty Ratio
Single-chip operation
Displayable Characters
Possible Icons
1
1/17
1 line of 48 characters
80
2
1/33
2 lines of 48 characters
80
4
1/33
4 lines of 24 characters
80
6-dot Font Width
Display Line
Numbers
Duty Ratio
Single-chip operation
Displayable Characters
Possible Icons
1
1/17
1 line of 40 characters
96
2
1/33
2 lines of 40 characters
96
4
1/33
4 lines of 20 characters
96
3
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
BLOCK DIAGRAM
IE
OSC1
OSC2
Oscillator
Power on Reset
(POR)
Timing Generator
RESET
IM
RS/CS
E/SCLK
RW/SID
System
Interface
Serial
4-bit
8-bit
8
Instruction
Register
(IR)
7
Instruction
Decoder
34-bit
Shift
Register
Display Data
RAM (DDRAM)
96 x 8-bit
Address
Counter
COM0Common COM33
Driver
7
7
8
8
DB4-DB7
8
Input/
Output
Buffer
DB3-DB1
COM1120-bit 120-bit
Segment COM120
Shift
Latch
Driver
Register Circuit
8
Busy Flag
DB0-SOD
3
Segment
RAM
(SEGRAM)
16 bytes
Vci
C1
Data
Register
(DR)
7
8
Character
Generator
RAM
(CGRAM)
64 bytes
LCD Driver
Voltage Selector
8
Character
Generator
ROM
(CGROM)
9600 bits
Cursor and
Blink
Controller
Voltage Converter
C2
5
V5OUT2
V5OUT3
VDD
GND(VSS)
4
5/6
Parallel/Serial Converter and
Smooth Scroll Circuit
V1 - V5
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
PAD CONFIGURATION
Y
(0, 0)
X
Chip size: 5340 × 8740
PAD size: 100 × 100
Unit
:µm
S6A0078
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
VDD
OSC2
OSC1
RESET
IM
IE
VSS1
RS/CS
RW/SID
E/SCLK
DB0/SOD
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Vci
C2
C1
VSS2
V5OUT2
V5OUT3
V5
V4
V3
V2
V1
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
5
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
PAD CENTER COORDINATES
Table 1. Pad Location
6
Pad
No.
Pad
Name
1
Coordinate
X
Y
Pad
No.
SEG79
-2504
3540
33
2
SEG80
-2504
3415
3
SEG81
-2504
4
SEG82
5
Coordinate
X
Y
Pad
No.
SEG111
-2504
-459
65
34
SEG112
-2504
-584
3290
35
SEG113
-2504
-2504
3165
36
SEG114
SEG83
-2504
3040
37
6
SEG84
-2504
2915
7
SEG85
-2504
8
SEG86
9
Pad Name
Pad Name
Coordinate
X
Y
IE
-1125
-4119
66
VSSI
-1100
-4119
-709
67
RS/CS
-875
-4119
-2504
-834
68
RW/SID
-750
-4119
SEG115
-2504
-959
69
E/SCLK
-625
-4119
38
SEG116
-2504
-1084
70
DB0/SOD
-500
-4119
2790
39
SEG117
-2504
-1209
71
DB1
-375
-4119
-2504
2665
40
SEG118
-2504
-1334
72
DB2
-250
-4119
SEG87
-2504
2540
41
SEG119
-2504
-1459
73
DB3
-125
-4119
10
SEG88
-2504
2415
42
SEG120
-2504
-1584
74
DB4
0
-4119
11
SEG89
-2504
2290
43
COM9
-2504
-1822
75
DB5
125
-4119
12
SEG90
-2504
2165
44
COM10
-2504
-1947
76
DB6
250
-4119
13
SEG91
-2504
2040
45
COM11
-2504
-2072
77
DB7
375
-4119
14
SEG92
-2504
1915
46
COM12
-2504
-2197
78
Vci
500
-4119
15
SEG93
-2504
1790
47
COM13
-2504
-2322
79
C2
625
-4119
16
SEG94
-2504
1665
48
COM14
-2504
-2447
80
C1
750
-4119
17
SEG95
-2504
1540
49
COM15
-2504
-2572
81
VSS2
875
-4119
18
SEG96
-2504
1425
50
COM16
-2504
-2697
82
V5OUT2
1000
-4119
19
SEG97
-2504
1290
51
COM25
-2504
-2822
83
V5OUT3
1125
-4119
20
SEG98
-2504
1165
52
COM26
-2504
-2947
84
V5
1250
-4119
21
SEG99
-2504
1040
53
COM27
-2504
-3072
85
V4
1375
-4119
22
SEG100
-2504
915
54
COM28
-2504
-3197
86
V3
1500
-4119
23
SEG101
-2504
790
55
COM29
-2504
-3322
87
V2
1625
-4119
24
SEG102
-2504
665
56
COM30
-2504
-3447
88
V1
1750
-4119
25
SEG103
-2504
540
57
COM31
-2504
-3572
89
COM24
2504
-3822
26
SEG104
-2504
415
58
COM32
-2504
-3697
90
COM23
2504
-3697
27
SEG105
-2504
290
59
COM33
-2504
-3822
91
COM22
2504
-3572
28
SEG106
-2504
165
60
VDD
-1750
-4119
92
COM21
2504
-3447
29
SEG107
-2504
40
61
OSC2
-1625
-4119
93
COM20
2504
-3322
30
SEG108
-2504
-84
62
OSC1
-1500
-4119
94
COM19
2504
-3197
31
SEG109
-2504
-209
63
RESET
-1375
-4119
95
COM18
2504
-3072
32
SEG110
-2504
-334
64
IM
-1250
-4119
96
COM17
2504
-2947
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
Table 1. Pad Location (Continued)
Pad
No.
Pad Name
97
Coordinate
X
Y
Pad
No.
COM8
2504
-2822
130
98
COM7
2504
-2697
99
COM6
2504
100
COM5
101
Coordinate
X
Y
Pad
No.
SEG25
2504
1415
163
131
SEG26
2504
1540
-2572
132
SEG27
2504
2504
-2447
133
SEG28
COM4
2504
-2322
134
102
COM3
2504
-2197
103
COM2
2504
104
COM1
105
Pad Name
Pad
Name
Coordinate
X
Y
SEG58
312
4119
164
SEG59
187
4119
1665
165
SEG60
62
4119
2504
1790
166
SEG61
-62
4119
SEG29
2504
1915
167
SEG62
-187
4119
135
SEG30
2504
2040
168
SEG63
-312
4119
-2072
136
SEG31
2504
2165
169
SEG64
-437
4119
2504
-1947
137
SEG32
2504
2290
170
SEG65
-562
4119
COM0
2504
-1822
138
SEG33
2504
2415
171
SEG66
-687
4119
106
SEG91
2504
-1584
139
SEG34
2504
2540
172
SEG67
-812
4119
107
SEG2
2504
-1459
140
SEG35
2504
2665
173
SEG68
-937
4119
108
SEG3
2504
-1334
141
SEG36
2504
2790
174
SEG69
-1062
4119
109
SEG4
2504
-1209
142
SEG37
2504
2915
175
SEG70
-1187
4119
110
SEG5
2504
-1084
143
SEG38
2504
3040
176
SEG71
-1312
4119
111
SEG6
2504
-959
144
SEG39
2504
3165
177
SEG72
-1437
4119
112
SEG7
2504
-834
145
SEG40
2504
3290
178
SEG73
-1562
4119
113
SEG8
2504
-709
146
SEG41
2504
3415
179
SEG74
-1687
4119
114
SEG9
2504
-584
147
SEG42
2504
3540
180
SEG75
-1812
4119
115
SEG10
2504
-459
148
SEG43
2187
4119
181
SEG76
-1937
4119
116
SEG11
2504
-334
149
SEG44
2062
4119
182
SEG77
-2062
4119
117
SEG12
2504
-209
150
SEG45
1937
4119
183
SEG78
-2187
4119
118
SEG13
2504
-84
151
SEG46
1812
4119
119
SEG14
2504
40
152
SEG47
1687
4119
120
SEG15
2504
165
153
SEG48
1562
4119
121
SEG16
2504
290
154
SEG49
1437
4119
122
SEG17
2504
415
155
SEG50
1312
4119
123
SEG18
2504
540
156
SEG51
1187
4119
124
SEG19
2504
665
157
SEG52
1062
4119
125
SEG20
2504
790
158
SEG53
937
4119
126
SEG21
2504
915
159
SEG54
812
4119
127
SEG22
2504
1040
160
SEG55
687
4119
128
SEG23
2504
1165
161
SEG56
562
4119
129
SEG24
2504
1290
162
SEG57
437
4119
7
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
PAD DESCRIPTION
Table 2. Pad Description
PAD (No)
Input/
Output
Name
VDD (60)
VSS1, VSS2
(66, 81)
0V (GND)
Power supply
Bias voltage level for LCD driving.
Power supply
Input voltage to the voltage converter to
generate LCD drive voltage
(Vci = 2.5 - 4.5V).
Input
SEG1-SEG80
(106-183, 1-42)
Output
Segment
output
Segment signal output for LCD drive.
LCD
COM0-COM33
(105-89, 43-59)
Output
Common
output
Common signal output for LCD drive.
LCD
Oscillator
When use internal oscillator, connect
external Rf resistor.
If external clock is used, connect it to
OSC1.
External
resistor/oscillator
(OSC1)
OSC1, OSC2
(61, 62)
Input
(OSC1),
Output
(OSC2)
C1, C2
(80, 79)
Input
External
capacitance
input
To use the voltage converter (2 times/3
times), these pins must be connected to the
external capacitance.
RESET (63)
Input
Reset pin
Initialized to low
Input
When IE = "High", Instruction set is
Select pin of
selected as Table 6.
instruction set When IE = "Low", Instruction set is selected
as Table 10.
IE (65)
V5OUT2 (82)
Output
V5OUT3 (83)
IM (64)
8
Interface
for logical circuit (+3V, +5V)
V1-V5
(88-84)
Vci (78)
Description
Input
Two times
converter
output
The value of Vci is converted two times.
To use three times converter, the same
capacitance as that of C1-C2 should be
connected here.
Three times
converter
output
The value of Vci is converted three times.
Interface
mode
selection
Select Interface mode with the MPU.
When IM = "Low": Serial mode,
When IM = "High": 4-bit/8-bit bus mode.
External
capacitance
-
-
V5 capacitance
V5
-
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
Table 2. Pad Description (Continued)
PAD (No)
RS/CS (67)
RW/SID (68)
E/SCLK (69)
DB0/SOD (70)
Input/
Output
Name
Interface
MPU
Input
Register
select/chip
select
When bus mode, used as register selection
input. When RS/CS = "High", data register
is selected. When RS/CS = "Low",
Instruction register is selected.
When serial mode, used as chip selection
input. When RS/CS = "Low", selected.
When RS/CS = "High", not selected.
(low access enable)
Input
Read
write/serial
input data
When bus mode, used as read/write
selection input. When RW/SID = "High",
read operation. When RW/SID = "Low",
write operation.
When serial mode, used for data input pin.
MPU
Input
Read write
enable/serial
clock
When bus mode, used as read write enable
signal.
When serial mode, used as serial clock
input pin.
MPU
Data bus 0
bit/serial
output data
When 8-bit bus mode, used as lowest bidirectional data bit. During 4-bit bus mode,
open this pin.
When serial mode, used as serial data
output pin. If not in read operation, open
this pin.
MPU
Input
Output/
Output
When 8-bit bus mode, used as low order bidirectional data bus.
DB1-DB3
(71-73)
Input.
Ouptut
DB4-DB7
(74-77)
Description
During 4-bit bus mode or serial mode, open
these pins.
Data bus 1- 7
When 8-bit bus mode, used as high order
bi-directional data bus. In case of 4-bit bus
mode, used as both high and low order.
DB7 used for Busy Flag output.
During serial mode, open these pins.
MPU
MPU
9
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
FUNCTION DESCRIPTION
SYSTEM INTERFACE
This chip has all three kinds interface type with MPU: Serial, 4-bit bus and 8-bit bus. Serial and bus (4-bit/8-bit) is
selected by IM input, and 4-bit bus and 8-bit bus is selected by DL bit in the instruction register. During read or
write operation, two 8-bit registers are used. one is data register (DR), the other is instruction register (IR). The
data register (DR) is used as temporary data storage place for being written into or read from
DDRAM/CGRAM/SEGRAM, target RAM is selected by RAM address setting instruction. Each internal operation,
reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the data in the
next DDRAM/CGRAM/SEGRAM address is transferred into DR automatically. Also after MPU writes data to DR,
the data in DR is transferred into DDRAM/CGRAM/SEGRAM automatically. The Instruction register (IR) is used
only to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select
register, use RS/CS input pin in 4-bit/8-bit bus mode (IM = "High") or RS bit in serial mode (IM = "Low").
RS
R/W
Operation
0
0
Instruction Write operation (MPU writes Instruction code into IR)
0
1
Read busy flag (DB7) and address counter (DB0-DB6)
1
0
Data write operation (MPU writes data into DR)
1
1
Data read operation (MPU reads data from DR)
BUSY FLAG (BF)
When BF = "High", it indicates that the internal operation is being processed. So during this time the next
instruction cannot be accepted. BF can be read, when RS = low and R/W = high (read instruction operation),
through DB7 Before executing the next instruction, be sure that BF is not high.
10
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
DISPLAY DATA RAM (DDRAM)
DDRAM stores display data of maximum 96 x 8 bits (96 characters). DDRAM address is set in the address
counter (AC) as a hexadecimal number. (refer to Figure 1)
MSB
LSB
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Figure 1. DDRAM Address
Display of 5-dot Font Width Character
5-dot 1-line Display
In case of 1-line display with 5-dot font, the address range of DDRAM is 00H-5FH (Refer to Figure 2).
Display Position
1
COM1
COM8
2
3
4
5
00 01 02 03 04
....
SEG1
20 21 22 23 24
25 26 27 28 29
13 14 15 16 17
18 19 1A 1B 1C
44 45 46 47 48
....
2B 2C 2D 2E 2F
SEG120 SEG1
COM9
COM16
SEG120
DDRAM Address
S6A0078
1
COM1
COM8
2
3
4
5
01 02 03 04 05
....
S6A0078
20 21 22 23 24
25 26 27 28 29
14 15 16 17 18
19 1A 1B 1C 1D
44 45 46 47 48
....
2C 2D 2E 2F 30
COM9
COM16
(After Shift Left)
1
COM1
COM8
2
3
4
5
5F 00 01 02 03
....
20 21 22 23 24
25 26 27 28 29
12 13 14 15 16
17 18 19 1A 1B
44 45 46 47 48
....
2A 2B 2C 2D 2E
COM9
COM16
(After Shift Right)
Figure 2. 1-line X 48ch. Display
11
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
5-dot 2-line Display
In case of 2-line display with 5-dot font, the address range of DDRAM is 00H-2FH, 40H-6FH (refer to Figure 3).
Display Position
20 21 22 23 24
25 26 27 28 29
COM1
COM8
00 01 02 03 04
1
2
3
4
5
....
13 14 15 16 17
18 19 1A 1B 1C
....
2B 2C 2D 2E 2F
COM9
COM16
COM17
COM24
40 41 42 43 44
....
53 54 55 56 57
58 59 5A 5B 5C
....
6B 6C 6D 6E 6F
COM25
COM32
SEG1
44 45 46 47 48
SEG120
SEG120 SEG1
DDRAM Address
S6A0078
1
2
3
4
5
S6A0078
20 21 22 23 24
25 26 27 28 29
COM1
COM8
01 02 03 04 05
....
14 15 16 17 18
19 1A 1B 1C 1D
....
2C 2D 2E 2F 00
44 45 46 47 48
COM9
COM16
COM17
COM24
41 42 43 44 45
....
54 55 56 57 58
59 5A 5B 5C 5D
....
6C 6D 6E 6F 40
COM25
COM32
(After Shift Left)
COM1
COM8
20 21 22 23 24
25 26 27 28 29
2F 00 01 02 03
1
2
3
4
5
....
12 13 14 15 16
17 18 19 1A 1B
....
2A 2B 2C 2D 2E
44 45 46 47 48
COM9
COM16
COM17
COM24
6F 40 41 42 43
....
52 53 54 55 56
57 58 59 5A 5B
....
6A 6B 6C 6D 6E
COM25
COM32
(After Shift Right)
Figure 3. 2-line X 48ch. Display (5-dot Font Width)
12
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
5-dot 4-line Display
In case of 4-line display with 5-dot font, the address range of DDRAM is 00H-17H, 20H-37H, 40H-57H, 60H-77H
(refer to Figure 4).
Display Position
1 2 3 4 5
COM1
00 01 02 03 04
COM8
COM9
20 21 22 23 24
COM16
COM17
40 41 42 43 44
COM24
20 21 22 23 24
....
13 14 15 16 17
....
33 34 35 36 37
....
53 54 55 56 57
COM25
60 61 62 63 64
....
73 74 75 76 77
COM32
SEG1
SEG120
DDRAM Address
S6A0078
1 2 3 4 5
COM1
01 02 03 04 05
COM8
COM9
21 22 23 24 25
COM16
20 21 22 23 24
....
14 15 16 17 00
....
34 35 36 37 20
COM17
41 42 43 44 45
COM24
....
54 55 56 57 40
COM25
61 62 63 64 65
COM32
....
74 75 76 77 60
(After Shift Left)
1 2 3 4 5
COM1
17 00 01 02 03
COM8
COM9
37 20 21 22 23
COM16
20 21 22 23 24
....
12 13 14 15 16
....
32 33 34 35 36
COM17
57 40 41 42 43
COM24
....
52 53 54 55 56
COM25
77 60 61 62 63
COM32
....
72 73 74 75 76
(After Shift Right)
Figure 4. 4-line X 24ch. Display (5-dot Font Width)
13
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Display of 6-dot Font Width Character
6-dot 1-line Display
In case of 1-line display with 6-dot font, the address range of DDRAM is 00H-5FH (refer to Figure 5).
Display Position
1
COM1
COM8
2
3
4
5
00 01 02 03 04
....
SEG1
16 17 18 19 20
21 22 23 24 25
0F 10 11 12 13
14 15 16 17 18
36 37 38 39 40
....
23 24 25 26 27
SEG120 SEG1
COM9
COM16
SEG120
DDRAM Address
S6A0078
1
COM1
COM8
2
3
4
5
01 02 03 04 05
....
S6A0078
16 17 18 19 20
21 22 23 24 25
10 11 12 13 14
15 16 17 18 19
36 37 38 39 40
....
24 25 26 27 28
COM9
COM16
(After Shift Left)
1
COM1
COM8
2
3
4
5
5F 00 01 02 03
....
16 17 18 19 20
21 22 23 24 25
0E 0F 10 11 12
13 14 15 16 17
(After Shift Right)
Figure 5. 1-line X 40ch. Display
14
36 37 38 39 40
....
22 23 24 25 26
COM9
COM16
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
6-dot 2-line Display
In case of 2-line display with 6-dot font, the address range of DDRAM is 00H-2FH, 40H-6FH (refer to Figure 6).
Display Position
16 17 18 19 20
21 22 23 24 25
COM1
COM8
00 01 02 03 04
1
2
3
4
5
....
0F 10 11 12 13
14 15 16 17 18
....
23 24 25 26 27
COM9
COM16
COM17
COM24
40 41 42 43 44
....
4F 50 51 52 53
54 55 56 57 58
....
63 64 65 66 67
COM25
COM32
SEG1
36 37 38 39 40
SEG120 SEG1
SEG120
DDRAM Address
S6A0078
1
2
3
4
5
S6A0078
16 17 18 19 20
21 22 23 24 25
COM1
COM8
01 02 03 04 05
....
10 11 12 13 14
15 16 17 18 19
....
36 37 38 39 40
24 25 26 27 28
COM9
COM16
COM17
COM24
41 42 43 44 45
....
50 51 52 53 54
55 56 57 58 59
....
64 65 66 67 68
COM25
COM32
(After Shift Left)
1
2
3
4
5
COM1
COM8
16 17 18 19 20
21 22 23 24 25
2F 00 01 02 03
....
0E 0F 10 11 12
13 14 15 16 17
....
36 37 38 39 40
22 23 24 25 26
COM9
COM16
COM17
COM24
6F 40 41 42 43
....
4E 4F 50 51 52
53 54 55 56 57
....
62 63 64 65 66
COM25
COM32
(After Shift Right)
Figure 6. 2-line X 40ch. Display (6-dot Font width)
15
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
6-dot 4-line Display
In case of 4-line display with 6-dot font, the address range of DDARM is 00H-17H, 20H-37H, 40H-57H, 60H-77H
(refer to Figure 7).
Display Position
1 2 3 4 5
COM1
00 01 02 03 04
COM8
COM9
20 21 22 23 24
COM16
COM17
40 41 42 43 44
COM24
16 17 18 19 20
....
0F 10 11 12 13
....
2F 30 31 32 33
....
4F 50 51 52 53
COM25
60 61 62 63 64
....
6F 70 71 72 73
COM32
SEG1
SEG120
DDRAM Address
S6A0078
1 2 3 4 5
COM1
01 02 03 04 05
COM8
COM9
21 22 23 24 25
COM16
16 17 18 19 20
....
10 11 12 13 14
....
30 31 32 33 34
COM17
41 42 43 44 45
COM24
....
50 51 52 53 54
COM25
61 62 63 64 65
COM32
....
70 71 72 73 74
(After Shift Left)
1 2 3 4 5
COM1
17 00 01 02 03
COM8
COM9
37 20 21 22 23
COM16
16 17 18 19 20
....
0E 0F 10 11 12
....
2E 2F 30 31 32
COM17
57 40 41 42 43
COM24
....
4E 4F 50 51 52
COM25
77 60 61 62 63
COM32
....
6E 6F 70 71 72
(After Shift Right)
Figure 7. 4-line X 20ch. Display (6-dot Font Width)
16
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
TIMING GENERATION CIRCUIT
Timing generation circuit generates clock signals for the internal operations.
ADDRESS COUNTER (AC)
Address Counter (AC) stores DDRAM/CGRAM/SEGRAM address, transferred from IR. After writing into (reading
from) DDRAM/CGRAM/SEGRAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W =
"High", AC can be read through DB0-DB6
CURSOR/BLINK CONTROL CIRCUIT
It controls cursor/blink ON/OFF and black/white inversion at cursor position.
LCD DRIVER CIRCUIT
LCD Driver circuit has 34 common and 120 segment signals for LCD driving. Data from
SEGRAM/CGRAM/CGROM is transferred to 120-bit segment latch serially, and then it is stored to 120-bit shift
latch. When each common is selected by 34-bit common register, segment data also output through segment
driver from 100-bit segment latch. In case of 1-line display mode, COM0-COM17 have 1/17 duty, and in 2-line or
4-line mode, COM0-COM33 have 1/33 duty ratio.
17
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
CGROM (CHARACTER GENERATOR ROM)
CGROM has 5 × 8-dot 240 character pattern
CGRAM (CHARACTER GENERATOR RAM)
CGRAM has up to 5 × 8-dot 8 characters. By writing font data to CGRAM, user defined character can be used
(refer to Table 4).
5x8 Dot Character Pattern
Table 4. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM)
Character Code (DDRAM data)
CGRAM Address
CGRAM Data
D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0
0 0 0 0 x 0 0 0 0 0 0 0 0 0 B1 B0 x 0 1 1 1 0
0 0 1
1 0 0 0 1
0 1 0
1 0 0 0 1
.
.
.
0
1
1
1 1 1 1 1
.
.
.
.
.
.
1 0 0
1 0 0 0 1
.
.
.
1
0
1
1 0 0 0 1
.
.
.
1 1 0
1 0 0 0 1
1 1 1
0 0 0 0 0
.
.
0
0
0
0
x
.
.
.
.
.
18
.
.
1
1
1
1
1
.
.
.
.
.
.
.
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
.
.
0
1
0
1
0
1
0
1
B1 B0
.
.
.
.
.
x
1
1
1
1
1
1
1
0
Pattern
Number
Pattern 1
.
.
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
1
0
Pattern 8
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
6 x 8 Dots Character Pattern
Character Code (DDRAM data)
CGRAM Address
CGRAM Data
D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0
0 0 0 0 x 0 0 0 0 0 0 0 0 0 B1 B0 0 0 1 1 1 0
0 0 1
0 1 0 0 0 1
0 1 0
0 1 0 0 0 1
.
.
.
0
0 1 1 1 1 1
1
1
.
.
.
.
.
.
0 1 0 0 0 1
1 0 0
.
.
.
0 1 0 0 0 1
1 0 1
.
.
.
0 1 0 0 0 1
1 1 0
0 0 0 0 0 0
1 1 1
.
.
.
.
0
0
0
0
x
.
.
.
.
.
1
1
1
1
1
.
.
.
.
.
.
.
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
.
.
0
1
0
1
0
1
0
1
B1 B0
.
.
.
.
.
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
0
Pattern
Number
Pattern 1
.
.
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
Pattern 8
1
1
0
1. When BE (Blink Enable bit) = "High", blink is controlled by B1 and B0 bit.
In case of 5-dot font width, when B1 = "1", enabled dots of P0-P4 will blink, and when B1 = "0" and B0 = "1",
enabled dots in P4 will blink, when B1 = "0" and B0 = "0", blink will not happen.
In case of 6-dot font width, when B1 = "1", enabled dots of P0-P5 will blink, and when B1 = "0" and B0 = "1",
enabled dots of P5 will blink, when B1 = "0" and B0 = "0", blink will not happen.
2. "X": Don't care
19
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
SEGRAM (SEGMENT ICON RAM)
SEGRAM has segment control data and segment pattern data. During 1-line display mode, COM0 (COM17)
makes the data of SEGRAM enable to display icons. When used in 2/4-line display mode COM0 (COM33) does
that. Its higher 2-bits are blinking control data, and lower 6-bits are pattern data (refer to Table 5 and Figure 7).
Table 5. Relationship Between SEGRAM Address and Display Pattern
SEGRAM Data Display Pattern
SEGRAM Address
5-dot Font Width
6-dot Font Width
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
B1
B0
X
S1
S2
S3
S4
S5
B1
B0
S1
S2
S3
S4
S5
S6
0
0
0
1
B1
B0
X
S6
S7
S8
S9
S10
B1
B0
S7
S8
S9
S10
S11
S12
0
0
1
0
B1
B0
X
S11
S12
S13
S14
S15
B1
B0
S13
S14
S15
S16
S17
S18
0
0
1
1
B1
B0
X
S16
S17
S18
S19
S20
B1
B0
S19
S20
S21
S22
S23
S24
0
1
0
0
B1
B0
X
S21
S22
S23
S24
S25
B1
B0
S25
S26
S27
S28
S29
S30
0
1
0
1
B1
B0
X
S26
S27
S28
S29
S30
B1
B0
S31
S32
S33
S34
S35
S36
0
1
1
0
B1
B0
X
S31
S32
S33
S34
S35
B1
B0
S37
S38
S39
S40
S41
S42
0
1
1
1
B1
B0
X
S36
S37
S38
S39
S40
B1
B0
S43
S44
S45
S46
S47
S48
1
0
0
0
B1
B0
X
S41
S42
S43
S44
S45
B1
B0
S49
S50
S51
S52
S53
S54
1
0
0
1
B1
B0
X
S46
S47
S48
S49
S50
B1
B0
S55
S56
S57
S58
S59
S60
1
0
1
0
B1
B0
X
S51
S52
S53
S54
S55
B1
B0
S61
S62
S63
S64
S65
S66
1
0
1
1
B1
B0
X
S56
S57
S58
S59
S60
B1
B0
S67
S68
S69
S70
S71
S72
1
1
0
0
B1
B0
X
S61
S62
S63
S64
S65
B1
B0
S73
S74
S75
S76
S77
S78
1
1
0
1
B1
B0
X
S66
S67
S68
S69
S70
B1
B0
S79
S80
S81
S82
S83
S84
1
1
1
0
B1
B0
X
S71
S72
S73
S74
S75
B1
B0
S85
S86
S87
S88
S89
S90
1
1
1
1
B1
B0
X
S76
S77
S78
S79
S80
B1
B0
S91
S92
S93
S94
S95
S96
•
B1, B0: Blinking control bit
Control Bit
Blinking Port
BE B1 B0
5-dot font width
6-dot font width
0 X X
No blink
No blink
1 0 0
No blink
No blink
1 0 1
D4
D5
1 1 X
D4 - D0
D5 - D0
•
S1-S80: Icon pattern ON / OFF in 5-dot font width
S1-S96: Icon pattern ON / OFF in 6-dot font width
•
"X": Don't care
20
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
SEG120
SEG119
SEG118
SEG117
SEG116
S116 S117 S118 S119 S120
SEG115
SEG114
SEG5
SEG113
SEG4
...
SEG112
SEG3
...
S111 S112 S113 S114 S115
SEG111
SEG2
S76 S77 S78 S79 S80
SEG80
S5
SEG79
S4
SEG78
S3
SEG77
S2
SEG76
S1
SEG1
5-Dot Font Width (FW = 0)
SEG120
SEG119
SEG118
SEG117
SEG116
SEG115
SEG114
SEG113
SEG6
SEG112
SEG5
SEG111
SEG4
...
SEG110
SEG3
...
S109 S110 S111 S112 S113 S114 S115 S116 S117 S118 S119 S120
SEG109
SEG2
S91 S92 S93 S94 S95 S96
SEG96
S6
SEG95
S5
SEG94
S4
SEG93
S3
SEG92
S2
SEG91
S1
SEG1
6-Dot Font Width (FW = 1)
Figure 7. Relationship between SEGRAM and Segment Display
21
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
INSTRUCTION DESCRIPTION
OUTLINE
To overcome the speed difference between internal clock of S6A0078 and MPU clock, S6A0078 performs
internal operation by storing control information to IR or DR. The internal operation is determined according to the
signal from MPU, composed of read/write and data bus. (refer to Table 6, 7) Instruction can be divided largely
four kinds,
•
S6A0078 function set instructions (set display methods, set data length, etc.)
•
Address set instructions to internal RAM
•
Data transfer instructions with internal RAM
•
Others .
The address of internal RAM is automatically increased or decreased by 1. When IE = "High", S6A0078 is
operated according to instruction set 1 (Table 6) and When IE = "Low", S6A0078 is operated according to
instruction set 2 (Table 7).
NOTE: During internal operation, busy flag (DB7) is read high. Busy flag check must precede the next instruction.
22
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
INSTRUCTION DESCRIPTION 1 (IE = "HIGH")
Table 6. Instruction Set 1
Instruction Code
Instruction RE
Clear
display
Return
home
Power
down
mode
Entry
mode set
Display
on/off
control
X
0
1
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Description
1
Write "20H" to DDRAM. and set
DDRAM address to "00H" from
AC.
1.53ms
X
Set DDRAM address to "00H" from
AC and return cursor to its original
position if shifted. The contents of
DDRAM are not changed.
1.53ms
PD
Set power down mode bit.
PD = "1" :power down mode set,
PD = "0" :power down mode
disable
39µs
Assign cursor moving direction.
I/D = "1": increment,
I/D = "0": decrement and display
shift enable bit.
S = "1": make display shift of the
enabled lines by the DS4
- DS1 bits in the shift enable
instruction.
S = "0": display shift disable
39µs
0
0
0
0
0
0
0
0
1
I/D
S
1
0
0
0
0
0
0
0
1
1
BID
Segment bi-direction function.
BID = "0": Seg1 → Seg80,
BID = "1": Seg80 → Seg1.
B
Set display/cursor/blink on/off
D = "1": display on,
D = "0": display off,
C = "1": cursor on,
C = "0": cursor off,
B = "1": blink on,
B = "0": blink off.
0
0
0
0
0
0
0
1
D
C
Executi
on Time
(fosc =
270kHz)
39µs
23
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Table 6. Instruction Set 1 (Continued)
Instruction Code
Instruction RE
Extended
function
set
Cursor or
display
shift
Shift
enable
Scroll
enable
24
1
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
1
FW B/W NW
Description
Assign font width, black/white
inverting of cursor, and 4-line
display mode control bit.
FW = "1": 6-dot font width,
FW = "0": 5-dot font width,
B/W = "1": black/white inverting of
cursor enable,
Executi
on Time
(fosc =
270kHz)
39µs
B/W = "0": black/white inverting
of cursor disable
NW = "1" : 4-line display mode,
NW = "0" : 1-line or 2-line display
mode.
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/L
X
X
Cursor or display shift.
S/C = "1": display shift,
S/C = "0": cursor shift,
R/L = "1": shift to right,
R/L = "0": shift to left.
1
S/C
39µs
1
(when DH = "1")
Determine the line for display shift
DS1 = "1/0": 1st line display shift
enable/disable
DS2 = "1/0": 2nd line display shift
DS4 DS3 DS2 DS1
enable/disable
DS3 = "1/0": 3rd line display shift
enable/disable
DS4 = "1/0": 4th line display shift
enable/disable.
39µs
1
(when DH = "0")
Determine the line for horizontal
smooth scroll.
HS1 = "1/0": 1st line dot scroll
enable/disable
HS4 HS3 HS2 HS1 HS2 = "1/0": 2nd line dot scroll
enable/disable
HS3 = "1/0": 3rd line dot scroll
enable/disable
HS4 = "1/0": 4th line dot scroll
enable/disable.
39µs
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
Table 6. Instruction Set 1 (Continued)
Instruction Code
Instruction RE
0
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
DL
N
RE
(0)
Function
Set
1
0
0
0
0
Set
CGRAM
address
0
0
0
0
1
Set
SEGRAM
address
1
0
0
0
1
Set
DDRAM
address
0
0
0
1
Set scroll
quantity
1
0
0
1
1
DL
N
RE
(1)
Set interface data length
(DL = "1": 8-bit, DL = "0": 4-bit),
numbers of display line when
NW = "0", (N = "1": 2-line, N = "0":
1-line),extension register, RE ("0"),
DH REV shift/scroll enable
DH = "1": display shift enable
DH = "0": dot scroll enable.
reverse bit
REV = "1": reverse display,
REV = "0": normal display.
BE
0
AC5 AC4 AC3 AC2 AC1 AC0
X
X
AC3 AC2 AC1 AC0
AC6 AC5 AC4 AC3 AC2 AC1 AC0
X
SQ
5
SQ
4
SQ
3
SQ
2
Description
SQ
1
SQ
0
Executi
on Time
(fosc =
270kHz)
39µs
Set DL, N, RE ("1") and
CGRAM/SEGRAM blink enable
(BE)
BE = " 1/0": CGRAM/SEGRAM
blink enable/disable
39µs
Set CGRAM address in address
counter.
39µs
Set SEGRAM address in address
counter.
39µs
Set DDRAM address in address
counter.
39µs
Set the quantity of horizontal dot
scroll.
39µs
Can be known whether during
internal operation or not by
reading BF. The contents of
AC6 AC5 AC4 AC3 AC2 AC1 AC0
address counter can also be read.
BF = "1": busy state,
BF = "0": ready state.
Read busy
flag and
address
X
0
1
BF
Write data
X
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write data into internal RAM
(DDRAM / CGRAM / SEGRAM).
43µs
Read data
X
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read data from internal RAM
(DDRAM / CGRAM / SEGRAM).
43µs
0µs
NOTES:
1. When an MPU program with busy flag (DB7) checking is mode, 1/2 fosc (is necessary) for executing the next instruction
by the "E" signal after the busy flag (DB7) goes to "Low"
2. "X" don’ s care
25
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Display Clear
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
1
Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H"
into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on first
line of the display. Make entry mode increment (I/D = "1").
Return Home: (RE = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
1
X
Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return
cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change.
Power Down Mode Set: (RE = 1)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
0
0
1
PD
Power down mode enable bit set instruction.
When PD = "High", it makes S6A0078 suppress current consumption except the current needed for data storage
by executing next three functions.
•
Make the output value of all the COM/SEG ports VDD
•
Make the COM/SEG output value of extension driver VDD by setting D output to "High" and M output to
"Low"
•
Disable voltage converter to remove the current through the divide resistor of power supply.
You can use this instruction as power sleep mode. When PD = "Low", power down mode becomes disabled.
26
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
Entry Mode Set
(RE = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
1
I/D
S
Set the moving direction of cursor and display.
I/D:
Increment/decrement of DDRAM address (cursor or blink)
When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1.
When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1.
- CGRAM/SEGRAM operates the same as DDRAM, when read from or write to CGRAM/SEGRAM.
When S = "High", after DDRAM write, the display of enabled line by DS1-DS4 bits in the shift enable instruction
is shifted to the right (I/D = "0") or to the left I/D = "1"). But it will seem as if the cursor does not move. When S =
"Low", or DDRAM read, or CGRAM/SEGRAM read/write operation, shift of display like this function is not
performed.
(RE = 1)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
1
1
BID
Set the data shift direction of segment in the application set.
BID:
Data shift direction of segment
When BID = "Low", segment data shift direction is set to normal order from SEG1 to SEG120.
When BID = "High", segment data shift direction is set to reverse from SEG120 to SEG1
By using this instruction, you can raise the efficiency of application board area.
- The BID setting instruction is recommended to be set at the same time level of function set instruction.
- DB1 bit must be set to "1".
27
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Display ON/OFF Control ( RE = 0 )
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
1
D
C
B
Control display/cursor/blink ON/OFF 1 bit register.
D:
Display ON/OFF control bit
When D = "High", entire display is turned on.
When D = "Low", display is turned off, but display data is remained in DDRAM.
C:
Cursor ON/OFF control bit
When C = "High", cursor is turned on.
When C = "Low", cursor is disappeared in current display, but I/D register remains its data.
B:
Cursor blink ON/OFF control bit
When B = "High", cursor blink is on, that performs alternate between all the high data and display
character at the cursor position. If fosc has 270kHz frequency, blinking has 370 ms interval.
When B = "Low", blink is off.
Extended Function Set (RE = 1)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
1
FW
B/W
NW
FW:
Font width control
When FW = "High", display character font width is assigned to 6-dot and execution time becomes 6/5
times than that of 5-dot font width.
The user font, specified in CGRAM, is displayed into 6-dot font width, bit-5 to bit-0,including the leftmost
space bit of CGRAM.(refer to Figure 7)
When FW = "Low", 5-dot font width is set.
B/W:
Black/White Inversion enable bit
When B/W = "High", black/white inversion at the cursor position is set. In this case C/B bit of display
ON/OFF control instruction becomes don't care condition. If fosc has frequency of 270kHz, inversion has
370 ms intervals.
NW:
4 Line mode enable bit
When NW = "High", 4 line display mode is set. In this case N bit of function set instruction becomes don't
care condition.
28
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
6-bit
S
p
a
c
e
S6A0078
6-bit
CGROM
Characte
Font
(5-dot)
CGRAM
Characte
Font
(6-dot)
8-bit
CGROM
8-bit
CGRAM
Figure 9. 6-dot font width CGROM/CGRAM
Cursor or Display Shift (RE = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
S/C
R/L
X
X
Without writing or reading of display data, shift right/left cursor position or display. This instruction is used to
correct or search display data. (refer to Table 7) during 2-line mode display, cursor moves to the 2nd line after
48th digit of 1st line. When 4-line mode, cursor moves to the next line, only after every 24th digit of the current
line. Note that display shift is performed simultaneously in all the line enabled by DS1-DS4 in the shift enable
instruction. When displayed data is shifted repeatedly, each line shifted individually. When display shift is
performed, the contents of address counter are not changed. During low power consumption mode, display shift
may not be performed normally.
Table 7. Shift Patterns According to S/C and R/L Bits
S/C
R/L
Operation
0
0
Shift cursor to the left, address counter is decreased by 1
0
1
Shift cursor to the right, address counter is increased by 1
1
0
Shift all the display to the left, cursor moves according to the display
1
1
Shift all the display to the right, cursor moves according to the
display
29
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Shift/Scroll Enable (RE = 1)
(DH = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
HS4
HS3
HS2
HS1
HS:
Horizontal scroll per line enable
This instruction makes valid dot shift by a display line unit. HS1, HS2, HS3 and HS4 indicate each line to
be dot scrolled, and each scroll is performed individually in each line.
If you want to scroll the line in 1-line display mode or the 1st line in 2-line display mode, set HS1 and
HS2 to "High". If the 2nd line scroll is needed in 2-line mode, set HS3 and HS4 to "High".
(refer to Table 8)
(DH = 1)
DS:
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
DS4
DS3
DS2
DS1
Display shift per line enable
This instruction selects shifting line to be shifted according to each line mode in display shift right/left
instruction.
DS1, DS2, DS3 and DS4 indicate each line to be shifted, and each shift is performed individually in each
line. If you set DS1 and DS2 to "High" (enable) in 2 line mode, only the 1st line is shifted and the 2nd line
is not shifted. When only DS1 = "High", only the half of the 1st line is shifted. If all the DS bits (DS1 to
DS4) are set to "Low" (disable), no display is shifted.
Table 8. Relationship Between DS and COM Signal
30
Enable Bit
Enabled Common Signals
During Shift
HS1/DS1
COM1 - COM8
HS2/DS2
COM9 - COM16
HS3/DS3
COM17 - COM24
HS4/DS4
COM25 - COM32
Description
The part of display line that corresponds to
enabled common signal can be shifted.
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
Function Set
(RE = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
DL
N
RE(0)
DH
REV
DL:
Interface data length control bit
When DL = "High", it means 8-bit bus mode with MPU.
When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit
bus mode.
When 4-bit bus mode, it needs to transfer 4-bit data by two times.
N:
Display line number control bit It is variable only when NW bit of extended function set instruction is
Low.
When N = "Low", it means 1-line display mode.
When N = "High", 2-line display mode is set.
When NW = "High", N bit is invalid, it means 4-line mode independent of N bit.
RE:
Extended function registers enable bit
At this instruction, RE must be "Low".
DH:
Display shift enable selection bit.
When DH = "High", display shift per line becomes enable.
When DH = "Low", smooth dot scroll becomes enable.
This bit can be accessed only when IE pin input is "High".
REV:
Reverse enable bit
When REV = "High", all the display data are reversed. Namely, all the white dots become black and
black dots become white.
When REV = "Low", the display mode set normal display.
(RE = 1)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
DL
N
RE(1)
BE
0
DL:
Interface data length control bit
When DL = "High", it means 8-bit bus mode with MPU.
When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit
bus mode.
When 4-bit bus mode, it needs to transfer 4-bit data by two times.
N:
Display line number control bit
It is variable only when NW bit of extended function set instruction is low.
When N = "Low", it means 1-line display mode.
When N = "High", 2-line display mode is set.
When NW = "High", N bit is invalid, it means 4-line mode independent of N bit.
RE:
Extended function registers enable bit
When RE = "High", extended function set registers, SEGRAM address set registers, BID bit, HS/DS bits
of shift/scroll enable instruction and BE bits of function set register can be accessed.
BE:
CGRAM/SEGRAM data blink enable bit
If BE is "High", It makes user font of CGRAM and segment of SEGRAM blinking. The quantity of blink is
assigned the highest 2 bit of CGRAM/SEGRAM.
31
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Set CGRAM Address (RE = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
AC5
AC4
AC3
AC2
AC1
AC0
Set CGRAM address to AC. This instruction makes CGRAM data available from MPU.
Set SEGRAM Address (RE = 1)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
X
X
AC3
AC2
AC1
AC0
Set CGRAM address to AC. This instruction makes CGRAM data available from MPU
Set DDRAM Address (RE = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. When 1-line display mode
(N = 0, NW = 0), DDRAM address is from "00H" to "5FH". In 2-line display mode (N = 1, NW = 0), DDRAM
address in the 1st line is from "00H" to "2FH", and DDRAM address in the 2nd line is from "40H" to "6FH". In 4line display mode (NW = 1), DDRAM address is from "00H" to "13H" in the 1st line, from "20H" to "37H" in the
2nd line, from "40H" to "57H" in the 3rd line and from "60H" to "77H" in the 4th line.
Set Scroll Quantity (RE = 1)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
X
SQ5
SQ4
SQ3
SQ2
SQ1
SQ0
As set SQ5 to SQ0, horizontal scroll quantity can be controlled in dot units (refer to Table 9). In this case
S6A0078 can show hidden areas of DDRAM by executing smooth scroll from 1 to 48 dots.
Table 9. Scroll Quantity According to HDS Bits
32
SQ5
SQ4
SQ3
SQ2
SQ1
SQ0
Function
0
0
0
0
0
0
No shift
0
0
0
0
0
1
Shift left by 1-dot
0
0
0
0
1
0
Shift left by 2-dot
0
0
0
0
1
1
Shift left by 3-dot
:
:
:
:
:
:
:
1
0
1
1
1
1
Shift left by 47-dot
1
1
X
X
X
X
Shift left by 48-dot
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
Read Busy Flag & Address
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
BF
AC6
AC5
AC4
AC3
AC2
AC1
AC0
This instruction shows whether S6A0078 is in internal operation or not. If the resultant BF is High, it means the
internal operation is in progress and you have to wait until BF to be Low, and then the next instruction can be
performed. In this instruction you can read also the value of address counter.
Write Data to RAM
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write binary 8-bit data to DDRAM/CGRAM/SEGRAM.
The selection of RAM from DDRAM, CGRAM, or SEGRAM, is set by the previous address set instruction:
DDRAM address set, CGRAM address set, SEGRAM address set. RAM set instruction can also determines the
AC direction to RAM. After write operation, the address is automatically increased/decreased by 1, according to
the entry mode.
Read Data From RAM
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read binary 8-bit data from DDRAM/CGRAM/SEGRAM.
The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not
performed before this instruction, the data that read first is invalid, because the direction of AC is not determined.
If you read RAM data several times without RAM address set instruction before read operation, you can get
correct RAM data from the second, but the first data would be incorrect, because there is no time margin to
transfer RAM data. In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM
address set instruction : it also transfer RAM data to output data register. After read operation address counter is
automatically increased/decreased by 1 according to the entry mode. After CGRAM/SEGRAM read operation,
display shift may not be executed correctly.
- In case of RAM write operation, after this AC is increased/decreased by 1 like read operation. In this time, AC
indicates the next address position, but you can read only the previous data by read instruction.
33
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
INSTRUCTION DESCRIPTION 2 (IE = "LOW")
Table 10. Instruction Set 2
Instruction Code
Instruction RE
Clear
display
Return
home
Entry
mode set
Display
ON/OFF
control
Extended
function
set
Cursor or
display
shift
X
X
X
0
1
0
Description
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
S/C
1
Write "20H" to DDRAM. and set
DDRAM address to "00H" from
AC.
1.53ms
X
Set DDRAM address to "00H" from
AC and return cursor to its original
position if shifted. The contents of
DDRAM are not changed.
1.53ms
S
Assign cursor moving direction.
I/D = "1": increment,
I/D = "0": decrement. and display
shift enable bit.
S = "1" :make entire display shift
of all lines during DDRAM write,
S = "0": display shift disable
39µs
B
Set display/cursor/blink on/off
D = "1": display on,
D = "0": display off,
C = "1": cursor on,
C = "0": cursor off,
B = "1": blink on,
B = "0": blink off.
39µs
FW B/W NW
Assign font width, black/white
inverting of cursor, and 4-line
display mode control bit.
FW = "1": 6-dot font width,
FW = "0": 5-dot font width,
B/W = "1": black/white inverting of
cursor enable,
B/W = "0": black/white inverting of
cursor disable
NW = "1": 4-line display mode,
NW = "0": 1-line or 2-line display
mode
39µs
R/L
Cursor or display shift.
S/C = "1": display shift,
S/C = "0": cursor shift,
R/L = "1": shift to right,
R/L = "0": shift to left
39µs
0
0
1
D
0
1
I/D
C
X
X
Table 10. Instruction Set 2 (Continued)
34
Execution
Time
(fosc =
270kHz)
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
Instruction Code
Instruction RE
Scroll
enable
Function
set
1
0
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
1
0
0
0
0
Set
CGRAM
address
0
0
0
0
1
Set
SEGRAM
address
1
0
0
0
1
Set
DDRAM
address
0
0
0
1
Set scroll
quantity
1
0
0
1
Read busy
flag and
address
X
0
1
BF
Write data
X
1
0
D7
0
1
1
1
DL
DL
Determine the line for horizontal
smooth scroll.
HS1 = "1/0": 1st line dot scroll
enable/disable
HS2 = "1/0": 2nd line dot scroll
HS4 HS3 HS2 HS1
enable/disable
HS3 = "1/0": 3rd line dot scroll
enable/disable
HS4 = "1/0": 4th line dot scroll
enable/disable
N
N
RE
(0)
RE
(1)
X
BE
X
X
39µs
0
Set DL, N, RE ("1") and
CGRAM/SEGRAM blink enable
(BE)
BE = "1/0": CGRAM/SEGRAM
blink enable/disable
39µs
Set CGRAM address in address
counter.
39µs
Set SEGRAM address in address
counter.
39µs
Set DDRAM address in address
counter.
39µs
Set the quantity of horizontal dot
scroll.
39µs
AC3 AC2 AC1 AC0
AC6 AC5 AC4 AC3 AC2 AC1 AC0
X
QC5 QC4 QC3 QC2 QC1 QC0
Can be known whether during
internal operation or not by
reading BF. The contents of
AC6 AC5 AC4 AC3 AC2 AC1 AC0
address counter can also be read.
BF = "1": busy state,
BF = "0": ready state.
D6
D5
D4
D3
D2
D1
39µs
Set interface data length
DL = "1": 8-bit,
DL = "0": 4-bit numbers of display
line when NW = "0",
N = "1": 2-line,
N = "0": 1-line extension register,
RE ("0")
AC5 AC4 AC3 AC2 AC1 AC0
X
Description
Execution
Time
(fosc =
270kHz)
D0
Write data into internal RAM
(DDRAM / CGRAM / SEGRAM).
0µs
43µs
35
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Table 10. Instruction Set 2 (Continued)
Instruction Code
Instruction RE
Read data
36
X
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Description
Read data from internal RAM
(DDRAM / CGRAM / SEGRAM).
Execution
Time
(fosc =
270kHz)
43µs
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
Display Clear
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
1
Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H"
into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on first
line of the display. And entry mode is set to increment mode (I/D = "1").
Return Home
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
1
X
Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return
cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change.
Entry Mode Set
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
1
I/D
S
Set the moving direction of cursor and display.
I/D:
Increment / decrement of DDRAM address (cursor or blink)
When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1.
When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1.
- CGRAM/SEGRAM operates the same as DDRAM, when read from or write to CGRAM/SEGRAM.
When S = "High", after DDRAM write, the entire display of all lines is shifted to the right (I/D = "0") or to the left
(I/D = "1"). But it will seem as if the cursor does not move. When S = "Low", or DDRAM read, or
CGRAM/SEGRAM read/write operation, shift of entire display is not performed.
37
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Display ON/OFF Control (RE = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
1
D
C
B
Control display/cursor/blink ON/OFF 1 bit register.
D:
Display ON/OFF control bit
When D = "High", entire display is turned on.
When D = "Low", display is turned off, but display data is remained in DDRAM.
C:
Cursor ON/OFF control bit
When C = "High", cursor is turned on.
When C = "Low", cursor is disappeared in current display, but I/D register remains its data.
B:
Cursor blink ON/OFF control bit
When B = "High", cursor blink is on, that performs alternate between all the high data and display
character at the cursor position. If fosc has 270kHz frequency, blinking has 370 ms interval.
When B = "Low", blink is off.
Extended Function Set (RE = 1)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
1
FW
B/W
NW
FW:
Font width control
When FW = "High", display character font width is assigned to 6-dot and execution time becomes 6/5
times than that of 5-dot font width. The user font, specified in CGRAM, is displayed into 6-dot font width,
bit-5 to bit-0, including the leftmost space bit of CGRAM. (Refer to Figure 8)
When FW = "Low", 5-dot font width is set.
B/W:
Black/White Inversion enable bit
When B/W = "High", black/white inversion at the cursor position is set. In this case C/B bit of display
ON/OFF control instruction becomes don't care condition. If fosc has frequency of 270kHz, inversion has
370ms intervals.
NW:
4 Line mode enable bit
When NW = "High", 4 line display mode is set. In this case N bit of function set instruction becomes don't
care condition.
6-bit
S
p
a
c
e
CGROM
Characte
Font
(5-dot)
CGROM
6-bit
8-bit
CGRAM
Characte
Font
(6-dot)
8-bit
CGRAM
Figure 10. 6-Dot Font Width CGROM/CGRAM
38
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
Cursor or Display Shift (RE = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
S/C
R/L
-
-
Without writing or reading of display data, shift right/left cursor position or display. This instruction is used to
correct or search display data. (Refer to Table 7) during 2-line mode display, cursor moves to the 2nd line after
48th digit of 1st line. When 4-line mode, cursor moves to the next line, only after every 24th digit of the current
line. Note that display shift is performed simultaneously in all the line. When displayed data is shifted repeatedly,
each line shifted individually. When display shift is performed, the contents of address counter are not changed.
Table 11. Shift Patterns According to S/C and R/L Bits
S/C
R/L
Operation
0
0
Shift cursor to the left, address counter is decreased by 1
0
1
Shift cursor to the right, address counter is increased by 1
1
0
Shift all the display to the left, cursor moves according to the display
1
1
Shift all the display to the right, cursor moves according to the display
Scroll Enable (RE = 1)
HS:
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
HS4
HS3
HS2
HS1
Horizontal scroll per line enable
This instruction makes valid dot shift by a display line unit. HS1, HS2, HS3 and HS4 indicate each line to
be dot scrolled, and each scroll is performed individually in each line.
If you want to scroll the line in 1-line display mode or the 1st line in 2-line display mode, set HS1 and
HS2 to "High". If the 2nd line scroll is needed in 2-line mode, set HS3 and HS4 to "High".
(refer to Table 8)
39
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Function Set
(RE = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
DL
N
RE(0)
-
-
DL:
Interface data length control bit
When DL = "High", it means 8-bit bus mode with MPU.
When DL = "Low", it means 4-bit bus mode with MPU.
So to speak, DL is a signal to select 8-bit or 4-bit bus mode.
When 4-bit bus mode, it needs to transfer 4-bit data by two times.
N:
Display line number control bit
It is variable only when NW bit of extended function set instruction is Low.
When N = "Low", it means 1-line display mode.
When N = "High", 2-line display mode is set.
When NW = "High", N bit is invalid, it means 4-line mode independent of N bit.
RE:
Extended function registers enable bit
At this instruction, RE must be "Low".
(RE = 1)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
DL
N
RE(1)
BE
0
DL:
Interface data length control bit
When DL = "High", it means 8-bit bus mode with MPU.
When DL = "Low", it means 4-bit bus mode with MPU.
So to speak, DL is a signal to select 8-bit or 4-bit bus mode.
When 4-bit bus mode, it needs to transfer 4-bit data by two times.
N:
Display line number control bit
It is variable only when NW bit of extended function set instruction is low.
When N = "Low", it means 1-line display mode.
When N = "High", 2-line display mode is set.
When NW = "High", N bit is invalid, it means 4-line mode independent of N bit.
RE:
Extended function registers enable bit
When RE = "High", extended function set registers, SEGRAM address set registers, HS bits of scroll
enable instruction and BE bits of function set register can be accessed.
BE:
CGRAM/SEGRAM data blink enable bit
If BE is "High", It makes user font of CGRAM and segment of SEGRAM blinking. The quantity of blink is
assigned the highest 2 bit of CGRAM/SEGRAM.
40
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
Set CGRAM Address (RE = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
AC5
AC4
AC3
AC2
AC1
AC0
Set CGRAM address to AC.
This instruction makes CGRAM data available from MPU.
Set SEGRAM Address (RE = 1)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
-
-
AC3
AC2
AC1
AC0
Set SEGRAM address to AC.
This instruction makes SEGRAM data available from MPU.
Set DDRAM Address (RE = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Set DDRAM address to AC.
This instruction makes DDRAM data available from MPU.
When 1-line display mode (N = 0, NW = 0), DDRAM address is from "00H" to "5FH".
In 2-line display mode (N = 1, NW = 0), DDRAM address in the 1st line is from "00H" to "2FH", and DDRAM
address in the 2nd line is from "40H" to "6FH".
In 4-line display mode (NW = 1), DDRAM address is from "00H" to "17H" in the 1st line, from "20H" to "37H" in
the 2nd line, from "40H" to "57H" in the 3rd line and from "60H" to "77H" in the 4th line.
Set Scroll Quantity (RE = 1)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
X
SQ5
SQ4
SQ3
SQ2
SQ1
SQ0
As set SQ5 to SQ0, horizontal scroll quantity can be controlled in dot units. (Refer to Table 12). In this case
S6A0078 execute dot smooth scroll from 1 to 48 dots.
Table 12. Scroll Quantity According to HDS Bits
SQ5
SQ4
SQ3
SQ2
SQ1
SQ0
Function
0
0
0
0
0
0
No shift
0
0
0
0
0
1
Shift left by 1-dot
0
0
0
0
1
0
Shift left by 2-dot
0
0
0
0
1
1
Shift left by 3-dot
:
:
:
:
:
:
:
1
0
1
1
1
1
Shift left by 47-dot
1
1
X
X
X
X
Shift left by 48-dot
41
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Read Busy Flag & Address
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
BF
AC6
AC5
AC4
AC3
AC2
AC1
AC0
This instruction shows whether S6A0078 is in internal operation or not. If the resultant BF is high, it means the
internal operation is in progress and you have to wait until BF to be low, and then the next instruction can be
performed. In this instruction you can read also the value of address counter.
Write Data to RAM
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write binary 8-bit data to DDRAM/CGRAM/SEGRAM. The selection of RAM from DDRAM, CGRAM, or
SEGRAM, is set by the previous address set instruction : DDRAM address set, CGRAM address set, SEGRAM
address set. RAM set instruction can also determines the AC direction to RAM. After write operation, the address
is automatically increased/decreased by 1, according to the entry mode.
Read Data From RAM
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read binary 8-bit data from DDRAM/CGRAM/SEGRAM.
The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not
performed before this instruction, the data that read first is invalid, because the direction of AC is not determined.
If you read RAM data several times without RAM address set instruction before read operation, you can get
correct RAM data from the second, but the first data would be incorrect, because there is no time margin to
transfer RAM data. In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM
address set instruction: it also transfer RAM data to output data register. After read operation address counter is
automatically increased/decreased by 1 according to the entry mode. After CGRAM/SEGRAM read operation,
display shift may not be executed correctly.
- In case of RAM write operation, after this AC is increased/decreased by 1 like read operation. In this time, AC
indicates the next address position, but you can read only the previous data by read instruction.
42
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
INTERFACE WITH MPU
S6A0078 can transfer data in bus mode (4-bit or 8-bit) or serial mode with MPU. So you can use any type 4 or 8bit MPU.
In case of 4-bit bus mode, data transfer is performed by two times to transfer 1 byte data.
•
When interfacing data length are 4-bit, only 4 ports, from DB4 to DB7, are used as data bus.
At first higher 4-bit (in case of 8-bit bus mode, the contents of DB4-DB7) are transferred, and then lower 4-bit
(in case of 8-bit bus mode, the contents of DB0-DB3) are transferred. So transfer is performed by two times.
Busy Flag outputs "High" after the second transfer are ended.
•
When interfacing data length are 8-bit, transfer is performed at a time through 8 ports, from DB0 to DB7.
•
If IM is set to "Low", serial transfer mode is set.
43
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
INTERFACE WITH MPU IN BUS MODE
Interface With 8-Bits MPU
If 8-bits MPU is used, S6A0078 can connect directly with that. In this case, port E, RS, R/W and DB0 to DB7
need to interface each other. Example of timing sequence is shown below.
RS
R/W
E
Internal Signal
DB7
Internal Operation
Data
Busy
No
Busy
Busy Flag
Check
Busy Flag
Check
Busy
Instruction
Busy Flag
Check
Data
Instruction
Figure 11. Example of 8-bit Bus Mode Timing Sequence
Interface With 4-bits MPU
If 4-bits MPU is used, S6A0078 can connect directly with this. In this case, port E, RS, R/W and DB4 to DB7
need to interface each other. The transfer is performed by two times.
Example of timing sequence is shown below.
RS
R/W
E
Internal Signal
DB7
Internal Operation
D7
D3
Instruction
Busy
AC3
Busy Flag Check
No
Busy
AC3
Busy Flag Check
Figure 12. Example of 4-bit Bus Mode Timing Sequence
44
D7
D3
Instruction
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
INTERFACE WITH MPU IN SERIAL MODE
When IM port input is "Low", serial interface mode is started. At this time, all three ports, SCLK (synchronizing
transfer clock), SID (serial input data), and SOD (serial output data), are used. If you want to use S6A0078 with
other chips, chip select port (CS) can be used. By setting CS to "Low", S6A0078 can receive SCLK input. If CS is
set to "High", S6A0078 reset the internal transfer counter. Before transfer real data, start byte has to be
transferred. It is composed of succeeding 5 "High" bits, read write control bit (R/W), register selection bit (RS),
and end bit that indicates the end of start byte. Whenever succeeding 5 "High" bits are detected by S6A0078, it
makes serial transfer counter reset and ready to receive next information. The next input data are register
selection bit that determine which register will be used, and read write control bit that determine the direction of
data. Then end bit is transferred, which must have "Low" value to show the end of start byte. (refer to Figure 11.
Figure 12)
Write Operation (R/W = 0)
After start byte is transferred from MPU to S6A0078, 8-bit data is transferred which is divided into 2 bytes, each
byte has 4 bit's real data and 4 bit's partition token data. For example, if real data is "10110001" (D0 - D7), then
serially transferred data becomes "1011 0000 0001 0000" where 2nd and 4th 4 bits must be "0000" for safe
transfer. To transfer several bytes continuously without changing RS bit and RW bit, start byte transfer is needed
only at first starting time. Namely, after first start byte is transferred, real data can be transferred succeeding.
Read Operation (R/W = 1)
After start byte is transferred to S6A0078, MPU can receive 8-bit data through the SOD port at a time from the
LSB. Wait time is needed to insert between start byte and data reading, because internal reading from RAM
requires some delay. Continuous data reading is possible like serial write operation. It also needs only one start
bytes, only if you insert some delay between reading operations of each byte. During the reading operation,
S6A0078 observes succeeding 5 "High" from MPU. If it is detected, S6A0078 restarts serial operation at once
and ready to receive RS bit. So in continuous reading operation, SID port must be "0".
45
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Serial Write Operation
CS (Input)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCLK (Input)
SID (Input)
"1" "1" "1" "1" "1" R/W RS 0 D0 D1 D2 D3 "0" "0" "0" "0" D4 D5 D6 D7 "0" "0" "0" "0"
Starting Byte
Synchronizing
Bit String
Instruction
Lower Data
Upper Data
1'st Byte
2'nd Byte
Serial Read Operation
CS (Input)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SCLK (Input)
SID (Input)
"1" "1" "1" "1" "1" R/W RS "0" "0" "0" "0" "0" "0" "0" "0" "0"
SOD (Output)
D0 D1 D2 D3 D4 D5 D6 D7
Starting Byte
Synchronizing
Bit String
Busy Flag/
Read Data
Lower
Data
Upper
Data
Figure 11. Timing Diagram of Serial Data Transfer
46
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
Continuous Write Operation
SCLK
SID
Wait
Start Byte
1'st Byte
2'nd Byte
Instruction1
Wait
1'st Byte
2'nd Byte
Instruction2
Instruction1
Execution Time
1'st Byte
2'nd Byte
Instruction3
Instruction2
Execution Time
Instruction3
Execution Time
Continuous Read Operation
SCLK
SID
SOD
Wait
Wait
Wait
Start
Byte
Data
Read1
Instruction1
Execution Time
Data
Read2
Instruction2
Execution Time
Data
Read3
Instruction3
Execution Time
Figure 12. Timing Diagram of Continuous Data Transfer
47
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
APPLICATION INFORMATION ACCORDING TO LCD PANEL
LCD Panel: 48 Character x 1-line Format (5-dot Font,1/17 Duty)
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM17
(COM0)
S6A0078
♠♣
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG118
SEG119
SEG120
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
LCD Panel: 48 Character x 2-line Format (5-dot Font, 1/33 Duty)
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM33
(COM0)
S6A0078
SEG1
SEG2
SEG3
SEG4
SEG5
SEG118
SEG119
SEG120
COM32
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
48
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
LCD Panel: 24 Character x 4-line Format (5-dot Font, 1/33 Duty)
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
S6A0078
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
(COM0)
SEG1
SEG2
SEG3
SEG4
SEG5
SEG118
SEG119
SEG120
LCD Panel: 20 Character x 4-line Format (6-dot Font, 1/33 Duty)
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
S6A0078
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
(COM0)
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG118
SEG119
SEG120
49
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
INITIALIZING
INITIALIZING BY INTERNAL RESET CIRCUIT
When the power is turned on, S6A0078 is initialized automatically by power on reset circuit. During the
initialization, the following instructions are executed, and BF(Busy Flag) is kept "High" (busy state) to the end of
initialization.
Display Clear instruction
Write "20H" to all DDRAM
Set Functions instruction
DL = 1: 8-bit bus mode
N = 1: 2-line display mode
RE = 0: Extension register disable
BE = 0: CGRAM/SEGRAM blink OFF
DH = 0: Horizontal scroll enable
REV = 0: Normal display (Not reversed display)
Control Display ON/OFF instruction
D = 0: Display OFF
C = 0: Cursor OFF
B = 0: Blink OFF
Set Entry Mode instruction
I/D = 1: Increment by 1
S = 0: No entire display shift
BID = 0: Normal direction segment port
Set Extension Function instruction
FW = 0: 5-dot font width character display
B/W = 0: Normal cursor (8th line)
NW = 0: Not 4-line display mode, 2-line mode is set because of N ("1")
Enable Shift instruction
HS = 0000: Scroll per line disable
DS = 0000: Shift per line disable
Set scroll Quantity instruction
SQ = 000000: Not scroll
INITIALIZING BY HARDWARE RESET INPUT
When RESET pin = "Low", S6A0078 can be initialized like the case of power on reset. During the power on reset
operation, this pin is ignored.
50
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
INITIALIZING BY INSTRUCTION
8-BIT INTERFACE MODE
Power On
Wait for more than 20ms after
VDD rises to 4.5V
Wait for more than 30ms after
VDD rises to 2.7V
Condition: fosc = 270kHz
(DL = "1")
Function Set
0
4-bit interface
1
8-bit interface
0
1-line mode
1
2-line mode
0
Display off
1
Display on
0
Cursor off
1
Cursor on
0
Blink off
1
Blink on
0
Decrement mode
1
Increment mode
0
Entire shift off
1
Entire shift on
DL
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
DL(1)
N
0
x
x
N
Wait for more than 39µs
D
Display ON/OFF Control
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C
0
0
0
0
0
0
1
D
C
B
B
Wait for more than 39µs
Clear Display
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
1
Wait for more than 1.53sms
Entry Mode Set
I/D
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
1
I/D
S
S
Initialization End
51
S6A0078
4-BIT INTERFACE MODE
52
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
Power On
Wait for more than 20ms after
VDD rises to 4.5V
Wait for more than 30ms after
VDD rises to 2.7V
Condition: fosc = 270kHz
(DL = "0")
Function Set
RS
0
R/W DB7
0
0
0
4-bit interface
1
8-bit interface
0
1-line mode
1
2-line mode
0
Display off
1
Display on
0
Cursor off
1
Cursor on
0
Blink off
1
Blink on
0
Decrement mode
1
Increment mode
0
Entire shift off
1
Entire shift on
DL
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
DL(0)
x
x
x
x
N
Wait for more than 39 µ s
Function Set
RS
R/W DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
0
x
x
x
x
0
0
N
x
x
x
x
x
x
x
Wait for more than 39 µ s
D
Display ON/OFF Control
RS
R/W DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C
0
0
0
0
0
0
x
x
x
x
0
0
1
D
C
B
x
x
x
x
B
Wait for more than 39 µ s
Display Clear
RS
R/W DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
x
x
x
x
0
0
0
0
0
1
x
x
x
x
Wait for more than 1.53 ms
Entry Mode Set
I/D
RS
0
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
x
x
x
x
S
0
0
0
1
I/D
S
x
x
x
x
Initialization End
53
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
EXAMPLE OF INSTRUCTION AND DISPLAY CORRESPONDENCE
IE = LOW
1. Power supply on: Initialized by the internal power on reset circuit
RS
R/W DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
1
0
0
X
X
LCD DISPLAY
2. Function Set: 8-bit, 1-line
RS
0
R/W DB7
0
0
3. Display ON/OFF Control: Display/Cursor on
RS
R/W DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
1
1
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
1
0
_
0
0
0
4. Entry Mode Set: Increment
RS
R/W DB7
_
0
0
0
5. Write Data to DDRAM: Write S
RS
R/W DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
1
0
0
1
1
S_
1
0
0
6. Write Data to DDRAM: Write A
RS
R/W DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
1
SA_
1
0
0
7. Write Data to DDRAM: Write M
RS
R/W DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
1
0
1
SAM_
1
0
0
8. Write Data to DDRAM: Write S
RS
R/W DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
1
0
0
1
1
SAMS_
1
54
0
0
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
9. Write Data to DDRAM: Write U
LCD DISPLAY
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
0
1
0
1
0
1
SAMSU_
10. Write Data to DDRAM: Write N
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
0
0
1
1
1
0
SAMSUN_
11. Write Data to DDRAM: Write G
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
0
0
0
1
1
1
SAMSUNG_
12. Cursor or Display Shift: Cursor shift to right
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
0
1
X
X
SAMSUNG _
13. Entry Mode Set: Entire Display Shift Enable
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
1
1
1
SAMSUNG _
14. Write Data to DDRAM: Write K
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
0
0
1
0
1
1
AMSUNG K_
15. Write Data to DDRAM: Write S
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
0
1
0
0
1
1
MSUNG KS_
16. Write Data to DDRAM: Write 0
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
1
1
0
0
0
0
SUNG KS0_
55
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
17. Write Data to DDRAM: Write 0
LCD DISPLAY
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
1
1
0
0
0
0
UNG KS00_
18. Write Data to DDRAM: Write 7
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
1
1
0
1
1
1
NG KS007_
19. Write Data to DDRAM: Write 3
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
1
1
0
0
1
1
G KS0073_
20. Cursor or Display Shift: Cursor shift left
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
0
0
x
x
G KS0073
21. Write Data to DDRAM: Write 8
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
1
1
1
0
0
0
KS0078_
22. Return Home
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
1
x
SAMSUNG KS0078
23. Clear Display
56
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
1
_
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
IE = HIGH
1. Power Supply On: Initialized by the internal power on reset circuit
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
2. Function Set: 8-bit, RE(1)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
1
1
1
0
0
3. Extended Function Set: 5-font, 4-line
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
1
0
0
1
4. Function Set: RE(0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
1
1
0
0
0
5. Display ON/OFF Control: Display/Cursor on
_
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
1
1
1
0
6. Write Data to DDRAM: Write S
S_
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
0
1
0
0
1
1
57
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
7. Write Data to DDRAM: Write A
SA_
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
0
0
0
0
0
1
12. Write Data to DDRAM: Write G
SAMSUNG_
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
0
0
0
1
1
1
13. Set DDRAM Address 20H
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
0
0
0
0
14. Write Data to DDRAM: Write K
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
0
0
1
0
1
1
19. Write Data to DDRAM: Write 8
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
1
1
1
0
0
0
20. Set DDRAM Address 40H
58
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
0
0
0
0
0
0
SAMSUNG
_
SAMSUNG
K_
SAMSUNG
KS0078_
SAMSUNG
KS0078
_
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
21. Write Data to DDRAM: Write L
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
0
0
1
1
0
0
30. Write Data to DDRAM: Write R
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
0
1
0
0
1
0
31. Set DDRAM Address 20H
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
0
0
0
0
43. Write Data to DDRAM: Write R
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
0
1
0
0
1
0
44. Function Set: RE("0"), DH("1")
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
1
1
0
1
0
45. Function Set: RE("1")
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
1
1
1
0
0
SAMSUNG
KS0078
L_
SAMSUNG
KS0078
LCD DRIVER_
SAMSUNG
KS0078
LCD DRIVER
_
SAMSUNG
KS0078
LCD DRIVER
& CONTROLLER_
SAMSUNG
KS0078
LCD DRIVER
& CONTROLLER_
SAMSUNG
KS0078
LCD DRIVER
& CONTROLLER_
59
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
46. Shift/Scroll Enable: DS4("1"), DS3/2/1("0")
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
1
0
0
0
47. Function Set: RE("0")
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
1
1
0
1
0
48. Cursor or Display Shift: Display shift to left
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
1
0
x
x
49. Cursor or Display Shift: Display shift to left
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
1
0
x
x
50. Cursor or Display Shift: Display shift to left
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
1
0
x
x
51. Cursor or Display Shift: Display shift to left
60
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
1
0
x
x
SAMSUNG
KS0078
LCD DRIVER
& CONTROLLER_
SAMSUNG
KS0078
LCD DRIVER
& CONTROLLER_
SAMSUNG
KS0078
LCD DRIVER
CONTROLLER_
SAMSUNG
KS0078
LCD DRIVER
CONTROLLER_
SAMSUNG
KS0078
LCD DRIVER
ONTROLLER_
SAMSUNG
KS0078
LCD DRIVER
NTROLLER_
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
52. Return Home
RS
0
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
x
53. Function Set: RE("0), REV("1")
RS
0
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
1
1
0
1
1
54. Cursor or Display Shift: Display shift to right
RS
0
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
x
x
55. Cursor or Display Shift: Display shift to right
RS
0
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
x
x
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
x
56. Return Home
RS
0
R/W DB7
0
0
57. Function Set: RE("0"), REV("0")
RS
0
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
1
1
0
0
0
SAMSUNG
KS0078
LCD DRIVER
& CONTROLLER
SAMSUNG
KS0078
LCD DRIVER
& CONTROLLER
SAMSUNG
KS0078
LCD DRIVER
& CONTROLLER
SAMSUNG
KS0078
LCD DRIVER
& CONTROLLER
SAMSUNG
KS0078
LCD DRIVER
& CONTROLLER
SAMSUNG
KS0078
LCD DRIVER
& CONTROLLER
61
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
58. Function Set: RE("1")
RS
0
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
1
1
1
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
1
1
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
1
SAMSUNG
KS0078
LCD DRIVER
& CONTROLLER
59. Entry Mode Set: BID("1")
RS
0
R/W DB7
0
0
60. Clear Display
0
R/W DB7
0
0
61. Write Data to DDRAM: Write B
RS
1
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
1
0
62. Write Data to DDRAM: Write I
RS
0
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
x
63. Write Data for DDRAM: Write D
RS
1
62
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
1
0
0
_
RS
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
FRAME FREQUENCY
1/17 DUTY CYCLE
1-line selection period
1
2
3
4
...
16 17
1
2
3
...
16 17
VDD
..
V1
COM1
V4
V5
1 Frame
1 Frame
Display Font Width
Item
5-Dot Font Width
6-Dot Font Width
240 clocks
288 clocks
66.2Hz
55.1Hz
1-line selection period
Frame frequency
fosc = 270kHz (1 clock = 3.7µs)
1/33 DUTY CYCLE
1-line selection period
1
2
3
4
...
32 33
1
2
3
...
32 33
VDD
..
V1
COM1
V4
V5
1 Frame
Item
1-line selection period
Frame frequency
1 Frame
Display Font Width
5-Dot Font Width
6-Dot Font Width
120 clocks
144 clocks
68.2Hz
56.8Hz
fosc = 270kHz (1 clock = 3.7µs)
63
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
POWER SUPPLY FOR DRIVING LCD PANEL
WHEN AN EXTERNAL POWER SUPPLY IS USED
VDD
VDD
V1
V2
V3
V4
V5
R
R
R0
R
R
VEE
WHEN AN INTERNAL BOOSTER IS USED
Boosting Twice
Boosting Three Times
VDD
VDD
+
1µF +-
1µF +
Vci
VDD
GND
V1
C1
V2
C2
V3
V5OUT2
V4
V5OUT3
V5
Can be detached if
not using power
down mode
R
R
R0
R
R
+
1µF +-
1µF +
1µF +
Vci
VDD
GND
V1
C1
V2
C2
V3
V5OUT2
V4
V5OUT3
V5
R
R
R0
R
R
Can be detached if
not using power
down mode
•
Boosted output voltage should not exceed the maximum value (13V) of the LCD driving voltage.
Especially, a voltage of over 4.3V should not be input to the reference voltage (Vci) when boosting three
times.
•
A voltage of over 5.5V should not be input to the reference voltage (Vci) when boosting twice.
•
The value of resistance, according to the number of lines, duty ratio and the bias, is shown below.
(refer to Table 13)
64
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
Table 13. Duty Ratio and Power Supply for LCD Driving
Item
Data
Number of lines
1
2 or 4
Duty ration
1/17
1/33
Bias
1/5
1/6.7
R
R
R
R0
R
2.7R
Divided resistance
MAXIMUM ABSOLUTE RATE
Characteristic
Symbol
Value
Unit
Power supply voltage (1)
VDD
-0.3 to +7.0
V
Power supply voltage (2)
VLCD
VDD -15.0 to VDD +0.3
V
VIN
-0.3 to VDD +0.3
V
Operating temperature
TOPR
-30 to +85
°C
Storage temperature
TSTG
-55 to +125
°C
Input voltage
Voltage greater than above may damage to the circuit (VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5)
65
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (VDD = 2.7V to 5.5V, Ta = -30 to +85°°C)
Characteristic
Symbol
Condition
Min
Typ
Max
Unit
Operating voltage
VDD
-
2.7
-
5.5
V
Supply current
IDD
Internal oscillation or external
clock.
(VDD = 3.0V, fosc = 270kHz)
-
0.15
0.3
mA
VIH1
-
0.7VDD
-
VDD
VDD = 2.7 to 3.0
-0.3
-
0.2VDD
VDD = 3.0 to 5.5
-0.3
-
0.6
Input voltage (1)
(except OSC1)
VIL1
-
Input voltage (2)
VIH2
-
0.7VDD
-
VDD
(OSC1)
VIL2
-
-
-
0.2VDD
Output voltage (1)
VOH1
IOH=-0.1mA
0.75VDD
-
-
(DB0 to DB7)
VOL1
IOL = 0.1 mA
-
-
0.2VDD
Output voltage (2)
VOH2
IO = -40µA
0.8VDD
-
-
(except DB0 to DB7)
VOL1
IO =40µA
-
-
0.2VDD
-
-
1
-
-
1
VIN = 0V to VDD
-1
-
1
IIL
VIN = 0V, VDD = 3V (pull up)
-10
-50
-120
f OSC
Rf = 91kΩ ± 2% (VDD = 5V)
190
270
350
KHz
125
270
410
KHz
45
50
55
%
-
-
0.2
µs
-3.0
-4.2
-
Voltage DROP
Input leakage current
Low input current
Internal clock
(external Rf)
VdCOM
VdSEG
ILKG
IO = ± 0.1mA
duty
-
t R, t F
Voltage converter out2
(Vci = 4.5V)
VOUT2
Voltage converter out3
(Vci = 2.7V)
VOUT3
Voltage converter input
Vci
LCD driving voltage
66
VLCD
Ta = 25°C, C = 1µF,
IOUT = 0.25mA,
f OSC = 270kHz
V
µA
V
-4.3
-5.1
-
2.5
-
4.5
1/5 bias
3.0
-
13.0
1/6.7 bias
3.0
-
13.0
VDD - V5
V
V
f EC
External clock
V
V
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0078
AC CHARACTERISTICS (VDD = 4.5 to 5.5V, Ta=-30 to +85°C)
Table 14. AC Characteristics
Mode
Item
Symbol
Min
Typ
Max
tc
500
-
-
tr, tf
-
-
20
E pulse width (high, low)
tw
230
-
-
R/W and RS setup time
tsu1
40
-
-
R/W and RS hold time
th1
10
-
-
Data setup time
tsu2
60
-
-
Data hold time
th2
10
-
-
tc
500
-
-
tr, tf
-
-
20
E pulse width (high, low)
tw
230
-
-
R/W and RS setup time
tsu
40
-
-
R/W and RS hold time
th
10
-
-
Data output delay time
tD
-
-
160
Data hold time
tDH
5
-
-
tc
0.5
-
20
tr, tf
-
-
50
tw
200
-
-
E cycle time
E rise/fall time
(1) Write mode
(refer to Figure 13)
E cycle time
E rise/fall time
(2) Read mode
(refer to Figure 14)
Serial clock cycle time
Serial clock rise/fall time
Serial clock width (high, low)
(3) Serial interface
Chip select setup time
tsu1
60
-
-
mode
Chip select hold time
th1
20
-
-
(refer to Figure 15)
Serial input data setup time
tsu2
100
-
-
Serial input data hold time
th2
100
-
-
Serial output data delay time
tD
-
-
160
Serial output data hold time
tDH
5
-
-
Unit
ns
ns
µs
ns
67
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
TABLE 14. AC CHARACTERISTICS (VDD = 2.7 to 4.5V, Ta=-30 to +85°C)
Mode
Item
Symbol
Min
Typ
Max
tc,
1000
-
-
tr, tf
-
-
25
E pulse width (high, low)
tw
450
-
-
R/W and RS setup time
tsu1
60
-
-
R/W and RS hold time
th1
20
-
-
Data setup time
tsu2
195
-
-
Data hold time
th2
10
-
-
tc
1000
-
-
tr, tf
-
-
25
E pulse width (high, low)
tw
450
-
-
R/W and RS setup time
tsu
60
-
-
R/W and RS hold time
th
20
-
-
Data output delay time
tD
-
-
360
Data hold time
tDH
5
-
-
tc
1
-
20
tr, tf
-
-
50
tw
400
-
-
E cycle time
E rise/fall time
(4) Write mode
(refer to Figure 13)
E cycle time
E rise/fall time
(5) Read mode
(refer to Figure 14)
Serial clock cycle time
Serial clock rise/fall time
Serial clock width (high, low)
(6) Serial interface
Chip select setup time
tsu1
60
-
-
mode
Chip select hold time
th1
20
-
-
(refer to Figure 15)
Serial input data setup time
tsu2
200
-
-
Serial input data hold time
th2
200
-
-
Serial output data delay time
tD
-
-
360
Serial output data hold time
tDH
5
-
-
68
Unit
ns
ns
µs
µs
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
RS
VIH1
VIL1
tsu1
R/W
S6A0078
th1
VIL1
VIL1
th1
tw
tf
VIH1
VIL1
E
VIH1
VIL1
tsu2
tr
VIH1
VIL1
DB0 - DB7
VIL1
th2
VIH1
VIL1
Valid Data
tc
Figure 13. Write Mode
RS
R/W
VIH1
VIL1
tsu
th
VIH1
VIH1
th
tw
tf
E
tr
DB0 - DB7
VIH1
VIL1
VIH1
VIL1
tD
VOH1
VOL1
VIL1
tDH
Valid Data
tc
VOH1
VOL1
Figure 14. Read Mode
69
S6A0078
120 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
tC
CS
SCLK
VIL1
tsu1
tr
tw
VIL1
th1
tw
tf
VIH1
VIL1
tsu2
VIH1 VIH1
VIL1 VIL1
th2
VIH1
VIL1
SID
tD
tDH
VOH1
VOL1
SOD
Figure 15. Serial Interface Mode
Reset Timing (VDD = 2.7 to 5.5V, Ta = -30 to +85°°C)
Item
Symbol
Min
Typ
Max
Unit
tRES
10
-
-
ms
Reset low level width (refer to Figure 16)
tRES
RESET
VIL1
VIL1
Figure 15. Reset Timing Diagram
70