SAMSUNG S6A0032

S6A0032
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
June. 1999.
Ver. 0.5
Prepared by:
Tae-Kwang, Park
[email protected]
Contents in this document are subject to change without notice. No part of this document may be reproduced or
transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written
permission of LCD Driver IC Team.
S6A0032
PRELIMINARY SPEC. VER. 0.5
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
S6A0032 Specification Revision History
Version
0.0
0.1
Content
Original
Date
Feb.1999
ECKON pad added
POR circuit added
Mar.1999
Page 5: (4/5) x V0 → (3/5) x V0
(3/5) x V0 → (2/5) x V0
Page 6: E_RD signal description is changed
0.2
E_RD: Active low signal for writing command in 6800 mode or high enable
signal for reading command in 8080 mode. →
E_RD: Active low signal for writing command or high enable signal for reading
command in 6800 mode, low enable signal for reading command in
Apr.1999
8080 mode.
Page 6: LCD DRIVER OUTPUT added
0.3
Page 18: Power ON / OFF timing added
Page 29: IDD1 (VDD = 2.4~3.6V): 150µA → 50µA
May.1999
Page 30: IDD1 (VDD = 3.6~5.5V): 250µA → 80µA
0.4
Page 1, 2, 11: CGROM character size is changed from 256 to 254.
Jun.1999
Page 6: RW_WR active low -> active high
0.5
2
Page 6: RW_WR active low -> low enable
Page 20: Wait for more than 1.2us or Busy Check -> delete “ or Busy Check”
Page 21: Wait for more than 1.2us or Busy Check -> delete “ or Busy Check”
Jun.1999
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0032
CONTENTS
INTRODUCTION.......................................................................................................................................... 1
FEATURES ................................................................................................................................................. 1
BLOCK DIAGRAM ...................................................................................................................................... 2
PAD CONFIGURATION............................................................................................................................... 3
PAD CENTER COORDINATES ................................................................................................................... 4
PIN DESCRIPTION...................................................................................................................................... 5
POWER SUPPLY ................................................................................................................................. 5
SYSTEM CONTROL ............................................................................................................................ 5
MPU INTERFACE ................................................................................................................................ 6
LCD DRIVER OUTPUT ........................................................................................................................ 6
TEST.................................................................................................................................................... 6
FUNCTIONAL DESCRIPTION..................................................................................................................... 7
MICROPROCESSOR INTERFACE ...................................................................................................... 7
ADDRESS COUNTER (AC)................................................................................................................ 10
DISPLAY DATA RAM (DDRAM) ......................................................................................................... 10
CHARACTER GENERATOR ROM (CGROM)..................................................................................... 11
CHARACTER GENERATOR RAM (CGRAM) ..................................................................................... 12
LCD DRIVER CIRCUIT....................................................................................................................... 13
INSTRUCTION DESCRIPTION.................................................................................................................. 14
INITIALIZING............................................................................................................................................. 18
HARDWARE RESET .......................................................................................................................... 18
INSTRUCTION INITIALIZING WITH RESET....................................................................................... 20
LCD DRIVING POWER SUPPLY CIRCUIT................................................................................................ 22
MPU INTERFACE...................................................................................................................................... 23
INTERFACING WITH 8080-SERIES MICROPROCESSORS.............................................................. 23
INTERFACING WITH 6800-SERIES MICROPROCESSORS.............................................................. 23
APPLICATION INFORMATION FOR LCD PANEL .................................................................................... 24
FRAME FREQUENCY ............................................................................................................................... 28
MAXIMUM ABSOLUTE RATE................................................................................................................... 29
ELECTRICAL CHARACTERISTICS .......................................................................................................... 30
DC CHARACTERISTICS .................................................................................................................... 30
AC CHARACTERISTICS .................................................................................................................... 32
3
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0032
INTRODUCTION
This character driver and controller LSI for liquid crystal dot matrix display systems can display 2-line of 16
characters with the 5 x 8 dots format. It is capable of interfacing various microprocessors, supporting the 4-bit or
8-bit parallel mode. Voltage follower and bias circuit is built in the IC.
FEATURES
Driver Output Circuits
−
16 common outputs / 80 segment outputs
Applicable Duty Ratio
Font size
Display size
Duty
Contents of outputs
5x8
2-line x 16 characters
1/16
2 x 16 characters
On-chip Display Data RAM
−
−
−
Character Generator ROM (CGROM): 10,160 bits (254 characters x 5 x 8 dots)
Character Generator RAM (CGRAM): 80 bits (2 characters x 5 x 8 dots)
Display Data RAM (DDRAM): 256 bits (16 characters x 2-line)
Microprocessor Interface
−
−
8-bit parallel interface with 6800-series or 8080-series MPU
4-bit parallel interface with 6800-series or 8080-series MPU
Function Set
−
−
−
Simple instruction set
COM / SEG bi-directional (4 types of LCD application available)
Hardware reset (RESETB)
On-chip Analog Circuit
−
−
−
Internal RC oscillator circuit
Voltage follower & bias circuit
Automatic power on reset circuit
Operating Voltage Range
−
−
Supply voltage (VDD): 2.4 to 5.5V
LCD driving voltage (VLCD = V0 - VSS): 6.0V Max.
Low Power Consumption
Package Type
−
Gold bumped chip
1
S6A0032
PRELIMINARY SPEC. VER. 0.5
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
BLOCK DIAGRAM
ECKON
CK
DIRC
Power On
Reset (POR)
Oscillator
RESETB
MI
8
Input Buffer
CSB
RS
RW_WR
E_RD
Parallel
Interface
4-/8-bit
(6800/8080
-series)
DB7 to
DB4
Instruction
Register
(IR)
Data
Register
(DR)
8 Data Output
Register
(OR)
DB3 to
DB0
Instruction
Decoder
Address
Counter
8
16 bits
Shift
Register
Display
Data RAM
(DDRAM)
256 bits
COM1 to
Common COM16
Driver
5
8
8
80 bits
Shift
Register
8
5
Busy
Flag
Timing Generator
80 bits
Latch
Circuit
SEG1 to
Segment SEG80
Driver
5
Character
Generator
RAM
(CGRAM)
80 bits
Character
Generator
ROM
(CGROM)
10,160 bits
Cursor
and
Blink
Controller
LCD Driving
Voltage Selector
VDD
5
5
Voltage Follower
& Bias Resistor
GND
Segment Data Conversion
DIRS
Figure 1. Block Diagram
2
V0 V1 V2 V3 V4
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0032
PAD CONFIGURATION
60
129
z
130
59
Y
S6A0032
136
137
X
(0,0)
144
53
52
45
44
1
PAD
DUMMY_PAD
Figure 2. S6A0032 Chip Configuration
Table 1. S6A0032 Pad Dimensions
Item
Pad No.
Chip size
-
Pad pitch
Bumped pad size
Bumped pad
height
Size
X
Y
5430
1410
1 to 44
90
45 to 144
70
1 to 44
52
92
45 to 59
92
42
60 to 129
42
92
130 to 144
92
42
1 to 144
Unit
µm
17 (Typ.)
COG Align Key Coordinate
30µm 30µm 30µm
(+2600, +590)
60µm
30µm 30µm 30µm
30µm
(-2600, +605)
30µm 30µm 30µm
3
S6A0032
PRELIMINARY SPEC. VER. 0.5
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PAD CENTER COORDINATES
Table 2. Pad Center Coordinates
[Unit: µm]
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
4
Name
DUMMY
VSS
VSS
VSS
ECKON
VDD
V4
V3
V2
V1
CK
VDD
VDD
VDD
V0
V0
VDD
VDD
VDD
RESETB
RS
RW_WR
VSS
E_RD
VDD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
CSB
VSS
MI
VDD
TEST
VSS
DIRC
VDD
DIRS
VSS
DUMMY
COM1
COM2
COM3
COM4
COM5
COM6
X
-1935
-1845
-1755
-1665
-1575
-1485
-1395
-1305
-1215
-1125
-1035
-945
-855
-765
-675
-585
-495
-405
-315
-225
-135
-45
45
135
225
315
405
495
585
675
765
855
945
1035
1125
1215
1305
1395
1485
1575
1665
1755
1845
1935
2605
2605
2605
2605
2605
2605
Y
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-595
-555
-485
-415
-345
-275
-205
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Name
COM7
COM8
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
DUMMY
DUMMY
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
X
2605
2605
2605
2605
2605
2605
2605
2605
2605
2415
2345
2275
2205
2135
2065
1995
1925
1855
1785
1715
1645
1575
1505
1435
1365
1295
1225
1155
1085
1015
945
875
805
735
665
595
525
455
385
315
245
175
105
35
-35
-105
-175
-245
-315
-385
Y
-135
-65
5
75
145
215
285
355
425
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Name
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
DUMMY
DUMMY
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
X
-455
-525
-595
-665
-735
-805
-875
-945
-1015
-1085
-1155
-1225
-1295
-1365
-1435
-1505
-1575
-1645
-1715
-1785
-1855
-1925
-1995
-2065
-2135
-2205
-2275
-2345
-2415
-2605
-2605
-2605
-2605
-2605
-2605
-2605
-2605
-2605
-2605
-2605
-2605
-2605
-2605
-2605
Y
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
595
425
355
285
215
145
75
5
-65
-135
-205
-275
-345
-415
-485
-555
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0032
PIN DESCRIPTION
POWER SUPPLY
Table 3. Pin Description
Name
I/O
Description
VDD
Supply
Power supply
VSS
Supply
Ground
V0
I
Bias voltage Input for LCD driving
LCD driving voltage outputs.
Voltages should have the following relationship;
V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
V1
V2
V3
O
V4
These voltages are generated as following table.
LCD bias
V1
V2
V3
V4
1/5 bias
(4/5) x V0
(3/5) x V0
(2/5) x V0
(1/5) x V0
SYSTEM CONTROL
Table 3. Pin Description (Continued)
Name
I/O
Description
ECKON
I
Clock source selection input
When ECKON = "High", External clock by CK pin is used as system clock, and internal
oscillator circuit is turned OFF. When ECKON = "Low", internal oscillator is used.
CK
I
MI
I
DIRC
DIRS
External clock input (When ECKON = "High")
It must be fixed "High" or "Low" when the internal oscillation circuit is used (When
ECKON = "Low").
MPU interface selection input
MI = "Low", 8080-series MPU
MI = "High", 6800-series MPU
I
COM direction selection input
When DIRC = "Low",
COM1 → COM2 - - - - → COM15 → COM16
When DIRC = "High",
COM16 → COM15 - - - - → COM2 → COM1
I
SEG direction selection input
When DIRS = "Low",
SEG1 → SEG2 - - - - → SEG79 → SEG80
When DIRS = "High",
SEG80 → SEG79 - - - - → SEG2 → SEG1
5
S6A0032
PRELIMINARY SPEC. VER. 0.5
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
MPU INTERFACE
Table 3. Pin Description (Continued)
Name
I/O
RESETB
I
Reset input
Initialization is performed by "Low" level sensing of the RESETB signal.
CSB
I
Chip selection input
S6A0032 is selected while CSB is "Low".
RS
I
Register selection input
When RS = "Low", instruction register
When RS = "High", data register
I
In 8080-series MPU interface mode, this pin is connected to WR pin of MPU and is an
active high write signal.
In 6800-series MPU interface mode, this pin is connected to R/W pin of MPU.
When RW_WR = "High", read mode
When RW_WR = "Low", write mode
I
In 8080-series MPU interface mode, this pin is connected to RD pin of MPU and is a low
enable read signal.
In 6800-series MPU interface mode, this pin is connected to E pin of MPU and enables
read or write command according to RW_WR signal.
RW_WR
E_RD
DB0 to DB3
DB4 to DB7
I/O
Description
When 8-bit interface mode, used as bi-directional data bus DB0 to DB7
During 4-bit bus mode, only DB4 to DB7 are used. In this case DB0 - DB3 pins are
don’ t care (connect to "High", "Low" or open).
LCD DRIVER OUTPUT
Table 3. Pin Description (Continued)
Name
I/O
Description
COM1 to
COM16
O
Common signal output for character display
SEG1 to
SEG80
O
Segment signal output for character display
TEST
Table 3. Pin Description (Continued)
Name
I/O
TEST
I
Description
Test pin
This pin is not used for normal operation and should be connect to "Low".
*NOTE: DUMMY – These pins should be opened (floated).
6
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0032
FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
S6A0032 has two kinds of interface type with MPU: 4-bit bus or 8-bit bus. 4-bit bus and 8-bit bus is selected by the
DL bit in the instruction register, and 6800-series MPU or 8080-series MPU is selected by MI pin.
Table 4. Various Kinds of MPU Interface according to MI and DL Bit
MI
DL
CSB
RS
RW_WR
E_RD
DB0 to DB3
DB4 to DB7
6800
series (H)
8-bit (H)
CSB
RS
R/W
E
DB0 to DB3
DB4 to DB7
4-bit (L)
CSB
RS
R/W
E
-
DB4 to DB7
8080
series (L)
8-bit (H)
CSB
RS
WR
RD
DB0 to DB3
DB4 to DB7
4-bit (L)
CSB
RS
WR
RD
-
DB4 to DB7
NOTE: "-" - Don’t care ("High", "Low" or Open)
(H): fixed "High" (VDD)
(L): fixed "Low" (VSS)
MI: "High" = 6800-series MPU, "Low" = 8080-series MPU
DL: "High" = 8-bit mode, "Low" = 4-bit mode
CSB: "High" = chip is not selected, "Low" = chip is selected
RS: "High" = data register, "Low" = instruction register
RW_WR: read / write indicating signal in 6800 mode, active high signal for writing command in 8080 mode.
E_RD: Active low signal for writing command or high enable signal for reading command in 6800 mode,
low enable signal for reading command in 8080 mode.
Parallel Interface
During writing operation, two 8-bit registers, data register (DR) and instruction register (IR), are used. The data
register (DR) is used as temporary data storage place for being written into DDRAM / CGRAM. Target RAM is
selected by RAM address set instruction. The Instruction register (IR) is used only to store instruction code
transferred from MPU. To select DR or IR register, RS input pin is used.
During reading operation, 8-bit output data register (OR) is used. The output data register (OR) is used as temporary
data storage place for being read from DDRAM / CGRAM. Destination RAM is selected by RAM address set
instruction. After RAM address set, the first reading in the 8-bit bus mode (first and second reading in the 4-bit bus
mode) is a dummy cycle (figure 3, 4, 5, 6). The valid data comes from the second reading in the 8-bit bus mode (from
the 3rd reading in 4-bit bus mode). The dummy cycle makes the address counter (AC) indicate the correct address.
So it is recommended to set address before writing. The instruction read operation is supported for indicating
internal operation is being processed (Busy Flag).
In the 4-bit bus mode, it is needed to transfer 4-bit data (through DB4 to DB7) by two times. The high order bits (for
8-bit mode DB4 to DB7) are transferred before the low order bits (for 8-bit mode DB0 to DB3) in read and write
transaction. The DB0 to DB3 pins are floated in this 4-bit bus mode.
After RESETB operation, S6A0032 considers the first 4-bit data from MPU as the high order bits in the 4-bit bus
mode.
7
S6A0032
PRELIMINARY SPEC. VER. 0.5
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
DL
MI
CSB
RS
RW_WR
E_RD
Valid
Data
DB7 to DB0
Instruction
W rite
Busy Flag
Read
Dummy
Data Read
Valid
Data Read
Data
W rite
Figure 3. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (6800-series MPU Mode)
DL
MI
CSB
RS
RW_WR
E_RD
Valid
Data
DB7 to DB0
Instruction
W rite
Busy Flag
Read
Dummy
Data Read
Valid
Data Read
Data
W rite
Figure 4. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (8080-series MPU Mode)
8
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0032
DL
MI
CSB
RS
RW_WR
E_RD
DB7 to DB0
Upper
4-bit
Lower
4-bit
Instruction W rite
BF
A3 A0
Busy Flag &
Address Read
D7 D4
Dummy
Data Read
D3 D0
Valid
Data Read
D7 D4
D3 D0
Data W rite
Figure 5. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (6800-series MPU Mode)
DL
MI
CSB
RS
RW_WR
E_RD
DB7 to DB0
Upper
4-bit
Lower
4-bit
Instruction W rite
BF
A3 A0
Busy Flag &
Addr ess Read
D7 D4
Dummy
Data Read
D3 D0
Valid
Data Read
D7 D4
D3 D0
Data W rite
Figure 6. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (8080-series MPU Mode)
Busy Flag
When DB7 is "High" in read status operation, it indicates that the internal operation is in busy status and can accept
only read status instruction. If the cycle time is correct, the microprocessor needs not to check this flag before each
instruction, except display clear instruction.
9
S6A0032
PRELIMINARY SPEC. VER. 0.5
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
ADDRESS COUNTER (AC)
Address Counter (AC) in S6A0032 stores DDRAM / CGRAM address. After writing into or reading from DDRAM /
CGRAM, AC is automatically increased or decreased by 1 according to the entry mode.
DISPLAY DATA RAM (DDRAM)
DDRAM stores display data of maximum 32 x 8 bits (32 characters). DDRAM address is set in the address counter
(AC) as a hexadecimal number.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
00
01
02
03
04
05
06
07
08
09
0A
0B
0C 0D 0E
0F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C 4D 4E
4F
(a) Display shift is not performed
1
2
3
4
5
6
7
8
9
10
11
01
02
03
04
05
06
07
08
09
0A
0B
41
42
43
44
45
46
47
48
49
4A
4B
12
13
14
15
16
0C 0D 0E
0F
00
4C 4D 4E
4F
40
15
16
(b) Display shift left is performed
1
2
3
4
5
6
7
8
9
10
11
12
13
0F
00
01
02
03
04
05
06
07
08
09
0A
0B
0C 0D 0E
4F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C 4D 4E
(c) Display shift right is performed
Figure 7. DDRAM Address
10
14
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0032
CHARACTER GENERATOR ROM (CGROM)
CGROM has 5 x 8-dot 254 characters. The CGROM character code 00h and 01h are CGRAM character data area.
Table 5. CGROM Character Code (00)
11
S6A0032
PRELIMINARY SPEC. VER. 0.5
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
CHARACTER GENERATOR RAM (CGRAM)
CGRAM has up to 5 x 8-dot 2 characters. By writing font data to CGRAM, user defined character can be used.
Table 6. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM)
Character code
(DDRAM data)
CGRAM address
CGRAM data
D7 D6 D5 D4 D3 D2 D1 D0
A3 A2 A1 A0
P7 P6 P5 P4 P3 P2 P1 P0
0 0 0 0 0 0 0 0
(00h)
0 0 0 0 0 0 0 1
(01h)
NOTE: "-" - Don’t care
12
Pattern
number
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-
-
-
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
Pattern 1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-
-
-
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Pattern 2
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0032
LCD DRIVER CIRCUIT
LCD Driver circuit has 16 common and 80 segment signals for driving LCD. Data from CGRAM / CGROM are
transferred to 80-bit segment register serially, and then they are stored to 80-bit shift latch. COM1 to COM16 have
1/16 duty ratio. SEG bi-directional function is selected by DIRS input, and COM shift direction is selected by DIRC
input.
Table 7. SEG Data Shift Direction
DIRS pin
SEG data shift direction
Low
SEG1 → SEG2 → SEG3 → - - - - - - - → SEG78 → SEG79 → SEG80
High
SEG80 → SEG79 → SEG78 → - - - - - - - → SEG3 → SEG2 → SEG1
Table 8. COM Data Shift Direction
DIRC pin
COM data shift direction
Low
COM1 → COM2 → COM3 → - - - - - - - - → COM14 → COM15 → COM16
High
COM16 → COM15 → COM14 → - - - - - - - - → COM3 → COM2 → COM1
13
S6A0032
PRELIMINARY SPEC. VER. 0.5
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
INSTRUCTION DESCRIPTION
Table 9. Instruction Table
Instruction
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description
*Clear display
0
0
0
0
0
0
0
0
0
1
Write "20H" to DDRAM and set DDRAM
address to "00H" from AC
Return home
0
0
0
0
0
0
0
0
1
-
DDRAM address is set to 00h from AC and
the cursor returns to 00h position. The
contents of DDRAM are not changed.
Entry mode set
0
0
0
0
0
0
0
1
I/D
SH
Assign cursor moving direction and enable
the shift of entire display
Display ON / OFF
0
control
0
0
0
0
0
1
D
C
B
Set display (D), cursor (C), and blinking of
cursor (B) ON / OFF control
Cursor or display
shift
0
0
0
0
0
1
-
-
Set cursor moving and display shift control
bit, and the direction, without changing of
DDRAM data
Function set
0
0
0
0
1
DL
-
-
-
-
Set interface data length (DL: 4-bit / 8-bit)
instruction
CGRAM
address set
0
0
0
1
0
0
A3
A2
A1
A0
Set CGRAM address in address counter.
DDRAM
address set
0
0
1
A6
A5
A4
A3
A2
A1
A0
Set DDRAM address in address counter.
Read busy flag
and address
0
1
BF
A6
A5
A4
A3
A2
A1
A0
Whether in internal operation or not can be
known by reading BF, The contents of
address counter can also be read
Write data
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write data into DDRAM / CGRAM
Read data
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read data from DDRAM / CGRAM
S/C R/L
("-": Don’t care )
NOTES:
1. Instruction execution time depends on the internal process time of S6A0032, therefore it is necessary to provide a time larger
than one MPU interface cycle time (tc) between execution of two successive instructions.
2. "Clear Display" instruction has 850µs execution time (when fosc = 40.0kHz), so check the Busy flag or wait for more than
850µs after using "Clear Display" instruction.
14
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0032
Clear Display
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
1
Clear all the display data by writing "20H" (space code of CGROM) to all the DDRAM address, and set the DDRAM
address to "00H" into AC (address counter). For this instruction, the CGROM address "20H" have to set space code.
If the display position has shifted then it returns to the original positions. Namely, when display data is shifted and
cursor or blinking is displayed, bring the cursor to the left edge on first line of the display. It makes entry mode to
increment (I/D = "High").
Return Home
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
1
Return Home instruction field makes cursor return home. DDRAM address is set to 00h from AC and the cursor
returns to 00h position. The contents of DDRAM are not changed.
Entry Mode Set
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
0
0
0
0
0
0
0
1
Set the moving direction of cursor and display after data writing or reading instruction.
DB1
DB0
I/D
SH
I/D: Increment / decrement of DDRAM / CGRAM address (cursor or blink)
After DDRAM / CGRAM data write/read operation, DDRAM/CGRAM address is increased (I/D = "High") or
decreased (I/D = "Low") by 1. So in case of DDRAM data transfer operation and cursor or blink is turned on, cursor
or blink moves to right (I/D = "High") or left (I/D = "Low"), but in CGRAM data transfer operation, cursor or blink does
not move.
SH: Shift of entire display
When DDRAM read (CGRAM read/write) operation or SH = "Low", entire display is not shift. Only when SH = "High"
and DDRAM write operation, entire display is shift according to I/D value (I/D = "1": shift left, I/D = "0": shift right).
Display ON / OFF Control
RS
R/W
DB7
DB6
DB5
0
0
0
0
0
Control display / cursor/blink ON / OFF 1 bit register
DB4
DB3
DB2
DB1
DB0
0
1
D
C
B
D: Display ON / OFF Control Bit
When D = "High", entire display is turned ON.
When D = "Low", entire display is turned OFF, but display data is remained in DDRAM.
C: Cursor ON / OFF Control Bit
When C = "High", cursor is turned ON.
When C = "Low", cursor is disappeared in current display, but I/D register remains its data.
B: Cursor Blink ON / OFF Control Bit
When B = "High", cursor blink is ON, that performs alternate between all high data (black pattern) and display
character at the cursor position.
When B = "Low", blink is OFF.
15
S6A0032
PRELIMINARY SPEC. VER. 0.5
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Cursor or Display Shift
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
S/C
R/L
Without writing or reading of display data, shift right / left the cursor position or display. This instruction is used to
correct or search display data (refer to table 10). Note that display shift is performed simultaneously in all the line.
When displayed data is shifted repeatedly, each line shifted individually. When display shift is performed, the
contents of address counter are not changed.
Table 10. Shift Patterns According to S/C and R/L Bits
S/C
R/L
Operation
0
0
Shift cursor to the left, AC is decreased by 1
0
1
Shift cursor to the right, AC is increased by 1
1
0
Shift all the display to the left, cursor moves according to the display
1
1
Shift all the display to the right, cursor moves according to the display
Function Set
RS
R/W
DB7
DB6
DB5
DB4
0
0
0
0
1
DL
DL: Interface Data Length Control Bit
When DL = "High", it means 8-bit bus mode with MPU.
When DL = "Low", it means 4-bit bus mode with MPU.
When 4-bit bus mode, it needs to transfer 4-bit data by two times.
DB3
DB2
DB1
DB0
-
-
-
-
DB3
DB2
DB1
DB0
CGRAM Address Set
RS
R/W
DB7
DB6
DB5
DB4
0
0
0
1
0
0
A3
A2
A1
A0
Set CGRAM address to AC. This instruction makes CGRAM data available from MPU for user defined character
pattern. CGRAM address is from 00h to 0Fh.
DDRAM Address Set
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
A6
A5
A4
A3
A2
A1
A0
Set DDRAM address to AC. Before writing / reading data into / from the RAM, set the address by RAM Address Set
instruction. Next, when data are written / read in succession, the address is automatically increased by 1 (when I/D
= "High") or decreased by 1 (when I/D = "Low"). The address ranges are 00h to 0Fh (1st line) and 40h to 4Fh (2nd
line).
16
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0032
Read Busy Flag and Address
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
BF
A6
A5
A4
A3
A2
A1
A0
This instruction shows whether S6A0032 is in internal operation or not. If the resultant BF is "High", it means the
internal operation is in progress and you have to wait until BF to be "Low", and then the next instruction can be
performed. In this instruction you can read also the value of address counter.
Write Data
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write binary 8- / 5- bit data to DDRAM / CGRAM. The selection of RAM from DDRAM / CGRAM is set by the
previous address set instruction (DDRAM address set, CGRAM address set). After write operation, the address is
automatically increased / decreased by 1, according to the entry mode.
Read Data
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read binary 8- / 5- bit data from DDRAM / CGRAM. The selection of RAM is set by the previous address set
instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is invalid,
because the direction of AC is not determined. If you read RAM data several times without RAM address set
instruction before read operation, you can get correct RAM data from the second, and the first data would be
incorrect, because there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift
instruction plays the same role as DDRAM address set instruction: it also transfers RAM data to output data register.
After read operation address counter is automatically increased / decreased by 1 according to the entry mode. After
CGRAM read operation, display shift may not be executed correctly.
* In case of RAM write operation, after this operation, AC is increased/decreased by 1 like read operation. In this
time, AC indicates the next address position, but you can read only the previous data by read instruction. RAM
address is dummy data, so the correct RAM data come from the second read transaction. After reading operation,
the address is increased by 1 automatically.
17
S6A0032
PRELIMINARY SPEC. VER. 0.5
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
INITIALIZING
HARDWARE RESET
When the power is turned on, S6A0032 is initialized automatically by the power on reset circuit (refer to figure 8).
In case of RESETB pin becomes "Low" and durable the state for more than 1.2µs (VDD = 3V), S6A0032 can be
initialized too. During the initialization, the following instructions are executed, and BF (Busy Flag) is kept "High"
(busy state) to the end of initialization.
Display Clear
All the DDRAM data is set to "20H"
Return Home
Address counter = "00H"
Entry Mode Set Instruction
I/D = 1: Address counter is set to increment mode.
SH = 0: Entire display shift is disabled.
Display ON / OFF Control Instruction
C = 0: cursor OFF
B = 0: blink OFF
D = 0: display OFF
Function Set Instruction
DL = 1: 8-bit interface mode
CGRAM / DDRAM Address
RAM address counter is set to "00H".
tRDD
VDD
tOFF
0.9VDD
0.1VDD
VDD
Power OFF Time
0.1VDD
tRDD
tOFF
0.1VDD
≤ 1 ms
≥ 1 ms
Note: If the upper power conditions are not satisfied in power ON / OFF sequence, the
internal Power On Reset (POR) circuit will not operates normally.
Figure 8. Power ON / OFF Timing
18
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0032
tR
tRW
RESETB
Internal Reset Time
Reset Pulse Width
Reset Time
tRW
tR
1.2 µs
850 µs
Note: tRW indicates the minimum RESETB duration for activate internal reset signal
tR indicates reset completion time of internal circuit from the start of the internal
reset signal (when fosc = 40.0kHz).
Figure 9. RESET Timing
19
S6A0032
PRELIMINARY SPEC. VER. 0.5
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
INSTRUCTION INITIALIZING WITH RESET
8-bit Interface Mode (fosc = 40.0kHz)
VDD-VSS Power ON
When Using RESETB
input for Initializing
When just Using Internal
Power On Reset Circuit
Wait until Power is Stable
Set Reset (RESETB Pin = "Low")
Wait for more than 20ms
after VDD rises to 0.9 VDD
Wait for more than 1.2µs
Release Reset (RESETB Pin = "High")
Wait for more than 1ms
Command Input
Function Set
RS
0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DL
0
0
0
1
(1)
Entry Mode Set
0
0
0
0
0
0
0
1
I/D
SH
0
1
D
C
B
Display ON / OFF Control
0
0
0
0
0
End of Initialization
RAM Address Set
RAM Data Write
20
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0032
4-bit Interface Mode (fosc = 40.0kHz)
VDD-VSS Power ON
When Using RESETB
Input for Initializing
When just Using Internal
Power On Reset Circuit
Wait until Power is Stable
Set Reset (RESETB Pin = "Low")
Wait for more than 20ms
after VDD rises to 0.9 VDD
Wait for more than 1.2µs
Release Reset (RESETB Pin = "High")
Wait for more than 1ms
Command Input
Function Set
RS
0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DL
0
0
0
1
(0)
Entry Mode Set
0
0
0
0
0
0
0
1
0
I/D
0
SH
-
-
-
-
0
B
-
-
-
-
Display ON / OFF Control
0
0
0
0
0
1
0
D
0
C
End of Initialization
RAM Address Set
RAM Data Write
21
S6A0032
PRELIMINARY SPEC. VER. 0.5
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
LCD DRIVING POWER SUPPLY CIRCUIT
The Power Supply circuit produces LCD panel driving voltage at low power consumption. The LCD driving Power
Supply circuit consists of external voltage input and voltage follower.
VDD
VDD
S6A0032
External
Power
Supply
C1
V0
O
P
E
N
V1
V2
V3
V4
VSS
GND
* Recommended Capacitance value is 0.1 to 4.7µF
Figure 10. LCD Driving Power Connection
22
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0032
MPU INTERFACE
INTERFACING WITH 8080-SERIES MICROPROCESSORS
VCC
VDD
VCC
MPU
A0
A1 - A7
IORQ
DECODER
RS
CSB
MI
E_RD
RW_WR
DB0 - DB7
RESET
RESETB
GND
GND
S6A0032
RD
WR
D0 - D7
(8080-series)
VSS
RESETB
GND
Figure 11. Interfacing with 8080-series MPU
INTERFACING WITH 6800-SERIES MICROPROCESSORS
VCC
VCC
MPU
DECODER
RS
CSB
MI
S6A0032
(6800 -series)
GND
VCC
VDD
A0
A1 - A7
VMA
E
R/W
D0 - D7
E_RD
RW_WR
DB0 - DB7
RESET
RESETB
RESETB
VSS
GND
Figure 12. Interfacing with 6800-series MPU
23
S6A0032
PRELIMINARY SPEC. VER. 0.5
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
APPLICATION INFORMATION FOR LCD PANEL
Chip Bottom & Lower View (DIRC = "0", DIRS = "0")
SEG80
SEG79
SEG78
SEG77
SEG76
•
•
•
•
•
•
•
•
•
•
•
•
•
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
COM8
COM7
COM6
•••
COM2
COM1
BOTTOM VIEW
COM16
COM15
•••
COM11
COM10
COM9
Figure 13. Chip Bottom & Lower View Interfacing with LCD Panel
24
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0032
Chip Bottom & Upper View (DIRC = "1", DIRS = "1")
BOTTOM VIEW
SEG1
SEG2
SEG3
SEG4
SEG5
•
•
•
•
•
•
•
•
•
•
•
•
•
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
COM9
COM10
COM11
•••
COM15
COM16
COM1
COM2
•••
COM6
COM7
COM8
Figure 14. Chip Bottom & Upper View Interfacing with LCD Panel
25
S6A0032
PRELIMINARY SPEC. VER. 0.5
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Chip Top & Lower View (DIRC = "0", DIRS = "1")
SEG1
SEG2
SEG3
SEG4
SEG5
•
•
•
•
•
•
•
•
•
•
•
•
•
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
COM16
COM15
•••
COM11
COM10
COM9
TOP VIEW
COM8
COM7
COM6
•••
COM2
COM1
Figure 15. Chip Top & Lower View Interfacing with LCD Panel
26
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0032
Chip Top & Upper View (DIRC = "1", DIRS = "0")
TOP VIEW
SEG80
SEG79
SEG78
SEG77
SEG76
•
•
•
•
•
•
•
•
•
•
•
•
•
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
COM1
COM2
•••
COM6
COM7
COM8
COM9
COM10
COM11
•••
COM15
COM16
Figure 16. Chip Top & Upper View Interfacing with LCD Panel
27
S6A0032
PRELIMINARY SPEC. VER. 0.5
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
FRAME FREQUENCY
1-line Selection Period
1 2
----
15 16 1 2
----
15 16 1 2
----
15 16 1 2
----
15 16
V0
V1
COM1
V4
VSS
1 FRAME
1 FRAME
1-line Selection Period = 16 Clock Pulses x 2 Division
One Frame
= 32 x 16 x 25.0µs = 12.8ms (1 Clock = 25.0µs at fosc = 40.0kHz)
Frame Frequency
= 1 / 12.8ms = 78Hz
Figure 17. Frame Frequency
28
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0032
MAXIMUM ABSOLUTE RATE
Table 11. Maximum Absolute Rate
Characteristics
Symbol
Value
Unit
Power supply voltage (1)
VDD
-0.3 to +7.0
V
Power supply voltage (2)
V0
-0.3 to + 8.0
V
Input voltage
VIN
-0.3 to VDD +0.3
V
Operating temperature
TOPR
-30 to +85
°C
Storage temperature
TSTG
-55 to +125
°C
NOTE1: All the voltage levels are based on VSS = 0V.
NOTE2: Voltage greater than above may damage the circuit.
Voltage level: V0 ≥ VDD ≥ VSS
Voltage level: V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
29
S6A0032
PRELIMINARY SPEC. VER. 0.5
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
Table 12. DC Characteristics
(VDD = 2.4V to 3.6V, Ta = -30 to +85 oC)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Operating voltage
VDD
-
2.4
-
3.6
V
IDD1
Display operation
V0 = 6V without load
No access from MPU
-
-
50
IDD2
Access operation from MPU
fcyc = 200kHz
-
-
500
VIH
-
0.7VDD
-
VDD
VIL
-
VSS
-
0.3VDD
ILEAK
VIN = 0V to VDD
-1
-
1
RCOM
Io = ± 50µA
-
-
5
RSEG
Io = ± 50µA
-
-
10
Frame frequency
f FR
VDD = 3V, Ta = 25 oC
55
78
101
Hz
External clock
frequency
f CK
-
-
40.0
-
kHz
LCD driving voltage
VLCD
VLCD = V0 – VSS
3.0
-
6.0
V
Supply current
(VDD = 3V, Ta = 25 oC)
Input voltage
Input leakage current
RON resistance
30
µA
V
µA
kΩ
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0032
Table 12. DC Characteristics (Continued)
(VDD = 3.6V to 5.5V, Ta = -30 to +85 oC)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Operating voltage
VDD
-
3.6
-
5.5
V
IDD1
Display operation
V0 = 6V without load
No access from MPU
-
-
80
IDD2
Access operation from MPU
fcyc = 200kHz
-
-
1000
VIH
-
0.7VDD
-
VDD
VIL
-
VSS
-
0.3VDD
ILEAK
VIN = 0V to VDD
-1
-
1
RCOM
Io = ± 50µA
-
-
5
RSEG
Io = ± 50µA
-
-
10
Frame frequency
f FR
VDD = 3V, Ta = 25 oC
55
78
101
Hz
External clock
frequency
f CK
-
-
40.0
-
kHz
LCD driving voltage
VLCD
VLCD = V0 – VSS
3.6
-
6.0
V
Supply current
(VDD = 5V, Ta = 25 oC)
Input voltage
Input leakage current
RON resistance
µA
V
µA
kΩ
31
S6A0032
PRELIMINARY SPEC. VER. 0.5
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
AC CHARACTERISTICS
6800-series MPU Interface & Write Instruction
Table 13. AC Characteristics (6800-series Write Instruction)
Condition
VDD = 2.4V to 3.6V,
Ta = -30 to +85 oC
VDD = 3.6V to 5.5V,
Ta = -30 to +85 oC
Characteristic
Symbol
Min.
E cycle time
tC
650
Pulse rise / fall time
tR , tF
-
-
25
E pulse width high
tWH
450
-
-
E pulse width low
tWL
150
-
-
RS and CSB setup time
tSU1
60
-
-
RS and CSB hold time
tH1
30
-
-
DB setup time
tSU2
100
-
-
DB hold time
tH2
50
-
-
E cycle time
tC
350
Pulse rise / fall time
tR , tF
-
-
25
E pulse width high
tWH
250
-
-
E pulse width low
tWL
100
-
-
RS and CSB setup time
tSU1
40
-
-
RS and CSB hold time
tH1
10
-
-
DB setup time
tSU2
40
-
-
DB hold time
tH2
10
-
-
Typ.
tH1
tWL
tF
E_RD
tR
tSU2
tH2
DB0 to DB7
tC
Figure 18. Write Bus Mode Timing (6800-series MPU Interface)
32
ns
-
RW_WR
tWH
Unit
-
RS, CSB
tSU1
Max.
ns
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0032
8080-series MPU Interface & Write Instruction
Table 14. AC Characteristics (8080-series Write Instruction)
Condition
VDD = 2.4V to 3.6V,
Ta = -30 to +85 oC
VDD = 3.6V to 5.5V,
Ta = -30 to +85 oC
Characteristic
Symbol
Min.
WR cycle time
tC
650
Pulse rise / fall time
tR , tF
-
-
25
WR pulse width high
tWH
150
-
-
WR pulse width low
tWL
450
-
-
RS and CSB setup time
tSU1
60
-
-
RS and CSB hold time
tH1
30
-
-
DB setup time
tSU2
100
-
-
DB hold time
tH2
50
-
-
WR cycle time
tC
350
Pulse rise / fall time
tR , tF
-
-
25
WR pulse width high
tWH
100
-
-
WR pulse width low
tWL
250
-
-
RS and CSB setup time
tSU1
40
-
-
RS and CSB hold time
tH1
10
-
-
DB setup time
tSU2
40
-
-
DB hold time
tH2
10
-
-
Typ.
Max.
Unit
-
ns
-
ns
RS, CSB
tSU1
t WL
tH1
tR
tWH
RW_WR
tF
tSU2
tH2
DB0 to DB7
tC
Figure 19. Write Bus Mode Timing (8080-series MPU Interface)
33
S6A0032
PRELIMINARY SPEC. VER. 0.5
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
6800-series MPU Interface & Read Instruction
Table 15. AC Characteristics (6800-series Read Instruction)
Condition
VDD = 2.4V to 3.6V,
Ta = -30 to +85 oC
VDD = 3.6V to 5.5V,
Ta = -30 to +85 oC
Characteristic
Symbol
Min.
E cycle time
tC
650
Pulse rise / fall time
tR,tF
-
-
25
E pulse width high
tWH
450
-
-
E pulse width low
tWL
150
-
-
RS and CSB setup time
tSU
60
-
-
RS and CSB hold time
tH
30
-
-
DB output delay time
tD
-
-
360
DB output hold time
tDH
20
-
-
E cycle time
tC
350
Pulse rise / fall time
tR,tF
-
-
25
E pulse width high
tWH
250
-
-
E pulse width low
tWL
100
-
-
RS and CSB setup time
tSU
40
-
-
RS and CSB hold time
tH
10
-
-
DB output delay time
tD
-
-
120
DB output hold time
tDH
10
-
-
Typ.
RW_WR
tWH
tF
t WL
E_RD
tR
tD
tDH
DB0 to DB7
tC
Figure 20. Read Bus Mode Timing (6800-series MPU Interface)
34
ns
-
tH
B
Unit
-
RS, CSB
tSU
Max.
ns
16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0032
8080-series MPU Interface & Read Instruction
Table 16. AC Characteristics (8080-series Read Instruction)
Condition
VDD = 2.4V to 3.6V,
Ta = -30 to +85 oC
VDD = 3.6V to 5.5V,
Ta = -30 to +85 oC
Characteristic
Symbol
Min.
RD cycle time
tC
650
Pulse rise / fall time
tR,tF
-
-
25
RD pulse width high
tWH
150
-
-
RD pulse width low
tWL
450
-
-
RS and CSB setup time
tSU
60
-
-
RS and CSB hold time
tH
30
-
-
DB output delay time
tD
-
360
DB output hold time
tDH
20
-
-
RD cycle time
tC
350
Pulse rise / fall time
tR,tF
-
-
25
RD pulse width high
tWH
100
-
-
RD pulse width low
tWL
250
-
-
RS and CSB setup time
tSU
40
-
-
RS and CSB hold time
tH
10
-
-
DB output delay time
tD
-
-
120
DB output hold time
tDH
10
-
-
Typ.
Max.
Unit
-
ns
-
ns
RS, CSB
tSU
tWL
tH
tR
tWH
E_RD
tF
tD
tDH
DB0 to DB7
tC
Figure 21. Read Bus Mode Timing (8080-series MPU Interface)
35