32COM/60SEG DRIVER & C O N T R O L L E R F O R D O T MATRIX LCD S6A0071 INTRODUCTION The S6A0071 is a dot matrix LCD controller & driver LSI which is fabricated by low power CMOS technology. It can display 1 line × 24 characters or 2 line × 24 characters with 5 × 7 dots format. FUNCTION • Character type dot matrix single chip LCD controller & driver • Internal driver: 32 common and 60 segment signal output • Easy interface with 4-bit or 8-bit MPU • Display character pattern: 5 × 7 dots format (240 kinds) • The Special character pattern is programmable by character generator RAM directly. • A customer character pattern is programmable by mask option. • Various instruction functions • Built-in automatic power on reset • Driving method is B-type (frame inversion) FEATURES Internal Memory • Character Generator ROM (CGROM): 8,400 bits (240 characters × 5 × 7 dots) • Character Generator RAM (CGRAM): 64 × 8 bits (8 characters × 5 × 8 dots) • Display Data RAM (DDRAM): 80 × 8 bits ( 80 characters max.) Low Power Operation • Power supply voltage range (VDD): 2.4 to 5.5V • LCD drive voltage range (VDD - V5): 3.0 to 12.0V Voltage doubler generates about double from signals power supply On chip generation of LCD supply voltage from voltage doubler (external supply also possible) Programmable duty cycle • 1/16 duty: 1 line × 5 × 7 dots + cursor × 24 characters • 1/32 duty: 2 lines × 5 × 7 dots + cursor × 24 characters Internal oscillator with an external resistor 118 TCP or bare chip available 1 S6A0071 32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD BLOCK DIAGRAM VDD GND V1 V2 V3 V4 V5 Parallel/Serial Data Conversion Circuit 5 Busy Flag R/W 8 RS E DB0-DB3 Character Generator ROM (CGROM) 8400 bits Character Generator RAM (CGRAM) 512 bits Cursor & Blink Controller Circuit 8 8 Data Register (DR) 8 Input/ Output Buffer 8 8 DB4-DB7 5 Instruction 8 Register (IR) Instruction Decoder Display Data RAM (DDRAM) 7 640 bits 60-bit Shift Register 7 60-bit Latch Circuit Seg60 ment Driver SEG1SEG60 D 7 Address Counter (AC) 32-bit Shift Register OSC1 OSC2 Timing Generator Circuit Voltage Doubler Vci C1 C2 V5out 2 T1 T2 Common 32 Driver COM1COM32 32COM/60SEG DRIVER & C O N T R O L L E R F O R D O T MATRIX LCD S6A0071 118 SEG44 117 SEG43 116 SEG42 115 SEG41 114 SEG40 113 SEG39 112 SEG38 111 SEG37 110 SEG36 109 SEG35 108 SEG34 107 SEG33 106 SEG32 105 SEG31 104 SEG30 103 SEG29 102 SEG28 101 SEG27 100 SEG26 99 SEG25 98 SEG24 97 SEG23 96 SEG22 95 SEG21 94 SEG20 93 SEG19 92 SEG18 91 SEG17 PAD DIAGRAM S6A0071 Y (0, 0) X Chip size: 3920 × 5080 Pad size: 100 × 100 Unit: µm 90 SEG16 89 SEG15 88 SEG14 87 SEG13 86 SEG12 85 SEG11 84 SEG10 83 SEG9 82 SEG8 81 SEG7 80 SEG6 79 SEG5 78 SEG4 77 SEG3 76 SEG2 75 SEG1 74 COM1 73 COM2 72 COM3 71 COM4 70 COM5 69 COM6 68 COM7 67 COM8 66 COM17 65 COM18 64 COM19 63 COM20 62 COM21 61 COM22 60 COM23 59 COM24 VSS 33 OSC1 34 OSC2 35 V1 36 V2 37 V3 38 V4 39 V5 40 V5OUT 41 C1 42 C2 43 VCI 44 VDD 45 RS 46 R/W 47 E 48 DB0 49 DB1 50 DB2 51 DB3 52 DB4 53 DB5 54 DB6 55 DB7 56 T2 57 T1 58 SEG45 1 SEG46 2 SEG47 3 SEG48 4 SEG49 5 SEG50 6 SEG51 7 SEG52 8 SEG53 9 SEG54 10 SEG55 11 SEG56 12 SEG57 13 SEG58 14 SEG59 15 SEG60 16 COM9 17 COM10 18 COM11 19 COM12 20 COM13 21 COM14 22 COM15 23 COM16 24 COM25 25 COM26 26 COM27 27 COM28 28 COM29 29 COM30 30 COM31 31 COM32 32 NOTE: "S6A0071" marking is to make the PAD No. 95 easy to find. 3 S6A0071 32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD PAD CENTER COORDINATES 4 PAD PAD COORDINATE PAD PAD NUM. NAME X 1 SEG45 2 COORDINATE PAD PAD Y NUM. NAME X -1794 2170 41 V5OUT SEG46 -1794 2030 42 3 SEG47 -1794 1890 4 SEG48 -1794 5 SEG49 6 COORDINATE Y NUM. NAME X Y -562 -2374 81 SEG7 1794 910 C1 -438 -2374 82 SEG8 1794 1050 43 C2 -312 -2374 83 SEG9 1794 1190 1750 44 VCI -188 -2374 84 SEG10 1794 1330 -1794 1610 45 VDD -62 -2374 85 SEG11 1794 1470 SEG50 -1794 1470 46 RS 62 -2374 86 SEG12 1794 1610 7 SEG51 -1794 1330 47 R/W 118 -2374 87 SEG13 1794 1750 8 SEG52 -1794 1190 48 E 312 -2374 88 SEG14 1794 1890 9 SEG53 -1794 1050 49 DB0 438 -2374 89 SEG15 1794 2030 10 SEG54 -1794 910 50 DB1 562 -2374 90 SEG16 1794 2170 11 SEG55 -1794 770 51 DB2 688 -2374 91 SEG17 1686 2374 12 SEG56 -1794 630 52 DB3 812 -2374 92 SEG18 1561 2374 13 SEG57 -1794 490 53 DB4 938 -2374 93 SEG19 1436 2374 14 SEG58 -1794 350 54 DB5 1062 -2374 94 SEG20 1311 2374 15 SEG59 -1794 210 55 DB6 1188 -2374 95 SEG21 1186 2374 16 SEG60 -1794 70 56 DB7 1312 -2374 96 SEG22 1061 2374 17 COM9 -1794 -70 57 T2 1438 -2374 97 SEG23 936 2374 18 COM10 -1794 -210 58 T1 1562 -2374 98 SEG24 811 2374 19 COM11 -1794 -350 59 COM24 1794 -2170 99 SEG25 686 2374 20 COM12 -1794 -490 60 COM23 1794 -2030 100 SEG26 561 2374 21 COM13 -1794 -630 61 COM22 1794 -1890 101 SEG27 436 2374 22 COM14 -1794 -770 62 COM21 1794 -1750 102 SEG28 311 2374 23 COM15 -1794 -910 63 COM20 1794 -1610 103 SEG29 186 2374 24 COM16 -1794 -1050 64 COM19 1794 -1470 104 SEG30 61 2374 25 COM25 -1794 -1190 65 COM18 1794 -1330 105 SEG31 -64 2374 26 COM26 -1794 -1330 66 COM17 1794 -1190 106 SEG32 -189 2374 27 COM27 -1794 -1470 67 COM8 1794 -1050 107 SEG33 -314 2374 28 COM28 -1794 -1610 68 COM7 1794 -910 108 SEG34 -439 2374 29 COM29 -1794 -1750 69 COM6 1794 -770 109 SEG35 -564 2374 30 COM30 -1794 -1890 70 COM5 1794 -630 110 SEG36 -689 2374 31 COM31 -1794 -2030 71 COM4 1794 -490 111 SEG37 -814 2374 32 COM32 -1794 -2170 72 COM3 1794 -350 112 SEG38 -939 2374 32COM/60SEG DRIVER & C O N T R O L L E R F O R D O T MATRIX LCD S6A0071 PAD CENTER COORDINATES (Continued) PAD PAD COORDINATE PAD PAD NUM. NAME X 33 VSS 34 COORDINATE PAD PAD Y NUM. NAME X -1562 -2374 73 COM2 OSC1 -1438 -2374 74 35 OSC2 -1312 -2374 36 V1 -1188 37 V2 38 COORDINATE Y NUM. NAME X Y 1794 -210 113 SEG39 -1064 2374 COM1 1794 -70 114 SEG40 -1189 2374 75 SEG1 1794 70 115 SEG41 -1314 2374 -2374 76 SEG2 1794 210 116 SEG42 -1439 2374 -1062 -2374 77 SEG3 1794 350 117 SEG43 -1564 2374 V3 -938 -2374 78 SEG4 1794 490 118 SEG44 -1689 2374 39 V4 -812 -2374 79 SEG5 1794 630 40 V5 -688 -2374 80 SEG6 1794 770 5 S6A0071 32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD PAD DESCRIPTION PAD ( No.) Pad No. VDD 45 VSS 33 V1-V5 36-40 S1-S60 75-118, 1-16 O Segment output Segment signal output for LCD drive LCD C1-C8 C9-C16 C17-C24 C25-C32 74-67, 17-24, 66-59, 25-32, O Common output Common signal output for LCD drive LCD OSC1 34 I Oscillator When using internal oscillator, connect external Rf resistor. External resistor OSC/OSC2 OSC2 35 O Oscillator If external clock is used, connect it to OSC1 External clock (OSC1) RS 46 I Register select Used as register selection input. When RS = 1, Data register is selected. When RS = 0, Instruction register is selected. MPU R/W 47 I Read/write Used as read/write selection input. When RW = 1, read operation. When RW = 0, write operation. MPU E 48 I Read/write Enable Used as read/write enable signal. MPU DB0 - DB3 49 - 52 I/O Data bus 0-7 In 8-bit bus mode, used as low order bidirectional data bus. In 4-bit bus mode, open these pins. MPU DB4 - DB7 53 - 56 I/O Data bus 0-7 In 8-bit bus mode, used as high order MPU bidirectional data bus. In 4-bit bus mode, used as both high and low order. DB7 used for busy flag output. Vci 44 I Voltage doubler output C1,C2 42, 43 I Capacitor V5OUT 41 O Voltage doubler output T1, T2 58, 57 I Test pin 6 I/O NAME Description Interface For logical circuit (+3V, 5V) Supply voltage Ground (0V) Power supply Bias voltage level for LCD driving Input terminal for voltage doubler. (normally Vci = VDD) Power supply Capacitor for voltage doubler connecting terminal (+). Capacitor for voltage doubler connecting terminal(-). Capacitor Voltage doubler output terminal connected to LCD supply voltage V5 Maker testing terminal (normally open) 32COM/60SEG DRIVER & C O N T R O L L E R F O R D O T MATRIX LCD S6A0071 FUNCTION DESCRIPTION System Interface This chip has both kinds of interface type with MPU: 4-bit bus and 8-bits bus. 4-bit bus and 8-bit bus are selected by the DL bit in the instruction register. During read or write operation, two 8-bit registers are used. One is the data register (DR), and the other is the instruction register (IR). The data register (DR) is used as a temporary data storage place for being written into or read from DDRAW/CGRAM . Target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically. Thus, after MPU reads DR data, the data in the next DDRAM/CGRAM address is transferred into DR automatically. Also, after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM automatically. The instruction register (IR) is used only to store instruction codes transferred from MPU. MPU cannot use it to read instruction data. To select a register, you can use the RS input pin in 4-bit/8-bit bus mode. Table 1. Various Kinds of Operations to RS and R/W Bits RS R/W Operation 0 0 Instruction Write operation (MPU writes instruction code into IR) 0 1 Read Busy flag (DB7) and address counter (DB0 - DB7) 1 0 Data Write operation (MPU writes data into DR) 1 1 Data Read operation (MPU reads data into DR) Busy Flag (BF) When BF = 1, it indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read through DB7 port, when RS = 0, and R/W = 1. (Read Instruction Operation). Before executing the next instruction, be sure that BF is not 1. Address Counter (AC) The Address Counter (AC) stores DDRAM/CGRAM addresses, transferred from IR. After writing into (reading from) DDRAM/CGRAM. AC is automatically increased (decreased) by 1. When RS = 0 and R/W = 1, AC can be read through ports DB0 - DB6. 7 S6A0071 32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD Display Data RAM (DDRAM) The DDRAM stores display data of maximum 80 × 8 bits (80 characteristics). The DDRAM address is set in the address counter (AC) as a hexadecimal number. (Refer to fig-1). MSB LSB AC6 AC5 AC4 AC3 AC2 AC1 AC0 Figure 1. DDRAM Address 1) 1-line Display In case of a 1-line display, the address range of DDRAM is 00H - 04H. Display position COM1 COM8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 SEG1 S6A0071 SEG60 SEG1 S6A0071 COM9 COM16 SEG60 DDRAM Address COM1 COM8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 COM9 COM16 (After Shift Left) COM1 COM8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 4F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 (After Shift Right) Figure 2. 1-line × 24 char. Display 8 COM9 COM16 32COM/60SEG DRIVER & C O N T R O L L E R F O R D O T MATRIX LCD S6A0071 2) 2-line Display In case of a 2-line display, the address range of DDRAM is 00H - 27H and 40H - 67H. Display position 1 2 3 4 5 6 7 8 9 10 11 12 COM1 00 01 02 03 04 05 06 07 08 09 0A 0B COM8 13 14 15 16 17 18 19 20 21 22 23 24 0C 0D 0E 0F 10 11 12 13 14 15 16 17 COM9 COM16 DDRAM Address COM17 40 41 42 43 44 45 46 47 48 49 4A 4B COM24 SEG1 1 S6A0071 2 3 4 5 6 7 SEG60 8 9 10 11 12 4C 4D 4E 4F 50 SEG1 13 51 52 53 54 55 S6A0071 56 57 COM25 COM32 SEG60 14 15 16 17 18 19 20 21 22 23 24 COM1 01 02 03 04 05 06 07 08 09 0A 0B 0C COM8 0D 0E 0F 10 11 12 13 14 15 16 17 18 COM17 41 42 43 44 45 46 47 48 49 4A 4B 4C COM24 4D 4E 4F 50 51 52 53 54 55 56 57 58 COM9 COM16 COM25 COM32 (After Shift Left) 16 17 18 19 20 21 22 23 24 COM1 27 00 01 02 03 04 05 06 07 08 09 0A COM8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 COM17 67 40 41 42 43 44 45 46 47 48 49 4A COM24 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 COM9 COM16 COM25 COM32 (After Shift Right) Figure 3. 2-line × 24 char. Display with 60 SEG. Extension Driver 9 S6A0071 32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD CGROM (Characteristic Generator ROM) CGROM has a 5 x 7 dots 240 character pattern. CGRAM (Character Generator RAM) CDRAM has up to 5 x 8 dots 8 characters. By writing font data to CGRAM, user defined characters can be used (Refer to table 3). Timing Generation Circuit The timing generation circuit generates clock signals for the internal operations. LCD Driver Circuit LCD Driver circuit has 32 common and 60 segment signals for LCD driving. Data from CGRAM/CGROM is transferred to an 60-bit segment latch serially, and then stored to an 60-bit shift latch. When each com is selected by a 32-bit common register, segment data is also outputs through the segment driver from and 60-bit segment latch. In case of a 1-line display mode, COM1 to COM8 have 1/6 duty, and in 2-line display mode, COM1 to COM32 have 1/32 duty ratio. Cursor/Blink Control Circuit It controls cursor/blink ON/OFF at cursor position. 10 32COM/60SEG DRIVER & C O N T R O L L E R F O R D O T MATRIX LCD S6A0071 Table 3. Relationship Between Character Code (DDRAM) and Character Pattern (CGROM) Character Code (DDRAM data) CGRAM Address CGRAM Data D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0 0 0 0 0 x 0 0 0 0 . . . . . 0 . . . . . . . . . . 0 0 0 0 x . . . . . 0 1 1 1 1 1 . . . . . . . . . . 1 0 0 0 0 0 1 0 0 1 1 0 1 1 0 0 1 0 1 1 1 1 1 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 1 0 1 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 0 . . . . . 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 1 0 1 1 0 1 1 1 x x x . . . . . x x . . . . . x Pattern number Pattern 1 . . . . . Pattern 8 "X": Don't care. 11 S6A0071 32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD INSTRUCTION DESCRIPTION OUTLINE To overcome the speed difference between internal clock of S6A0071 and MPU clock, S6A0071 performs internal operation by storing control information to IR or DR. The internal operation is determined according to the signal from MPU, composed of read/write and data bus. (refer to Table 5 ) Instruction can be divided largely four kinds, (1) S6A0071 function set instructions ( set display methods, set data length, etc.) (2) Address set instructions to internal RAM (3) Data transfer instructions with internal RAM (4) Others. The address of internal RAM is automatically increased or decreased by 1. NOTE: During internal operation, Busy Flag (DB7) is read "1". Busy Flag check must be precede by the next instruction. When you make an MPU program with checking the Busy Flag (DB7) is made, it must be necessary 1/2 fosc for executing the next instruction by falling E signal after the Busy Flag (DB7) goes to "0". Contents 1) Clear Display RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H" into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on first line of the display. Make entry mode increment (I/D = "1"). 2) Return Home RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 0 0 0 0 0 0 0 0 1 DB0 x * "x": don't care Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change. 12 32COM/60SEG DRIVER & C O N T R O L L E R F O R D O T MATRIX LCD S6A0071 3) Entry Mode Set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 I/D SH Set the moving direction of cursor and display. I/D: Increment /Decrement of DDRAMAddress (C ursor orBlink) When I/D = "1", cursor/blink moves to right and DDRAM address is increased by 1. When I/D = "0", cursor/blink moves to left and DDRAM address is decreased by 1. * CGRAM operates the same as DDRAM, when reading from or writing to CGRAM. SH: Shift ofEntire Display When DDRAM is in the read (CGRAM read/write) operation or SH = "0", shift of entire display is not performed. If SH = "1" and DDRAM is in the write operation, shift of entire display is performed according to I/D value (I/D = "1" : shift left, I/D = "0" : shift right). 4) Display ON/OFF Control RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 D C B Control display/cursor/blink ON/OFF 1 bit register. D: Display ON/OFFControl Bit When D = "1", entire display is turned on. When D = "0", display is turned off, but display data remained in DDRAM. C: Cursor ON/OFF Control Bit When C = "1", cursor is turned on. When C = "0", cursor is disappeared in current display, but I/D register preserves its data. B: Cursor Blink ON/OFFControl Bit When B = "1", cursor blink is on, which performs alternate between all the "1" data and display character at the cursor position. When B = "0", blink is off. 13 S6A0071 32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 5) Cursor or Display Shift RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 S/C R/L x x Without waiting or reading the display data, shift right/left cursor position or display. This instruction is used to correct or search display data (Refer to table 6). During 2-line mode display, cursor moves to the 2nd line after the 40th digit of the 1st line. Note that display shift is performed simultaneously for the whole line. When displayed data is shifted repeatedly, each line is shifts individually. When display shift is performed, the contents of the address counter are not changed. Table 6. Shift Patterns According to S/C and R/L Bits S/C R/L Operation 0 0 Shift cursor to the left, AC is decreased by 1 0 1 Shift cursor to the right, AC is increased by 1 1 0 Shift all the display to the left, cursor moves according to the display 1 1 Shift all the display to the right, cursor moves according to the display 6) Function Set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 DL N x x x DL: Interface data length control bit When DL = "1", it means 8-bit bus mode with MPU. When DL = "0", it means 4-bit bus mode with MPU. Hence, DL is a signal to select 8-bit or 4-bit bus mode. When 4-bit bus mode, it needs to transfer 4-bit data by two times. N: Display line number control bit When N = "0", it means 1-line display mode. When N = "1", 2-line display mode is set. 7) Set CGRAM Address RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address to AC. This instruction makes CGRAM data available from MPU. 14 32COM/60SEG DRIVER & C O N T R O L L E R F O R D O T MATRIX LCD S6A0071 8) Set DDRAM Address RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. When 1-line display mode (N = 0), DDRAM address is from "00H" to "4FH". In 2-line display mode (N = 1), DDRAM address in the 1st line is from "00H" to "27H", and DDRAM address in the 2nd line is from "40H" to "67H". 9) Read Busy Flag & Address RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 This instruction shows whether S6A0071 is in internal operation or not. If the resultant BF is "1", it means the internal operation is in progress and you have to wait until BF to be Low, and then the next instruction can be performed. In this instruction you can read also the value of address counter. 10) Write data to RAM RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Write binary 8-bit data to DDRAM/CGRAM. The selection of RAM from DDRAM, and CGRAM, is set by the previous address set instruction: (DDRAM address set, CGRAM address set). RAM set instruction can also determine the AC direction to RAM. After write operation, the address is automatically increased/decreased by 1, according to the entry mode. 11) Read data from RAM RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Read binary 8-bit data from DDRAM/CGRAM. The selection of RAM is set by the previous address set instruction. If the address set instruction of RAM is not performed before this instruction, the data that is read first is invalid, because the direction of AC is not determined. If you read RAM data several times without RAM address set instruction before read operation, you can get correct RAM data from the second, but the first data would be incorrect, because there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction; it also transfer RAM data to output data register. After read operation address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM read operation, display shift may not be executed correctly. NOTE: In case of RAM write operation, AC is increased/decreased by 1 like read operation. In this time, AC indicates the next address position, but you can read only the previous data by read instruction. 15 S6A0071 32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD Table 6. Instruction Table Instruction Code Instruction RS Clear Display 0 R/ DB DB DB DB DB DB DB DB W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 1 Description Execution Instruction Code time(fsoc=270 ) Write "20H" to DDRAM. and set 1.53ms DDRAM address to "00H" from AC. Return Home 0 0 0 0 0 0 0 0 1 X Set DDRAM address to "00H" from 1.53ms the AC and return cursor to its original position if shifted. The contents of DDRAM are not change. Entry Mode 0 0 0 0 0 0 0 1 I/D SH Set Display 39µs make shift of entire display possible. 0 0 0 0 0 0 1 D C B ON/OFF Set display(D), cursor(C), and 39µs blinking of cursor(B) on/off control Control Cursor or Assign cursor moving direction and bit. 0 0 0 0 0 1 S/C R/L X X Display Shift Set cursor moving and display shift 39µs control bit, and the direction, without changing of the AC. Function Set 0 0 0 0 1 DL N X X X Set interface data length (DL : 4- 39µs bit/8-bit), numbers of display line (N : 1-line/2-line). Set CGRAM 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 Address Set DDRAM 39µs counter. 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Address Read Busy Set CGRAM address in address Set DDRAM address in address 39µs counter. 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 Whether during internal operation or Flag and not can be known by reading BF. Address The contents of address counter 0µs can also be read. Write Data to 1 0 D7 D6 D5 D4 D3 D2 D1 D0 RAM Read Data from RAM Write data into internal RAM 43µs (DDRAM/CGRAM). 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Read data from internal RAM 43µs (DDRAM/CGRAM). *"x": don't care NOTE: When you make an MPU program, checking the Busy Flag (DB7), a time margin of 1/2 fOSC is necessary for executing the next instruction by the falling edge of the 'E' signal after the Busy Flag (DB7) goes to "0". 16 32COM/60SEG DRIVER & C O N T R O L L E R F O R D O T MATRIX LCD S6A0071 INTERFACE WITH MPU 1) Interface with 8 - bit MPU When the interfacing data length are 8-bit, transfer is performed all at once through 8 ports, from DB0 to DB7. An example of the timing sequence is shown below. RS R/W E Internal signal Internal Operation DB7 DATA Busy Instruction No Busy Busy Busy Flag Check Busy Flag Check Busy Flag Check DATA Instruction Figure 4. Example of -8bit Bus Mode Timing Diagram 2) Interface with 4 - bit MPU When interfacing data length is 4-bit, only 4 ports, from DB4 to DB7, are used as data bus. At first higher 4-bit (in the case of 8-bit bus mode, the contents of DB4 - DB7), and then lower 4-bit (in case of 8bit bus mode, the contents of DB0 - DB3) are transferred. So transfer is performed twice Busy Flag outputs "high" after the second transfer are ended. An example of timing sequence is shown below. RS R/W E Internal signal DB7 Internal Operation D7 D3 Instruction Busy AC3 Busy Flag Check No Busy AC3 Busy Flag Check D7 D3 Instruction Figure 5. Example of -4bit Bus Mode Timing Diagram 17 S6A0071 32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD APPLICATION INFORMATION ACCORDING TO LCD PANEL 1) LCD Panel: 24 character× 1-line character format: × 5 7 dots + 1 cursor line (1/5 bias, 1/16 duty) COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 .. SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 S6A0071 SEG7 SEG8 SEG9 SEG10 SEG58 SEG59 SEG60 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 18 32COM/60SEG DRIVER & C O N T R O L L E R F O R D O T MATRIX LCD S6A0071 2) LCD Panel: 24 character× 2-line character format: × 5 7 dots + 1 cursor line (1/6.7 bias, 1/3 2 duty) COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 .. S6A0071 SEG1 SEG2 SEG3 SEG4 SEG5 SEG58 SEG59 SEG60 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 19 S6A0071 32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD POWER SUPPLY FOR DRIV ING LCD PANEL 1) When an external power supply is used V5OUT VSS open C1 C2 VDD V1 V2 V3 V4 V5 VDD R R R0 R R open VEE 2) When an internal booster is used (Boosting twice) VDD VDD VR 4.7 µ F + - Vci C1 + C2 4.7µ F V5OUT VSS VDD V1 V2 V3 V4 V5 R R R0 R R 4.7 µ F + - Vci C1 + C2 4.7 µ F V5OUT VSS VDD V1 V2 V3 V4 V5 R R R0 R R VR + + 4.7 µ F 4.7µ F VR: Contrast Control Resistor NOTES: 1. Boosted output voltage should not exceed the maximum value (11V) of the LCD driving voltage. 2. A voltage of over 5.5V should not be input into the reference voltage (Vci) when boosting twice. 3. The value of resistance, according to the number of lines, duty ratio and the bias, is shown below. (Refer to table 8) 20 32COM/60SEG DRIVER & C O N T R O L L E R F O R D O T MATRIX LCD S6A0071 Table 8. Duty Ratio and Power Supply for LCD Driving Item Data Number 1 2 Duty Ratio 1/16 1/32 Bias 1/5 1/6.7 Divided R R R Resistance R0 R 2.7R INITIALIZING When the power is turned on, S6A0071 is initialized automatically by power on reset circuit. During the initialization, the following instructions are executed, and BF(Busy Flag) is kept "High"(busy state) to the end of initialization. (1) Display Clear instruction: Write "20H" to all DDRAM (2) Set Functions instruction DL = 1 : 8-bit bus mode N = 1 : 2-line display mode (3) Control Display ON/OFF instruction D = 0 : Display OFF C = 0 : Cursor OFF B = 0 : Blink OFF (4) Set Entry Mode instruction I/D = 1 : Increment by 1 SH = 0 : No entire display shift 21 S6A0071 32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD FRAME FREQUENCY B-Type Waveform (Frame Inversion) 1) 1/16 Duty Cycle 1-line selection period 1 2 3 4 ... 15 16 1 2 3 ... 15 16 VDD .. V1 COM1 V4 V5 1 FRAME 1 FRAME Item Clock/Frequency 1-line selection period 120 clocks Frame frequency 140.7Hz * fOSC = 270kHz (1 clock = 3.7µs) 2) 1/32 duty cycle 1-line selection period 1 2 3 4 ... 31 32 1 2 3 ... 31 32 VDD .. V1 COM1 V4 V5 1 FRAME Item Clock/Frequency Line Selection Period 120 clocks Frame Frequency 22 1 FRAME 70.4Hz * fOSC = 270kHz (1 clock = 3.7µs) 32COM/60SEG DRIVER & C O N T R O L L E R F O R D O T MATRIX LCD S6A0071 INITIALIZING BY INSTRUCTION 1) 8-bit Interface mode Power On Wait for more than 20ms after VDD rises to 4.5V Wait for more than 30ms after VDD rises to 2.7V Condition: fosc = 270kHz 0 4-bit interface 1 8-bit interface 0 1-line mode 1 2-line mode 0 Display off 1 Display on 0 Cursor off 1 Cursor on 0 Blink off 1 Blink on 0 Decrement mode 1 Increment mode 0 Entire shift off 1 Entire shift on DL Function Set RS 0 R/W DB7 0 0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 DL(1) N X X X N Wait for more than 39µ s D Display ON/OFF Control RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C 0 0 0 0 0 0 1 D C B Wait for more than 39µ s B Display Clear RS 0 R/W DB7 0 0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 Wait for more than 1.53ms I/D Entry Mode Set RS 0 R/W DB7 0 0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 I/D SH SH Initialization End 23 S6A0071 32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 2) 4-bit Interface mode Power On Wait for more than 20ms after V DD rises to 4.5V Wait for more than 30ms after V DD rises to 2.7V Condition: fosc = 270kHz Function Set 0 4-bit interface 1 8-bit interface 0 1-line mode 1 2-line mode 0 Display off 1 Display on 0 Cursor off 1 Cursor on 0 Blink off 1 Blink on 0 Decrement mode 1 Increment mode 0 Entire shift off 1 Entire shift on DL RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 DL(0) X X X X F Wait for more than 39 µ s Function Set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 X X X X 0 0 N X X X X X X X Wait for more than 39 µ s D Display ON/OFF Control RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 X X X X 0 0 1 D C B X X X X C B Wait for more than 39 µ s Clear Display RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 X X X X 0 0 0 0 0 1 X X X X Wait for more than 1.53 ms Entry Mode Set I/D RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 X X X X 0 0 0 1 I/D SH X X X X Initialization End 24 SH 32COM/60SEG DRIVER & C O N T R O L L E R F O R D O T MATRIX LCD S6A0071 MAXIMUM ABSOLUTE LIMIT RATING Maximum Absolute Power Ratings Description Symbol Unit Value Power Supply Voltage (1) VDD V - 0.3 to +7.0 LCD Drive Voltage VLCD V VDD-13.5 to VDD+3.0 VIN V -0.3 to VDD+0.3 Input Voltage NOTE: Voltage greater than above may damage the circuit. (VDD ≥ V1 ≥ 2 ≥ V3 ≥ V4 ≥ V5) Temperature Characteristics Description Symbol Unit Value Operating Temperature TOPR °C - 3.0 to +85 Storage Temperature TSTG °C - 55 to +125 25 S6A0071 32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD ELECTRICAL CHARACTERISTICS DC Characte ristics ( VDD = +5V ± 10%, Ta = -30 to +85°C) Characteristic Symbol Condition Min Typ Max Unit Operating voltage VDD - 4.5 5.0 5.5 V Supply current IDD Internal oscillation or external clock operation. (VDD = 5V, fOSC = 270 kHz) - 0.6 1.0 mA Input voltage (1) VIH1 - 2.3 - VDD V (except OSC1) VIL1 - - - 0.8 Input voltage (2) VIH2 - VDD-1.0 - VDD (OSC1) VIL2 - - - 1.0 Output voltage (1) VOH1 IOH = -0.205mA 2.4 - - (DB0 to DB7) VOL1 IOL = 1.6mA - - 0.4 Output voltage (2) VOH2 IO = -40µA 0.9VDD - - (OSC2) VOL2 IO = 40µA - - 0.1VDD IO = ± 0.1mA - - 1 - - 1 Voltage drop VdCOM VdSEG V V V V µA Input Leakage Current (1) E IIL1 VIN = 0V to VDD -1 - 1 Input leakage current(2) (R/W, RS, DB0 to DB7) IIL2 VIN = VDD -5 - 5 Low Input Current (R/W, RS, DB0 to DB7) IIN VIN = 0V, VDD = 5V (pull up) -50 -125 -250 Internal Clock (external Rf) f IC Rf = 91kΩ ± 2% (VDD = 5V) 190 270 350 160 250 350 45 50 55 % - - 0.2 µs -4.5 -4.7 - V f EC External Clock duty - t R, t F V5out Voltage Doubler LCD Driving Voltage 26 Iout = 1mA, Ta = 25°C kHz VEF RL = ∞ 95 99.9 - % Vci Input voltage 2.5 - 5.5 V VDD-V5 (1/5, 1/6.7 bias) 3.0 - 13.5 V VLCD 32COM/60SEG DRIVER & C O N T R O L L E R F O R D O T MATRIX LCD S6A0071 DC Characteristics (VDD = +3V ± 20%, Ta = -30 to +85°C) Characteristic Symbol Condition Min Typ Max Unit Operating voltage VDD - 2.4 3.0 3.6 V Supply current IDD Internal oscillation or external clock. (VDD = 3V, fOSC = 270kHz) - 0.2 0.3 mA Input voltage (1) VIH1 - 0.8VDD - VDD V (except OSC1) VIL1 - - - 0.2VDD Input voltage (2) VIH2 - VDD-1.0 - VDD (OSC1) VIL2 - - - 1.0 Output voltage (1) VOH1 IOH = -0.205mA 2.0 - - (DB0 to DB7) VOL1 IOL = 1.6mA - - 0.5 Output voltage (2) VOH2 IO = -40µA 0.9VDD - - (OSC2) VOL2 IO = 40µA - - 0.1VDD IO = ± 0.1mA - - 1 - - 1 Voltage drop VdCOM VdSEG V V V V µA Input Leakage Current (1) E IIL1 VIN = 0V to VDD -1 - 1 Input leakage current(2) (R/W, RS, DB0 to DB7) IIL2 VIN = VDD -5 - 5 Low Input Current (R/W, RS, DB0 to DB7) IIN VIN = 0V, VDD = 3V (pull up) -10 -25 -50 Internal Clock (external Rf) f IC Rf = 91kΩ ± 2% (VDD = 3V) 160 240 320 kHz Iout = 1mA, Ta = 25°C -2.5 -2.75 - V V5out Voltage Doubler LCD Driving Voltage VEF RL = ∞ 95 99.9 - % Vci Input voltage 1.8 - VDD V VDD-V5 (1/5, 1/6.7 bias) 3.0 - 12.0 V VLCD 27 S6A0071 32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD AC Characteristics(VDD = 4.5 to 5.5V, Ta = -30 to +85°C) Mode Characteristic Write Mode E Cycle Time (Refer to figure 6) E Rise Time / Fall Time E Pulse Width ( High, Low ) Symbol Min Typ Max Unit tC 500 - - ns - 20 t R, t F tW 220 - - R/W and RS Setup Time tSU1 40 - - R/W and RS Hold Time th1 10 - - Data Setup Time tSU2 60 - - Data Hold Time th2 10 - - Read Mode E Cycle Time tC 500 - - (Refer to figure 7) E Rise Time / Fall Time - 20 t R, t F E Pulse Width ( High, Low ) tW 220 - - R/W and RS Setup Time tSU 40 - - R/W and RS Hold Time tH 10 - - Data Output Delay Time tD - - 120 Data Hold Time tDH 10 - - Symbol Min Typ Max tC 1400 - - - 20 ns AC Characteristics(VDD = 2.4 to 3.6V, Ta = -30 to +85°C) Mode Characteristic Write Mode E Cycle Time (Refer to figure 6) E Rise Time / Fall Time t r, t f E Pulse Width ( High, Low ) tW 500 - - R/W and RS Setup Time tSU1 70 - - R/W and RS Hold Time th1 10 - - Data Setup Time tSU2 195 - - Data Hold Time th2 10 - - Read Mode E Cycle Time tC 1400 - - (Refer to figure 7) E Rise Time / Fall Time t R, t F - - 20 E Pulse Width ( High, Low ) tW 500 - - R/W and RS Setup Time tSU 70 - - R/W and RS Hold Time tH 10 - - Data Output Delay Time tD - - 600 Data Hold Time tDH 20 - - 28 Unit ns ns 32COM/60SEG DRIVER & C O N T R O L L E R F O R D O T MATRIX LCD RS R/W S6A0071 VIH1 VIL1 tsu1 th1 VIL1 VIL1 th1 tw tf VIH1 VIL1 E VIH1 VIL1 tsu2 tr VIH1 VIL1 DB0 - DB7 VIL1 th2 VIH1 VIL1 Valid Data tc Figure 6. Write Mode Timing Diagram RS R/W VIH1 VIL1 tsu th VIH1 VIH1 th1 tw tf VIH1 VIL1 E tr DB0 - DB7 VIH1 VIL1 VIL1 tDH tD VOH1 VOL1 Valid Data VOH1 VOL1 tc Figure 7. Read Mode Timing Diagram 29