FAIRCHILD 74LVQ174

74LVQ174
Low Voltage Hex D-Type Flip-Flop with Master Reset
General Description
Features
The LVQ174 is a high-speed hex D-type flip-flop. The device
is used primarily as a 6-bit edge-triggered storage register.
The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a
Master Reset to simultaneously clear all flip-flops.
n Ideal for low power/low noise 3.3V applications
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Guaranteed pin-to-pin skew AC performance
n Guaranteed incident wave switching into 75Ω
Ordering Code:
Order Number
Package Number
Package Description
74LVQ174SC
M16A
16-Lead (0.150" Wide) Small Outline Integrated Circuit, SOIC JEDEC
74LVQ174SJ
M16D
16-Lead Molded Small Outline Package, SOIC EIAJ
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment for
SOIC JEDEC and EIAJ
DS011353-1
IEEE/IEC
DS011353-3
Pin Descriptions
Pin Names
Description
D0–D5
Data Inputs
CP
Clock Pulse Input
MR
Master Reset Input
Q0–Q5
Outputs
DS011353-2
© 1998 Fairchild Semiconductor Corporation
DS011353
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74LVQ174 Low Voltage Hex D-Type Flip-Flop with Master Reset
May 1998
Functional Description
Truth Table
The LVQ174 consists of six edge-triggered D flip-flops with
individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input’s
state is transferred to the corresponding flip-flop’s output following the LOW-to-HIGH Clock (CP) transition. A LOW input
to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. The LVQ174 is useful for applications where the true output only is required and the Clock
and Master Reset are common to all storage elements.
Inputs
Output
MR
CP
D
L
X
X
Q
L
H
N
H
H
H
N
L
L
H
L
X
Q
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N = LOW-to-HIGH Transition
Logic Diagram
DS011353-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings (Note 1)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
(ICC or IGND)
Storage Temperature (TSTG)
DC Latch-Up Source or
Sink Current
Recommended Operating
Conditions (Note 2)
−0.5V to +7.0V
Supply Voltage (VCC)
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
VIN from 0.8V to 2.0V
VCC @ 3.0V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
2.0V to 3.6V
0V to VCC
0V to VCC
−40˚C to +85˚C
125 mV/ns
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The
“Recommended Operating Conditions” table will define the conditions for actual device operation.
± 50 mA
± 200 mA
−65˚C to +150˚C
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
± 100 mA
DC Electrical Characteristics
Symbol
Parameter
VCC
(V)
TA = +25˚C
Typ
VIH
Minimum High Level
3.0
TA = −40˚C to +85˚C
Units
1.5
2.0
2.0
V
Maximum Low Level
3.0
1.5
0.8
0.8
V
Input Voltage
VOH
Minimum High Level
VOUT = 0.1V
or VCC − 0.1V
Input Voltage
VIL
Conditions
Guaranteed Limits
VOUT = 0.1V
or VCC − 0.1V
3.0
2.99
2.9
2.9
V
2.58
2.48
V
IOUT = −50 µA
Output Voltage
3.0
VIN = VIL or VIH (Note 3)
IOH = −12 mA
VOL
Maximum Low Level
3.0
0.002
0.1
0.1
V
0.36
0.44
V
IOUT = 50 µA
Output Voltage
3.0
VIN = VIL or VIH (Note 3)
IOL = 12 mA
IIN
Maximum Input
± 0.1
3.6
± 1.0
µA
VI = VCC, GND
VOLD = 0.8V Max (Note 5)
Leakage Current
IOLD
Minimum Dynamic (Note 4)
3.6
36
mA
IOHD
Output Current
3.6
−25
mA
VOHD = 2.0V Min (Note 5)
ICC
Maximum Quiescent
3.6
40.0
µA
VIN = VCC
4.0
Supply Current
VOLP
Quiet Output
or GND
3.3
0.7
0.8
V
(Notes 6, 7)
3.3
−0.6
−0.8
V
(Notes 6, 7)
3.3
1.8
2.0
V
(Notes 6, 8)
3.3
1.6
0.8
V
(Notes 6, 8)
Maximum Dynamic VOL
VOLV
Quiet Output
Minimum Dynamic VOL
VIHD
Maximum High Level
Dynamic Input Voltage
VILD
Maximum Low Level
Dynamic Input Voltage
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed.
Note 6: Worst case package.
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND.
Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD),
f = 1 MHz.
3
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AC Electrical Characteristics
Symbol
Frequency
Min
Typ
60
90
50
3.3 ± 0.3
90
100
70
Propagation Delay
tPLH
CP to Qn
CP to Qn
MR to Qn
tOSHL,
Output to
tOSLH
Output Skew (Note 9)
Min
Units
Max
MHz
2.7
2.0
10.8
16.2
1.5
18.0
2.0
9.0
11.5
1.5
12.5
2.7
2.0
10.2
15.5
1.5
17.0
3.3 ± 0.3
2.0
8.5
11.0
1.5
12.0
2.7
2.5
10.8
16.2
2.0
18.0
3.3 ± 0.3
2.5
9.0
11.5
2.0
12.5
2.7
1.0
1.5
1.5
3.3 ± 0.3
1.0
1.5
1.5
Propagation Delay
tPHL
Max
3.3 ± 0.3
Propagation Delay
tPHL
TA = −40˚C to +85˚C
CL = 50 pF
2.7
Maximum Clock
fmax
TA = +25˚C
CL = 50 pF
VCC
(V)
Parameter
ns
ns
ns
ns
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design.
AC Operating Requirements
Symbol
TA = +25˚C
CL = 50 pF
VCC
(V)
Parameter
TA = −40˚C to +85˚C
CL = 50 pF
Typ
Setup Time, HIGH or LOW
tS
Dn to CP
tH
Hold Time, HIGH or LOW
Dn to CP
MR Pulse Width, LOW
tW
tW
CP Pulse Width
trec
Recovery Time
MR to CP
Units
Guaranteed Minimum
2.7
3.0
8.0
10.0
3.3 ± 0.3
2.5
6.5
7.0
2.7
1.2
4.0
4.5
3.3 ± 0.3
1.0
3.0
3.0
2.7
1.2
7.0
10.0
3.3 ± 0.3
1.0
5.5
7.0
2.7
1.2
7.0
10.0
3.3 ± 0.3
1.0
5.5
7.0
2.7
0
3.5
3.5
3.3 ± 0.3
0
2.5
2.5
ns
ns
ns
ns
ns
Capacitance
Symbol
CIN
CPD (Note 10)
Typ
Units
Input Capacitance
Parameter
4.5
pF
VCC = Open
Power Dissipation
23
pF
VCC = 3.3V
Capacitance
Note 10: CPD is measured at 10 MHz.
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4
Conditions
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead (0.150" Wide) Small Outline Integrated Circuit, SOIC JEDEC
Package Number M16A
16-Lead Molded Small Outline Package, SOIC EIAJ
Package Number M16D
5
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74LVQ174 Low Voltage Hex D-Type Flip-Flop with Master Reset
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
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sonably expected to cause the failure of the life support
the body, or (b) support or sustain life, and (c) whose
device or system, or to affect its safety or effectiveness.
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
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