74LVQ240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs General Description Features The LVQ240 is an inverting octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density. n Ideal for low power/low noise 3.3V applications n Implements patented EMI reduction circuitry n Available in SOIC JEDEC, SOIC EIAJ, and QSOP packages n Guaranteed simultaneous switching noise level and dynamic threshold performance n Improved latch-up immunity n Guaranteed incident wave switching into 75Ω n 4 kV minimum ESD immunity Ordering Code: Order Number Package Number 74LVQ240SC M20B 74LVQ240SJ M20D 74LVQ240QSC Package Description 20-Lead (0.300" Wide) Molded Small Outline Package, SOIC, JEDEC 20-Lead Molded Shrink Small Outline Package, SOIC, EIAJ MQA20 20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP, JEDEC Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Pin Assignment, SOIC and QSOP DS011611-1 Pin Descriptions Pin Names Description OE1, OE2 3-STATE Output Enable Inputs I0–I7 Inputs O0–O7 Outputs DS011611-2 Truth Tables Inputs OE1 Outputs In (Pins 12, 14, 16, 18) L L H L H L H X Z In (Pins 3, 5, 7, 9) L L H L H L H X Z Inputs OE2 H = HIGH Voltage Level X = Immaterial © 1998 Fairchild Semiconductor Corporation DS011611 Outputs L = LOW Voltage Level Z = High Impedance www.fairchildsemi.com 74LVQ240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs May 1998 Absolute Maximum Ratings (Note 1) Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or Sink Current Recommended Operating Conditions (Note 2) −0.5V to +7.0V Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) VIN 0.8V to 2.0V VCC @ 3.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V 2.0V to 3.6V 0V to VCC 0V to VCC −40˚C to +85˚C 125 mV/ns Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. ± 50 mA ± 400 mA −65˚C to +150˚C Note 2: Unused inputs must be held HIGH or LOW. They may not float. ± 300 mA DC Electrical Characteristics Symbol Parameter VCC (V) TA = +25˚C Typ VIH VIL VOH Minimum High Level Input Voltage 3.0 Maximum Low Level Input Voltage 3.0 Minimum High Level Output Voltage 1.5 TA = −40˚C to +85˚C Units Conditions Guaranteed Limits 2.0 2.0 V VOUT = 0.1V or VCC − 0.1V 1.5 0.8 0.8 V VOUT = 0.1V or VCC − 0.1V 2.9 2.9 V IOUT = −50 µA 2.58 2.48 V VIN = VIL or VIH (Note 3) 0.1 0.1 V IOUT = 50 µA 3.0 0.36 0.44 V VIN = VIL or VIH (Note 3) 3.6 ± 0.1 ± 1.0 µA 3.0 2.99 3.0 IOH = −12 mA VOL Maximum Low Level Output Voltage 3.0 0.002 IOL = 12 mA IIN Maximum Input Leakage Current IOLD Minimum Dynamic Output Current (Note 4) IOHD VI = VCC, GND 3.6 36 mA VOLD = 0.8V Max (Note 5) 3.6 −25 mA VOHD = 2.0V Min (Note 5) 40.0 µA 3.6 Maximum 3-STATE Leakage Current 3.6 VOLP Quiet Output Maximum Dynamic VOL 3.3 0.4 0.8 V (Notes 6, 7) VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.4 −0.8 V (Notes 6, 7) VIHD Maximum High Level Dynamic Input Voltage 3.3 1.6 2.0 V (Notes 6, 8) VILD Maximum Low Level Dynamic Input Voltage 3.3 1.6 0.8 V (Notes 6, 8) IOZ 4.0 VIN = VCC Maximum Quiescent Supply Current ICC or GND ± 0.25 ± 2.5 µA VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for 74LVQ. Note 6: Worst case package. Note 7: Max number of outputs defined as (n). Data Inputs are driven 0V to 3.3V. One output @ GND. Note 8: Max number of Data Inputs (n) switching. n−1 Inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. www.fairchildsemi.com 2 AC Electrical Characteristics Symbol tPHL Propagation Delay tPLH Data to Output tPZL Output Enable Time tPZH Output Disable Time tPHZ TA = +25˚C CL = 50 pF VCC (V) Parameter tPLZ TA = −40˚C to +85˚C CL = 50 pF Min Typ Max Min 2.7 2.0 8.4 14.0 2.0 15.0 3.3 ± 0.3 2.0 7.0 10.0 2.0 10.5 Units Max 2.7 2.5 9.6 16.9 2.5 18.0 3.3 ± 0.3 2.5 8.0 12.0 2.5 12.5 2.7 1.0 10.2 19.0 1.0 20.0 3.3 ± 0.3 1.0 8.5 13.5 1.0 14.0 tOSHL Output to Output Skew 2.7 1.0 1.5 1.5 tOSLH Data to Output (Note 9) 3.3 ± 0.3 1.0 1.5 1.5 ns ns ns ns Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design. Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = Open Conditions CPD (Note 10) Power Dissipation Capacitance 70 pF VCC = 3.3V Note 10: CPD is measured at 10 MHz. 3 www.fairchildsemi.com 4 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead (0.300" Wide) Molded Small Outline Package, SOIC, JEDEC Package Number M20B 20-Lead Molded Shrink Small Outline Package, SOIC, EIAJ Package Number M20D 5 www.fairchildsemi.com 74LVQ240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP, JEDEC (also known as QSOP) Package Number MQA20 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and (c) whose device or system, or to affect its safety or effectiveness. failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. Fairchild Semiconductor Corporation Americas Customer Response Center Tel: 1-888-522-5372 Fax: 972-910-8036 Fairchild Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 8 141-35-0 English Tel: +44 (0) 1 793-85-68-56 Italy Tel: +39 (0) 2 57 5631 Fairchild Semiconductor Hong Kong Ltd. 8/F Room 808 Empire Centre 68 Mody Road, Tsimshatsui East Kowloon, Hong Kong Tel: 852-2722-8338 Fax: 852-2722-8383 Fairchild Semiconductor Japan Ltd. 4F, Natsume BI, 2-18-6 Yushima, Bunkyo-ku, Tokyo 113-0034, Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8450 www.fairchildsemi.com Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.