Revised June 2001 74LVQ273 Low Voltage Octal D-Type Flip-Flop General Description Features The LVQ273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. ■ Ideal for low power/low noise 3.3V applications The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. ■ Guaranteed simultaneous switching noise level and dynamic threshold performance All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. ■ Implements patented EMI reduction circuitry ■ Available in SOIC JEDEC, SOIC EIAJ and QSOP packages ■ Improved latch-up immunity ■ Guaranteed incident wave switching into 75Ω ■ 4 kV minimum ESD immunity Ordering Code: Order Number Package Number 74LVQ273SC 74LVQ273SJ 74LVQ273QSC Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names D0–D7 © 2001 Fairchild Semiconductor Corporation DS011358 Description Data Inputs MR Master Reset CP Clock Pulse Input Q0–Q7 Data Outputs www.fairchildsemi.com 74LVQ273 Low Voltage Octal D-Type Flip-Flop February 1992 74LVQ273 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) Supply Voltage (VCC) VI = −0.5V −20 mA Input Voltage (VI) VI = VCC + 0.5V +20 mA Output Voltage (VO) DC Input Voltage (VI) −0.5V to VCC + 0.5V 0V to VCC −40°C to +85°C Minimum Input Edge Rate ∆V/∆t VO = −0.5V −20 mA VIN from 0.8V to 2.0V VO = VCC + 0.5V +20 mA VCC @ 3.0V 125 mV/ns −0.5V to VCC + 0.5V DC Output Source Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. ±50 mA or Sink Current (IO) DC VCC or Ground Current ±400 mA (ICC or IGND) Storage Temperature (TSTG) 0V to VCC Operating Temperature (TA) DC Output Diode Current (IOK) DC Output Voltage (VO) 2.0V to 3.6V −65°C to +150°C Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Latch-up Source or ±300 mA Sink Current DC Electrical Characteristics Symbol VIH Parameter Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage VOL Maximum Low Level Output Voltage IIN Maximum Input Leakage Current TA = +25°C VCC TA = −40°C to +85°C Units (V) Typ 3.0 1.5 2.0 2.0 V 3.0 1.5 0.8 0.8 V 3.0 2.99 2.9 2.9 V 3.0 3.0 Conditions Guaranteed Limits 0.002 2.58 2.48 V 0.1 0.1 V 3.0 0.36 0.44 V 3.6 ±0.1 ±1.0 µA VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VIL or VIH (Note 3) IOH = −12 mA IOUT = 50 µA VIN = VIL or VIH (Note 3) IOL = 12 mA VI = VCC, GND IOLD Minimum Dynamic 3.6 36 mA VOLD = 0.8V Max (Note 5) IOHD Output Current (Note 4) 3.6 −25 mA VOHD = 2.0V Min (Note 5) ICC Maximum Quiescent 40.0 µA Supply Current VOLP Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL VIHD Maximum High Level Dynamic Input Voltage VILD Maximum Low Level Dynamic Input Voltage 3.6 4.0 VIN = VCC or GND 3.3 0.4 0.8 V (Note 6)(Note 7) 3.3 −0.3 −0.8 V (Note 6)(Note 7) 3.3 1.7 2.0 V (Note 6)(Note 8) 3.3 1.6 0.8 V (Note 6)(Note 8) Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for. Note 6: Worst case package. Note 7: Max number of outputs defined as (n). Data Inputs are driven 0V to 3.3V; one output at GND. Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. www.fairchildsemi.com 2 TA = +25°C Symbol Parameter fMAX Maximum Clock Frequency Propagation Delay tPLH CP to Qn Propagation Delay tPHL CP to Qn tPHL Propagation Delay MR to Qn tOSHL Output to Output tOSLH Skew (Note 9) TA = −40°C to +85°C CL = 50 pF VCC (V) Min Typ CL = 50 pF Max Min 2.7 50 45 3.3 ± 0.3 90 75 Units Max MHz 2.7 4.0 9.6 17.6 3.0 20.0 3.3 ± 0.3 4.0 8.0 12.5 3.0 14.0 2.7 4.0 10.2 18.3 3.5 20.5 3.3 ± 0.3 4.0 8.5 13.0 3.5 14.5 2.7 4.0 10.2 18.3 3.5 20.0 3.3 ± 0.3 4.0 8.5 13.0 3.5 14.0 2.7 1.0 1.5 1.5 3.3 ± 0.3 1.0 1.5 1.5 ns ns ns ns Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Not tested. AC Operating Requirements TA = +25°C Symbol Parameter (V) tS Setup Time, HIGH or LOW Dn to CP tH Hold Time, HIGH or LOW Dn to CP tW Clock Pulse Width HIGH or LOW tW MR Pulse Width HIGH or LOW tW Recovery Time MR to CP TA = −40°C to +85°C CL = 50 pF VCC Typ CL = 50 pF Units Guaranteed Minimum 2.7 6.5 8.5 3.3 ± 0.3 5.0 6.0 2.7 0.0 0.0 3.3 ± 0.3 0.0 0.0 2.7 7.0 8.5 3.3 ± 0.3 5.5 6.0 2.7 7.0 8.5 3.3 ± 0.3 5.5 6.0 2.7 5.0 6.5 3.3 ± 0.3 4.0 4.5 ns ns ns ns ns Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = Open Conditions CPD (Note 10) Power Dissipation Capacitance 35 pF VCC = 3.3V Note 10: CPD is measured at 10 MHz. 3 www.fairchildsemi.com 74LVQ273 AC Electrical Characteristics 74LVQ273 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B www.fairchildsemi.com 4 74LVQ273 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com 74LVQ273 Low Voltage Octal D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Package Number MQA20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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