Ordering number : EN6002 LB1875 Monolithic Digital IC LB1875 Polygon Mirror Motor Predriver IC Overview Package Dimensions The LB1875 is a predriver IC for polygon mirror motors. By using a driver array or discrete transistors (FETs) at the output, motor drive with high rotation precision is possible. PAM drive or direct PWM drive can be selected for the output to realize high-efficiency control with minimum power loss. unit: mm 3235-HSOP36 [LB1875] 17.9 0.65 6.2 2.7 1 1.3 0.25 0.8 0.3 0.1 Features 2.5max 2.25 0.55 10.5 7.9 (4.9) 36 • • • • • • • • • • • • • • • Three-phase bipolar drive Direct PWM drive (bottom side) or PAM drive selectable PLL speed control circuit PWM oscillator Quartz oscillator Frequency divider FG with Schmitt comparator FG input single edge, dual edge selector circuit Integrating amplifier Phase lock detector output Current limiter Motor lock protection Thermal protection Forward/reverse circuit 5V regulator output SANYO : HSOP36 Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co., Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN D0898RM(KI) No. 6002-1/17 LB1875 Specifications Maximum Ratings at Ta = 25°C Parameter Symbol Maximum supply voltage VCC max Output current IO max Allowable power dissipation Pd max Conditions Ratings Unit 14.5 IC only V 30 mA 0.9 W 2.1 W 3 with substrate (114.3 x 76.1 x 1.6 mm , glass exposy) Operating temperature Topr – 20 to +80 °C Storage temperature Tstg – 55 to +150 °C Operation Conditions at Ta = 25°C Parameter Symbol Maximum supply voltage Conditions Ratings VCC1 VCC2 Output current Unit 8 to 13.5 4.5 to 5.5 When shorted between VCC and VREG IO V V 20 mA mA 5V regulated output current IREG 0 to –20 Voltage applied at LD pin V LD 0 to 13.5 LD pin output current IL D 0 to 10 Voltage applied at PWM pin VPWM 0 to 13.5 PWM pin output current IPWM 0 to 20 V mA V mA Pd max – Ta 2.4 Power dissipation, Pd max – W With substrate (114.3 x 76.1 x 1.6 mm, glass exposy) 2.1 2.0 1.6 1.2 1.18 IC only 0.9 0.8 0.5 0.4 0 –20 0 20 40 60 80 100 120 Ambient temperature, Ta – ˚C No. 6002-2/17 LB1875 Electrical Characteristics at Ta = 25 °C, VCC = 12V Parameter Symbol Ratings Conditions min Power supply current IC C Unit typ max 30 40 mA [5V regulated output ] Output fluctuation VREG 5.0 5.35 V Voltage fluctuation ∆VREG1 VCC=8 to 13.5V 4.65 40 100 mV Load fluctuation ∆VREG2 IO=0 to –15 mA 20 100 Temperature coefficcient ∆VREG3 Design target value mV 0 mV/°C [Output Section] Output saturation voltage Output leak current VO(sat)1-1 UH, VH, WH "L" level, IO=50 µA 0.1 0.3 V Vo(sat)1-2 UH, VH, WH "L" level, IO=10 mA 0.9 1.1 V VCC–0.9 VCC–1.1 V 0.2 0.4 V 10 µA VO(sat)2 UH, VH, WH "L" level, IO=20 mA VO(sat)3 UL, VL, WL, IO=20 mA IOleak UL, VL, WL [Hall amplifier] Input bias current Same-phase input voltage range IHB(HA) –4 VICM 0 Hall input sensitivity Hysteresis width µA –1 VCC–2.0 30 ∆VIN(HA) 8 V mVP-P 14 24 mV Input voltage L->H VSLH 7 mV Input voltage H->L VSHL –7 mV [FG/Schmitt comparator section] IB(FGS) –4 Same-phase input voltage range VICM(FGS) 0 Input sensitivity VIN(FGS) 30 Input bias current µA –1 VCC–2.0 V mVP-P Hysteresis width ∆VIN(FGS) Design target value Input voltage L->H VSLH(FGS) Design target value 7 mV Input voltage H->L VSHL(FGS) Design target value –7 mV 8 14 24 mV [PWM oscillator] Output High level voltage VOH(OSC) 2.7 3.0 3.3 Output Low level voltage VOL(OSC) 1.5 1.8 2.1 Oscillator frequency f(OSC) Amplitude V(OSC) C=2200 pF 30 1.0 V V kHz 1.2 1.4 VP-P 0.9 2.0 V 10 µA [PWM output] Output saturation voltage Output leak current VOL(PWM) IPWM=15 mA IL(PWM) VO=VCC [CSD oscillator ] Output High level voltage VOH(CSD) 2.5 2.8 3.1 V Output Low level voltage VOL(CSD) 0.55 0.85 1.15 V External C charge current ICHG 1 –13 –10 –7 µA External C discharge current ICHG 2 7 10 13 Oscillator frequency fCSD Amplitude VCSD C=0.068 µF 35 1.75 1.95 VREG–0.2 VREG–0.1 µA Hz 2.15 VP-P 0.2 V –0.6 mA [Phase comparator output] Output High level voltage VPDH IOH=–100 µA Output Low level voltage VPDL IOH=100 µA Output source current IPD+ VPD=VREG/2 Output sink current IPD– VPD=VREG/2 VOL(LD) ILD=10 mA 0.1 V 1.5 mA [Phase lock detector output] Output saturation voltage Output leak current IL(LD) VO=VCC 0.1 0.4 V 10 µA Continued on next page No. 6002-3/17 LB1875 Continued from preceding page Parameter Symbol Ratings Conditions min typ Unit max [ERR amplifier] Input offset voltage VIO(ER) Input bias current IB(ER) Design target value –10 +10 mV –1 +1 µA 0.9 1.2 V Ouput High level voltage VOH(ER) IOH = –500 µA Ouput Low level voltage VOL(ER) IOL=500 µA DC bias level VB(ER) –5% VREG/2 + 5% V VRF 0.45 0.5 0.55 V VREG–1.2 VREG–0.9 V [Current limiter] Limiter voltage [Low-voltage protection circuit] Operation voltage VSDL 3.55 3.75 3.95 V Release voltage VSDH 3.8 4.0 4.2 V Hysteresis width ∆VSD 0.15 0.25 0.35 °C 150 180 °C 30 °C [Thermal shutdown operation] Termal shutdown temperature Hysteresis width TSD Design target value (junction temperature) ∆TSD Design target value (junction temperature) [SOFT pin] Stop voltage VSFT 3.0 3.3 3.6 External C discharge current ID C H G In stop condition 4 6 8 µA V fOSC 2 10 MHz [Quartz oscillator] Quartz oscillator frequency Low level pin voltage VOSCL IOSC=–0.5 mA High level pin voltage VOSCH VOSC=VOSCL+0.6V 1.45 V 0.5 mA [CLKOUT pin] Output saturation voltage VOL(CKOUT) ICKOUT=2 mA Output leak current IL(CKOUT) VO=VCC 0.1 0.4 V 10 µA kHz [CLKIN pin] fI(CKIN) 0.1 10 High level input voltage VIH(CKIN) 3.5 VREG V Low level input voltage VIL(CKIN) 0 1.5 V Input open voltage VIO(CKIN) VREG–0.5 VREG V Hysteresis width VIS(CKIN) 0.3 0.4 0.5 V High level input current IIH(CKIN) VCKIN=VREG –10 0 +10 Low level input current IIL(CKIN) VCKIN=0V –200 –140 External input frequency µA µA [S/S pin] High level input voltage VIH(SS) 3.5 VREG V Low level input voltage VIL(SS) 0 1.5 V Input open voltage VIO(SS) VREG–0.5 Hysteresis width VIS(SS) 0.3 High level input current IIH(SS) VS/S=VREG Low level input current IIL(SS) VS/S=0V VREG V 0.4 0.5 V –10 0 +10 –200 –140 µA µA [F/R pin] High level input voltage VIH(FR) 3.5 VREG V Low level input voltage VIL(FR) 0 1.5 V Input open voltage VIO(FR) VREG–0.5 VREG V High level input current IIH(FR) VF/R=VREG Low level input current IIL(FR) VF/R=0V –10 0 –200 –140 +10 µA µA [FGSEL pin] High level input voltage VIH(FSEL) Low level input voltage VIL(FSEL) Input open voltage VIO(FSEL) High level input current IIH(FSEL) VFSEL=VREG –10 0 Low level input current IIL(FSEL) VFSEL=0V –200 –140 3.5 VREG V 0 1.5 V VREG–0.5 VREG V +10 µA µA Continued on next page No. 6002-4/17 LB1875 Continued from previous page Parameter Symbol Ratings Conditions min Unit typ max [CLKSEL pin] High level input voltage VIH(CSEL) 4.0 VREG V Middle level input voltage VIM(CSEL) 2.0 3.0 V V Low level input voltage VIL(CSEL) 0 1.0 Input open voltage VIO(CSEL) VREG–0.5 VREG V High level input current IIH(CSEL) VCSEL=VREG –10 0 +10 µA Low level input current IIL(CSEL) VCSEL=0V –200 –140 µA [LIM pin] High level input voltage VIH(LIM) 3.5 VREG V Low level input voltage VIL(LIM) 0 1.5 V Input open voltage VIO(LIM) High level input current IIH(LIM) VLIM=VREG Low level input current IIL(LIM) VLIM=0V VREG–0.5 –10 0 –200 –140 VREG V +10 µA µA 3-phase logic truth table (IN = “H” indicates the IN+ > IN– condition) F/R= "L" Output F/R= "H" IN1 IN2 IN3 IN1 IN2 IN3 SOURCE SYNC 1 H L H L H L VH UL 2 H L L L H H WH UL 3 H H L L L H WH VL 4 L H L H L H UH VL 5 L H H H L L UH WL 6 L L H H H L VH WL S/S pin CLKSEL pin FGSEL pin Input state Condition Input state Edge detection Input state Divisor High or open Stop L Start High or open FG dual edge High or open 1024 x 4 L FG single edge M 1024 L 1024 x 3 LIM pin Input state Output pin (UH, VH, WH) High or open No PWM (PAM operation) PWMOUT pin PWM output L PWM (direct PWN operation) FG/Schmitt comparator output VH WL WH RF PWMOUT 27 26 25 24 23 22 21 20 19 10 11 12 13 14 15 16 17 18 EI EO TOC SOFT CPWM 28 VL IN3– 29 PD IN3+ 30 UH IN2– 31 LD2 IN2+ 32 UL IN1– 33 LD1 IN1+ 34 VCC FGIN– 35 LIM FGIN+ 36 GND CSD Pin Assignment 2 3 4 5 6 7 8 9 XI XO S/S CLKSEL CLKIN CLKOUT F/R FGSEL GND 1 VREG LB1875 A11348 No. 6002-5/17 LB1875 Block Diagram and Sample Application Circuit (Sample application: PAM drive, FET output) VREG LD2 FGIN– LD1 PD EI – FGIN+ FG FILTER + VREG LD – – EO + + FG SELECT FGSEL TOC CLKIN 12V + CLK PLL LVSD CLKOUT PWM OUT TSD 24V + CLK SELECT CLKSEL XI COMP OSC XO ECL 1/8 PWM 1/128 1/384 1/512 VCC + VREG CPWM S/S VREG VREG PWM OSC UL S/S UH F/R CSD F/R PRI DRIVER LOGIC VH WL HALL LOGIC SD OSC WH CURR LIM HALL HYS AMP IN1+ IN1– VL IN2+ IN2– IN3+ IN3– SOFT LIM RF GND VCC A11596 Note: For applications where the motor has variable speed and control at low motor voltages is required, the base voltage of the output interface transistor must be made low. In this case, a P-channel FET which can be used at low gate voltages must be selected. No. 6002-6/17 LB1875 (Sample application: direct PWM drive, FET output) VREG LD2 FGIN– LD1 PD EI – FGIN+ FG FILTER + LD VREG – – EO + + FG SELECT FGSEL TOC CLKIN CLK VREG PLL FGS LVSD CLKOUT TSD PWMOUT 12V CLK SELECT CLKSEL + XI COMP OSC XO ECL 1/8 PWM 1/128 1/384 1/512 24V VCC + VREG CPWM S/S VREG VREG PWM OSC UL S/S UH F/R CSD F/R PRI DRIVER LOGIC VH WL HALL LOGIC SD OSC WH CURR LIM HALL HYS AMP IN1+ IN1– VL IN2+ IN2– IN3+ IN3– SOFT LIM RF GND VCC A11597 No. 6002-7/17 LB1875 (Sample application: PAM drive, bipolar transistor output) VREG LD2 FGIN– LD1 PD EI – FGIN+ FG FILTER + VREG LD – – EO + + FG SELECT FGSEL TOC CLKIN 5V + CLK PLL LVSD CLKOUT PWM OUT TSD + CLK SELECT CLKSEL XI COMP OSC XO ECL 1/8 24V PWM 1/128 1/384 1/512 VCC + VREG CPWM S/S VREG VREG PWM OSC UL S/S UH F/R CSD F/R PRI DRIVER LOGIC VH WL HALL LOGIC SD OSC WH CURR LIM HALL HYS AMP IN1+ IN1– VL IN2+ IN2– IN3+ IN3– SOFT LIM RF GND VCC A11598 No. 6002-8/17 LB1875 Description of the LB1875 1. Speed control circuit This IC uses the PLL speed control technique which allows stable, high-precision motor rotation with low jitter. The PLL circuit performs phase comparison of the falling edge of the clock input (CLKIN) with the edge of the FG input. Control is based on the differential output. When the FGSEL pin is Low, only the falling edge of the FG signal is valid. When the pin is High or open, both edges are valid. When both edges are used, the FG waveform precision becomes critical. When using an external clock input (supplied from CLKIN pin), the FG servo frequency is determined by the following equation. fFG (servo) = f CLK (FGSEL = Low) fFG (servo) = f CLK/2 (FG SEL = High or open) When using the internal clock, the FG servo frequency is determined by the following equation. The number of FG pulses and the quartz oscillator frequency determine the motor rotation speed. fFG (servo) = f OSC/N (FGSEL = Low) fFG (servo) = f OSC/2N (FGSEL = High or open) fOSC: Quartz oscillator frequency N: Clock divisor (see table) 2. Output drive This IC allows selection of PAM drive or direct PWM drive. When the LIM pin is Low, the direct PWM mode is selected. The ON duty cycle of the UH, VH, and WH output (external bottomside transistor drive output) changes, thereby controlling the motor speed. Current control is also realized by changing the ON duty cycle to limit the current. At this time, the Schmitt comparator output of the FG is supplied at the PWM OUT pin. When bipolar transistors are used externally, the top-side transistors should not have an integrated diode, but Schottky barrier diodes should be used instead (to prevent feedthrough current caused by diode reverse recovery during PWM switching). When the LIM pin is High or open, the PAM drive mode is selected. The PWMOUT pin carries the PWM signal. This output can drive an external switching regulator circuit for varying the motor supply voltage and thereby controlling motor speed. Current control is also realized by changing the motor supply voltage. In this case, a delay in the switching regulator circuit will cause a delay in the current control action. During the delay, a higher current than the set current may flow, which must be taken into consideration when selecting output transistors. For applications where the motor has variable speed and control at low motor voltages is required, the lowest operation voltage is limited by the base voltage of the interface transistor for top-side output transistor drive. If this causes a problem, the base voltage must be made low (for example by dividing the VREG voltage with resistors). When FETs are used as topside output transistors, types which can be used at low gate voltages must be selected. 3. Current limiting circuit The current limiting circuit limits the peak current to the value I = VRF/Rf (V RF = 0.5V typ., Rf: current detector resistor). As mentioned above, in PAM drive mode, a current higher than the set current may flow during the delay interval. If the capacitor charge current of the switching regulator circuit is a problem, a smoothing capacitor may be inserted, with the negative side connected to the RF pin. If PWM noise is a problem in the RF waveform, a filter should be provided at the input. No. 6002-9/17 LB1875 4. Reference clock Since the clock input of the PLL circuit (CLKIN) and the internal divisor output (CLKOUT) are separate, various applications are possible. (1) Using the internal divider circuit Basically, CLKIN and CLKOUT are shorted. If a division ratio other than the built-in ratio is required, an external divider circuit can be inserted between these two pins. [1] Using a quartz oscillator An oscillator using a quartz crystal and C, R components can be configured as shown below. XI XO C1, R1 : For stable oscillation C2 : For overtone oscillation prevention C3 C3 : For crystal coupling C1 C2 R1 VREG A11349 (Reference values) Oscillator frequency (MHz) C1 (µF) 2 to 3 3 to 7 R1 ( Ω) C2 (pF) C3 (pF) 0.1 10 100 330k 0.1 None 47 330k 7 to 9 0.1 None 22 330k 9 to 10 0.1 None 12 330k The circuit configuration and values are for reference only. The quartz crystal characteristics as well as the possibility of floating capacitance and noise due to layout factors must be taken into consideration when designing an actual application. [Precautions for wiring layout design] Since the quartz oscillator circuit operates at high frequencies, it is susceptible to the influence of floating capacitance from the circuit board. Wiring should be kept as short as possible and traces should be kept narrow. [2] External clock input (equivalent to quartz oscillator, several MHz) When using an external signal source instead of a quartz oscillator, a resistor of about 13 kΩ should be inserted in series at the XI input. The XO pin should be left open. Signal input level Low: 0 to 0.8 V High: 2.5 to 5 V (2) When not using the internal divider circuit When using an external signal source to supply a signal equivalent to the FG frequency (several kHz), the signal is input via the CLKIN pin. When not using a quartz oscillator, the XI pin should be left open or connected to the VREG pin (XO is open). 5. Hall input signal The Hall input requires a signal with an amplitude of at least the hysteresis width (24 mV max.). Taking possible noise influences into consideration, an amplitude of at least 100 mV is desirable. If noise at the Hall input is a problem, a noise-canceling capacitor (about 0.001 to 0.1 µF) should be connected across the Hall input pins . Since the same-phase input range is 0 to VCC–2V, a Hall element can be connected in series if 12V is applied at the VCC pin. 6. FG input signal The FG input is designed mainly for input from a Hall element and has the same specifications as the Hall input. If the input is to be used for an FG pattern or other very low-level signal, an external amplifier must be used to amplify the signal first. When there is noise at the FG input, locking may be impaired and jitter may increase. If PWM switching noise or other noise is found to be present, countermeasures such as making the Hall element power supply more stable or connecting a capacitor across the input will be necessary. No. 6002-10/17 LB1875 7. PWM frequency The PWM frequency is determined by the capacitance connected to the CPWM pin. . f PWM =. 1/(15000 x C) The PWM frequency should be between 15 and 50 kHz. If the frequency is too low, noise and control performance may be a problem. If it is too high, switching losses will increase. 8. LD output The LD1 output is ON when phase lock is achieved. Phase lock is evaluated only by the phase (through edge comparison), not by speed deviation. Therefore when LD1 is ON, speed deviation is affected by the FG signal acceleration for example when establishing the lock condition. (The lower the acceleration, the lower the speed deviation.) When it is necessary to limit speed deviation when LD1 is ON, the results of actual motor speed measurement must be applied. 9. Power supply When using FETs as bottom-side output transistors, applying a voltage of 12V to the VCC pin makes it possible to supply a gate voltage of about 10V. When using FETs or bipolar transistors that can handle a low gate voltage, the VCC and VREG pins can also be short- circuited to apply 5V. (In this case, do not apply voltage higher than 5.5V.) Since this IC is designed for use in high-current motors, the power supply line may fluctuate easily. Therefore a capacitor of sufficient capacitance must be provided between the VCC pin and ground, to assure stable operation. If a diode is used in the power line for reverse-connection protection, power line fluctuations may be further increased, which will require more capacitance. 10. Motor lock protection circuit To protect the IC and the motor itself when rotation is inhibited, a motor lock protection circuit is provided. If the LD output is High (unlocked) for a certain interval in the start condition, the external bottom-side transistors are turned off. The length of the interval is determined by the capacitance at the CSD pin. A capacitance of 0.1 µF results in a trigger interval of about 10 seconds. . Trigger interval (S) =. 110 x C (µF) The trigger interval should be set so as to leave sufficient leeway for motor startup. Speed reduction due to clock frequency switching does not trigger the protection circuit. When the protection circuit has been triggered, the condition can only be canceled by setting the system to the stop condition or by turning the power off and on again. When wishing not to use the motor lock protection circuit, connect the CSD pin to ground. 11. Low voltage protection circuit The low voltage protection circuit cuts off the bottom-side output transistors (external) when the voltage at the VREG pin falls below 3.75V (typ.). The circuit action is released when the voltage rises above approx. 4.0V (typ.). 12. F/R switching Forward/reverse switching in principle should be carried out while the motor is stopped. If switching is carried out while the motor is running, feedthrough current (due to output transistor delay) is prevented by the circuit design, but a high current will flow in the output transistors (due to counterelectromotive voltage and coil resistance). If such a condition is anticipated, the output transistors must be selected appropriately, to allow handling even higher current than in normal use. 13. Soft start In PAM drive mode, connecting a capacitor (approx. 0.01 to 0.1 µF) between the SOFT pin and ground enables soft start (gradual increase in PWM ON duty cycle, causing a sloped rise in motor supply voltage). This prevents the current flow exceeding the set current due to switching regulator circuit delay at startup. The Soft start function is active only immediately after motor startup. When the motor is stopped, the output transistors are turned off, therefore the charge accumulated in the switching regulator smoothing capacitors can only be discharged as leak current of the output transistors. When the motor is restarted before the supply voltage has dropped, the soft start function will not be active. Therefore it is necessary to discharge the capacitors via a resistor so that the soft start function operates properly. No. 6002-11/17 LB1875 Pin Descriptions Pin number Pin name 1 VREG Equivalent circuit Pin function 5V regulator output (control circuit power supply) For stable operation, pin should be connected to ground via a capacitor (0.1 µF or more). VCC 1 A11350 2 XI 3 XO Pin 2: Quartz oscillator input. Maximum oscillation frequency is 10 MHz Pin 3: Quartz oscillator output Generates reference clock. When an VREG 3 2 external clock (several MHz) is used, connect a resistor of about 13 kΩ in series to the XI pin, so that the signal is input via the resistor. Leave the X O pin open. A11351 4 S/S Start/stop pin Low: Start High: Stop High when open. VREG 30 kΩ 5.6 KΩ 4 A11352 5 CLKSEL Divisor selector pin "L": (divisor 3072): 0 to 1.0V "M": (divisor 1024): 2.0 to 3.0V "H": (divisor 4093): 4.0V to VREG VREG High when open. 30 kΩ 5.6 kΩ 5 A11353 Continued on next page No. 6002-12/17 LB1875 Continued from preceding page Pin number Pin name 6 CLKIN Equivalent circuit Pin function Clock input (max. 10 kHz) Low: 0 to 1.5V High: 3.5V to VREG High when open. VREG 30 kΩ 5.6 KΩ 6 A11354 7 CLKOUT Quartz oscillator divider output Ratio is selected with pin 5. Open collector output VREG 7 A11355 8 F/R Forward/reverse switching pin Low: 0 to 1.5V High: 3.5V to VREG High when open. VREG 30 kΩ 5.6 kΩ 8 A11356 9 FGSEL VREG 30 kΩ 5.6 kΩ 9 FG comparator selector pin Low: 0 to 1.5V –> Speed control on FG single edge High: 3.5V to VREG –> Speed control on FG dual edge High when open. A11357 10 LIM Drive mode selector pin Low: 0 to 1.5V –> Direct PWM drive mode High: 3.5 V to VREG VREG 30 kΩ 5.6 kΩ 10 –> PAM drive mode High when open. A11358 Continued on next page No. 6002-13/17 LB1875 Continued from preceding page Pin number Pin name 11 LD1I Equivalent circuit Pin function Phase lock detector output On when PLL phase lock is achieved. Open collector output VREG 12 11 12 LD2 Phase lock detector output (LD1 inverted output) On when PLL phase lock is achieved. Open collector output A11359 13 PD Phase comparator output (PLL output) Outputs the phase difference as a signal with changing pulse duty cycle. The higher the duty cycle, the higher the output current. VREG 13 A11360 14 EI Differential amplifier input VREG 200Ω 14 A11361 15 EO Differential amplifier output Output current increases at Low. VREG 15 20 kΩ A11362 16 TOC Torque control input Normally connected to EO pin. When TOC pin goes Low, duty cycle of UH, VH, WH (direct PWM mode) or PWM output (PAM mode) changes, resulting in increased torque. VREG 17 SOFT 200Ω 17 200Ω 16 A11363 Soft start control pin Connect to ground via a capacitor. Leave open when soft start is not to be used. Continued on next page No. 6002-14/17 LB1875 Continued from preceding page Pin number Pin name 18 PWM Equivalent circuit Pin function PWM oscillator pin Connect to ground with a capacitor to set oscillation frequency. VREG 200Ω 18 2 kΩ A11364 19 PWMOUT PWM output Open collector output (Darlington connection). In direct PWM mode (LIM pin Low) the output is an FG Schmitt output. VREG 19 A11365 20 RF Output current detector pin Connect to ground via a lower resistor. Sets maximum output current IOUT = VREG 0.5/Rf. 5 kΩ 23 A11366 21 WH 23 VH 25 UH VCC Output pin (for external bottom-side transistor drive) Performs duty cycle control in direct PWM mode (LIM pin Low). 21 23 25 A11367 22 WL 24 VL 26 UL Output pin (for external bottom-side transistor drive) . Open collector output. VCC 22 24 26 A11368 Continued on next page No. 6002-15/17 LB1875 Continued from preceding page Pin number Pin name 27 V CC 33 IN1+ 32 IN1– 31 IN2+ 30 IN2– 29 IN3+ 28 IN3– Equivalent circuit Pin function Power supply pin (output and regulator circuit power supply). Connect to ground via capacitor to prevent noise. When using the IC with a single 5V source, short this pin to the VREG pin. Hall inputs for various phases Logic "High" indicates VIN+>V IN-. VCC 29 28 31 30 200Ω 33 200Ω 32 A11369 + IN 35 FG 34 FGIN– FG comparator input Pin 35: Non-inverted input Pin 36: Inverted input VCC 35 34 200Ω 200Ω A11370 36 CSD VREG 200Ω 19 Reference signal oscillator for motor lock protection circuit, clock interruption error protection circuit etc. Connect to ground via capacitor. Connect directly to ground if protection circuit is not to be used. A11371 FRAME GND Ground No. 6002-16/17 LB1875 Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1998. Specifications and information herein are subject to change without notice. PS No. 6002-17/17