SANYO LB11822

Ordering number : ENN7105
Monolithic Digital IC
LB11822
Three-Phase Brushless Motor Driver for OA Products
Overview
Package Dimensions
The LB11822 is a three-phase brushless motor driver that
is optimal for driving drum and paper feed motors in laser
printers and plain paper copiers. This IC adopts a direct
PWM drive technique for minimal power loss. Flexible
control of motor speed in response to an externally
provided clock frequency (corresponding to the FG
frequency) can be implemented by using the LB11822 in
conjunction with the Sanyo LB11825M.
unit: mm
3147B-DIP28H
[LB11822]
0.4
R1.7
Functions and Features
1
14
20.0
27.0
4.0
Three-phase bipolar drive (30 V, 3.1 A)
Direct PWM drive
Built-in low side inductive kickback absorbing diode
Speed discriminator + PLL speed control
Speed locked state detection output
Built-in forward/reverse switching circuit
Full complement of built-in protection circuits,
including current limiter circuit, thermal protection
circuit, and motor lock protection circuit.
4.0
•
•
•
•
•
•
•
15
12.7
11.2
8.4
28
1.93
1.78
0.6
1.0
SANYO: DIP28H
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Supply voltage
VCC max
Output current
IO max
Conditions
Ratings
Unit
30
T ≤ 500 ms
Allowable power dissipation 1
Pd max1
Independent IC
Allowable power dissipation 2
Pd max2
When infinitely large heat sink
V
3.1
A
3
W
20
W
Operating temperature
Topr
–20 to +80
°C
Storage temperature
Tstg
–55 to +150
°C
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N1703SI (OT) No. 7105-1/11
LB11822
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage range 1
VCC
9.5 to 28
V
Voltage output current
IREG
0 to – 30
mA
LD output current
ILD
0 to 15
mA
Electrical Characteristics at Ta = 25°C, VCC = VM = 24 V
Parameter
Symbol
Supply Current 1
ICC1
Supply Current 2
ICC2
Conditions
Ratings
min
typ
Unit
max
23
30
mA
When stopped
3.5
5
mA
[Output Block]
Output saturation voltage 1
VOsat1
IO = 1.0 A, VO (SINK)+ VO (SOURCE)
2.0
2.5
Output saturation voltage 2
VOsat2
IO = 2.0 A, VO (SINK)+ VO (SOURCE)
2.6
3.2
V
Output leakage current
IOleak
100
µA
V
Lower side diode forward voltage 1
VD1
ID = –1.0 A
1.2
1.5
V
Lower side diode forward voltage 2
VD2
ID = –2.0 A
1.5
2.0
V
[5 V Voltage Output]
Output voltage
VREG
IO = –5 mA
5.00
5.35
V
Voltage regulation
∆VREG1
VCC = 9.5 to 28 V
4.65
30
100
mV
Load regulation
∆VREG2
IO = –5 to –20 mA
20
100
mV
[Hall Amplifier]
Input bias current
Common-mode input voltage range
IHB
–2
VICM
1.5
Hall input sensitivity
–0.5
µA
VREG–1.5
80
V
mVP-P
Hysteresis
∆VIN
Input voltage low→ high
VSLH
12
mV
Input voltage high→ low
VSHL
–12
mV
15
24
42
mV
[PWM Oscillator Circuit]
High-level output voltage
VOH(PWM)
2.5
2.8
3.1
V
Low-level output voltage
VOL(PWM)
1.2
1.5
1.8
V
1.05
1.30
1.55
VP-P
Oscillator frequency
f(PWM)
Amplitude
V(PWM)
C = 3900 pF
18
kHz
[CSD Circuit]
Operating voltage
External C charging current
Operating time
VOH(CSD)
3.6
3.9
4.2
V
ICHG
–17
–12
–9
µA
T(CSD)
C = 10 µF Design target value*
3.3
s
[Current Limiter Operation]
Limiter
VRF
VCC–VM
0.45
0.5
TSD
Design target value* (junction temperature)
150
180
°C
∆TSD
Design target value* (junction temperature)
50
°C
0.55
V
[Thermal Shutdown Operation]
Thermal shutdown operating temperature
Hysteresis
[FG Amplifier]
Input offset voltage
Input bias current
VIO(FG)
–10
+10
mV
IB(FG)
–1
+1
µA
Output H level voltage
VOH(FG)
IFGO = –0.2 mA
Output L level voltage
VOL(FG)
IFGO = 0.2 mA
FG input sensitivity
Gain: 100
Schmitt amplitude for the next stage
Design target value*
VREG–1.2 VREG–0.8
0.8
3
100
f(FG) = 2 kHz
45
V
mV
180
Operating frequency range
Open-loop gain
V
1.2
51
250
mV
2
kHz
dB
Note: * These are design target values and are not tested.
Continued on next page.
No. 7105-2/11
LB11822
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
min
typ
Unit
max
[Speed Discriminator]
Output H level voltage
VOH(D)
IDO = –0.1 mA
Output L level voltage
VOL(D)
IDO = 0.1 mA
VREG–1.0 VREG–0.7
0.8
Number of counts
V
1.1
V
512
[PLL Output]
Output H level voltage
VOH(P)
IPO = –0.1 mA
Output L level voltage
VOL(P)
IPO = 0.1 mA
VOL(LD)
ILD = 10 mA
VREG–1.8 VREG–1.5
1.2
VREG–1.2
1.5
1.8
0.15
0.5
V
V
[Lock Detection]
Output L level voltage
Lock range
6.25
V
%
[Integrator]
Input bias current
IB(INT)
–0.4
Output H level voltage
VOH(INT) IINTO = –0.2 mA
Output L level voltage
VOL(INT)
IINTO = 0.2 mA
Open-loop gain
f(INT) = 1 kHz
Gain width product
Design target value*
Reference voltage
Design target value*
+0.4
VREG–1.2 VREG–0.8
0.8
45
51
–5%
VREG/2
µA
V
1.2
V
dB
450
kHz
5%
V
[Clock Input Pin]
Operating frequency range
fOSC
1
L level pin voltage
VOSCL
IOSC = –0.5 mA
H level pin current
IOSCH
VOSC = VOSCL+0.5 V
MHz
1.55
V
0.4
mA
[Start/Stop Pin]
H level input voltage range
VIH(S/S)
3.5
VREG
V
L level input voltage range
VIL(S/S)
0
1.5
V
Input open voltage
VIO(S/S)
VREG
V
Hysteresis
VREG–0.5
∆VIN
H level input current
IIH(S/S)
V(S/S) = VREG
L level input current
IIL(S/S)
V(S/S) = 0 V
0.35
0.50
0.65
V
–10
0
10
µA
–280
–210
µA
[Forward/Reverse Pin]
H level input voltage range
VIH(F/R)
3.5
VREG
V
L level input voltage range
VIL(F/R)
0
1.5
V
Input open voltage
VIO(F/R)
VREG
V
Hysteresis
VREG–0.5
∆VIN
H level input current
IIH(F/R)
V(F/R) = VREG
L level input current
IIL(F/R)
V(F/R) = 0 V
0.35
0.50
0.65
V
–10
0
+10
µA
–280
–210
µA
Note: * These are design target values and are not tested.
No. 7105-3/11
LB11822
Allowable power dissipation, Pdmax—W
Infinitely large heat sink
Independent IC
Ambient temperature, Ta —°C
Truth Table
Source
F/R = "L"
Sink
F/R = "H"
IN1
IN2
IN3
IN1
IN2
IN3
1
OUT2 → OUT1
H
L
H
L
H
L
2
OUT3 → OUT1
H
L
L
L
H
H
3
OUT3 → OUT2
H
H
L
L
L
H
4
OUT1 → OUT2
L
H
L
H
L
H
5
OUT1 → OUT3
L
H
H
H
L
L
6
OUT2 → OUT3
L
L
H
H
H
L
The relation between the clock frequency, fCLK, and the FG frequency, fFG, is given by the following equation.
fFG(servo) = fCLK/<number of counts>
= fCLK/512
Pin Assignment
OUT1
F/R
IN3+
IN3-
IN2+
IN2-
IN1+
28
27
26
25
24
23
22
IN1- GND1
21
20
S/S
19
FGIN+ FGIN- FGOUT LD
18
17
16
15
11
12
13
14
LB11822
1
2
3
4
OUT2 OUT3 GND2 VCC
5
VM
6
7
VREG PWM
8
9
10
CSD
XI
XO
INTOUT INTIN POUT DOUT
Top view
No. 7105-4/11
LB11822
Equivalent Circuit Block Diagram and Peripheral Circuits
No. 7105-5/11
LB11822
Pin Function
Pin No.
Pin
28
OUT1
1
OUT2
2
OUT3
3
GND2
Function
Motor drive output pin
Equivalent circuit
VCC
300 Ω
Connect the Schottky diode between the output – VCC.
VM
5
Output GND pin
1
5
4
VM
VCC
2
28
Power and output current detection pins of the output. Connect a
low resistance (Rf) between this pin and VCC.
The output current is limited to the current value set with IOUT =
VRF/Rf.
3
Power pin (Other than the output)
VCC
Stabilized power supply output pin (5 V output)
6
VREG
6
Connect a capacitor (about 0.1 µF) between this pin and GND for
stabilization
VREG
Pin to set the PWM oscillation frequency.
7
PWM
Connect a capacitor between this pin and GND.
200 Ω
2 kΩ
This can be set to about 18 kHz with C =3900 pF.
7
VREG
Pin to set the operation time of motor lock protection circuit.
CSD
Connection of a capacitor (about 10 µF) between CSD and GND
can set the protection operation time of about 3.3seconds.
300 Ω
1 kΩ
8
8
Continued on next page.
No. 7105-6/11
LB11822
Continued from preceding page.
Pin No.
Pin
Function
Equivalent circuit
VREG
9
XI
10
XO
Clock input pin, which enters the clock signal (1 MHz or less) to
the XI pin via resistor (about 5.1 kΩ).
Keep the XO pin open.
10
9
VREG
INT
OUT
11
Integrating amplifier output (speed control pin).
40 kΩ
11
PWM Comparator
VREG
12
INT
IN
Integrating amplifier input pin
300 Ω
12
VREG
300 Ω
13
POUT
13
PLL output pin
Continued on next page.
No. 7105-7/11
LB11822
Continued from preceding page.
Pin No.
Pin
Function
Equivalent circuit
VREG
14
DOUT
300 Ω
Speed discriminator output.
14
Accelerate: high, decelerate: low
VREG
15
Speed lock detection output.
15
LD
L when the motor speed is within the speed lock range (±6.25%).
Voltage resistance 30 Vmax
VREG
FG
OUT
16
FG amplifier output pin
40 kΩ
16
FG schmidt comparator
17
20 kΩ
VREG
FGIN–
FG Reset
FG amplifier input pin.
18
18
300 Ω
300 Ω
17
20 kΩ
Connection of a capacitor (about 0.1 µF) between FGIN+ and
GND causes initial reset to the logic circuit.
FGIN+
VREG
Low: 0 V to 1.5 V
19
S/S
High: 3.5 V to VREG
H level when open.
22 kΩ
Start/stop control pin.
2 kΩ
19
Hysteresis width about 0.5 V
Continued on next page.
No. 7105-8/11
LB11822
Continued from preceding page.
Pin No.
Pin
20
GND1
Function
Equivalent circuit
GND pin (Other than the output)
VREG
22
IN1+
Hall amplifier input.
21
IN1–
24
IN2+
IN+ > IN– is the input high state, and the reverse is the input low
state.
23
IN2–
26
IN3+
25
IN3–
It is recommended that the Hall signal has an amplitude of 100m
Vp-p (differential) or more.
21
23
25
300 Ω
300 Ω
22
24
26
Connect a capacitor between the IN+ and IN– inputs if there is
noise in the Hall sensor signals.
VREG
Low: 0 V to 1.5 V
27
F/R
High: 3.5 V to VREG
H level when open
Hysteresis width about 0.5 V
22 kΩ
Forward/reverse control pin
2 kΩ
27
Overview of the LB11822
1. Speed control circuit
This IC performs speed control by using both the speed discriminator circuit and PLL circuit. The speed control circuit
outputs the error signal once for every two cycles of FG (one FG cycle counted). The PLL circuit outputs the phase
error signal once for each cycle of FG.
As the FG servo frequency is calculated as follows, the motor speed is set with the number of FG pulses and clock
frequency.
fFG(servo) = fCLK/512
fCLK: Clock frequency
This IC achieves variable speed control with ease when combined with LB11825M.
2. Output drive circuit
This IC employs a direct PWM drive method to minimize the power loss at output. The output Tr is always saturated
at ON, and the motor drive force is adjusted through change of the duty at which the output is turned ON. Since the
output PWM switching is made with the lower-side output Tr, it is necessary to connect the schottky diode between
OUT and VCC (because the through current flows at an instant when the lower-side Tr is turned ON if the diode with a
short reverse recovery time is not used). The diode between OUT and GND is incorporated. When the large output
current presents problem (waveform disturbance at kickback on the lower side), connect a commutating diode or
schottky diode externally.
3. Current limiting circuit
The current limiting circuit performs limiting with the current determined from I = VRF/Rf (VRF = 0.5 Vtyp, Rf:
current detector resistance) (that is, this circuit limits the peak current).
Limiting operation includes decrease in the output on-duty to suppress the current.
No. 7105-9/11
LB11822
4. Power save circuit
This IC enters the power save condition to decrease the current dissipation in the stop mode. In this condition, the bias
current of most of circuits is cut off. Even in the power save condition, the 5 V regulator output is given.
5. Reference clock
This is entered from the external signal source (1 MHz max) via a resistor (reference: about 5.1 kΩ) in series with the
XI pin. The XO pin is left open.
Input signal source levels:
Low-level voltage: 0 to 0.8 V
High-level voltage: 2.5 to 5.0 V
6. Speed lock range
The speed lock range is ±6.25% of the constant speed. If the motor speed falls inside the lock range, the LD pin goes
to “L” (open collector output). When the motor speed falls outside the lock range, the on-duty ratio of motor drive
output changes according to the speed error, causing control to keep the motor speed within the lock range.
7. PWM frequency
PWM frequency is determined from the capacity C (F) of capacitor connected to the PWM pin.
fPWM ≈ 1/(14,400 × C)
It is recommended to keep the PWM frequency at 15 kHz to 25 kHz
8. Hall input signal
The Hall input requires the signal input with an amplitude exceeding the hysteresis width (42 mV max). Considering
the effect of noise, the input with the amplitude of 100 mV or more is recommended.
9. F/R changeover
Motor rotation direction can be changed over with the F/R pin. When changing F/R while the motor is running, pay
attention to following points.
• For the through current at a time of changeover, the countermeasure is taken using a circuit. However, it is
necessary to prevent exceeding of the rated voltage (30 V) due to rise of VCC voltage at a time of changeover
(because the motor current returns instantaneously to the power supply). When this problem exists, increase the
capacity of a capacitor between VCC and GND.
• When the motor current exceeds the current limit value after changeover, the lower-side Tr is turned OFF. But, the
upper-side Tr enters the short-brake condition and the current determined from the motor counter electromotive
voltage and coil resistance flows. It is necessary to prevent this current from exceeding the rated current (3.1 A).
(F/R changeover at high speed is dangerous.)
10. Motor lock protection circuit
A motor lock protection circuit is incorporated for protection of IC and motor when the motor is locked.
When the LD output is “H” (unlocked) for a certain period in the start condition, the lower-side Tr is turned OFF. This
time is set with the capacity of the capacitor connected to the CSD pin. The time can be set to about 3.3 seconds with
the capacity of 10 µF (variance about ±30%).
Set time (s) ≈ 0.33 × C (µF)
When the capacitor used has a leak current, due consideration is necessary because it may cause error in the set time,
etc.
Cancelling requires either the stop condition or re-application of power supply (in the stop condition). When the lock
protection circuit is not to be used, connect the CSD pin to GND.
When the stop period during which lock protection is to be cancelled is short, the charge of capacitor cannot be
discharged completely and the lock protection activation time at restart becomes shorter than the set value. It is
necessary to provide the stop time with an allowance while referring to the following equation. (The same applies to
restart in the motor start transient condition.)
No. 7105-10/11
LB11822
Stop time (ms) ≥ 15 × C (µF)
11. Power supply stabilization
This IC has a large output current and is driven by switching, resulting in ready oscillation of the power line. It is
therefore necessary to connect a capacitor with a sufficient capacity between the VCC pin and GND for stabilization.
When a diode is inserted in the power line to prevent breakdown due to reverse connection of power supply, the power
line is particularly readily oscillated. The larger capacity need be selected.
12. Constant of integrating amplifier parts
Arrange the integrating amplifier external parts as near as possible to IC to protect them from noise effects. Arrange
them by keeping the largest possible distance from the motor.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of November, 2003. Specifications and information herein are
subject to change without notice.
PS No. 7105-11/11