Ordering number : EN4795C CMOS LSI LC321664AJ, AM, AT-80 1 MEG (65536 words × 16 bits) DRAM Fast Page Mode, Byte Write Overview Package Dimensions The LC321664AJ, AM, AT is a CMOS dynamic RAM operating on a single 5 V power source and having a 65536-word × 16-bit configuration. Equipped with large capacity capabilities, high-speed transfer rates and low power dissipation, this series is suited for a wide variety of applications ranging from computer main memory and expansion memory to commercial equipment. Address input utilizes a multiplexed address bus which permits it to be enclosed in compact plastic packages of SOJ 40-pin, SOP 40-pin and TSOP 44-pin. Refresh rates are within 4 ms with 256 row address (A0 to A7) selection and support RAS-only refresh, CAS-before-RAS refresh and hidden refresh settings. There are functions such as page mode, read-modifywrite, and byte-write. unit: mm 3200-SOJ40 [LC321664AJ] Features • • • • • • • • • 65536-word × 16-bit configuration Single 5 V ±10% power supply All input and output (I/O) TTL compatible Supports fast page mode, read-modify-write, and bytewrite. Supports output caching control using early write and Output Enable (OE) control. 4 ms refresh using 256 refresh cycles Supports RAS-only refresh, CAS-before-RAS refresh and hidden refresh. Packages SOJ 40-pin (400 mil) plastic package: LC321664AJ SOP 40-pin (525 mil) plastic package: LC321664AM TSOP 44-pin (400 mil) plastic package: LC321664AT RAS access time/column address access time/CAS access time/ cycle time/power dissipation SANYO:SOJ40 unit : mm 3195-SOP40 [LC321664AM] SANYO:SOP40 Parameter LC321664AJ, AM, AT-80 RAS access time 80 ns Column address access time 45 ns CAS access time 30 ns Cycle time 135 ns Power dissipation (max.) During operation During standby 633 mW 5.5 mW (CMOS level)/11 mW (TTL level) SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN 32896HA (OT)/O3194TH/81094TH (OT) No. 4795-1/30 LC321664AJ, AM, AT-80 Package Dimensions unit : mm 3207-TSOP44 [LC321664AT] SANYO:TSOP44 (TYPE-II) Pin Assignments No. 4795-2/30 LC321664AJ, AM, AT-80 Block Diagram Specifications Absolute Maximum Ratings Parameter Symbol Ratings Unit Note Maximum supply voltage VCC max –1.0 to +7.0 V 1 Input voltage VIN –1.0 to +7.0 V 1 Output voltage VOUT –1.0 to +7.0 V 1 mW 1 Allowable power dissipation LC321664AJ, AM 800 Pd max LC321664AT 700 Output short-circuit current IOUT 50 mA 1 Operating temperature range Topr 0 to +70 °C 1 Storage temperature range Tstg –55 to +150 °C 1 Note: 1) Stresses greater than the above listed maximum values may result in damage to the device. DC Recommended Operating Ranges at Ta = 0 to +70°C Parameter Symbol min typ max Unit Note Power supply voltage VCC 4.5 5.0 5.5 V 2 Input high level voltage VIH 2.4 6.5 V 2 Input low level voltage (A0 to A7, RAS, CAS, UW, LW, OE) VIL –1.0* +0.8 V 2 Input low level voltage (I/O1 to I/O16) VIL –0.5* +0.8 V 2 Note: 2) All voltages are referenced to VSS. A bypass capacitor of about 0.1 µF should be connected between VCC and VSS of the device. * –2.0 V when pulse width is less than 20 ns No. 4795-3/30 LC321664AJ, AM, AT-80 DC Electrical Characteristics at Ta = 0 to + 70°C, VCC = 5 V ± 10% Parameter Symbol Conditions min max Unit Note 115 mA 3, 4, 5 2 mA Operating current (Average current during operation) ICC1 RAS, CAS, address cycling: tRC = tRC min Standby current ICC2 RAS = CAS = VIH RAS-only refresh current ICC3 RAS cycling, CAS = VIH: tRC = tRC min 115 mA 3, 5 Fast page mode current ICC4 RAS = VIL, CAS address cycling: tPC = tPC min 70 mA 3, 4, 5 Standby current ICC5 RAS = CAS = VCC–0.2V 1 mA CAS-before-RAS refresh current ICC6 RAS, CAS cycling: tRC = tRC min 115 mA Input leakage current IIL 0V ≤ VIN ≤ 6.5V, pins other than measuring pin = 0V –10 +10 µA Output leakage current IOL DOUT disable, 0V ≤ VOUT ≤ 5.5V –10 +10 µA Output high level voltage VOH IOUT = –2.5mA 2.4 Output low level voltage VOL IOUT = 2.1mA 3 V 0.4 V Note: 3) All current values are measured at minimum cycle rate. Since current flows immoderately, if cycle time is longer than shown here value becomes smaller. Note: 4) ICC1 and ICC4 are dependent on output loads. Maximum values for ICC1 and ICC4 represent values with output open. Note: 5) One address change can be performed while RAS = VIL (ICC1 and ICC3). One address change can be performed during one tPC cycle (ICC4). No. 4795-4/30 LC321664AJ, AM, AT-80 AC Electrical Characteristics at Ta = 0 to +70°C, VCC = 5 V ± 10% (Note 6, 7, 8) Parameter Symbol min max Unit Note Random read or write cycle time tRC 135 ns Read-write/read-modify-write cycle time tRWC 180 ns Fast page mode cycle time tPC 55 ns Fast page mode Read-write/read-modifywrite cycle time tPRWC 100 ns RAS access time tRAC 80 ns 9, 14 15 CAS access time tCAC 30 ns 9, 14 Column address access time tAA 45 ns 9, 15 CAS precharge access time tCPA 50 ns 9 Output low-impedance time from CAS low tCLZ 0 ns 9 Output buffer turn-off delay time tOFF 0 20 ns 10 Rise or fall time tT 3 50 RAS precharge time tRP 45 RAS pulse width tRAS 80 10000 ns RAS pulse width for fast page mode only tRASP 80 100000 ns RAS hold time tRSH 30 ns CAS hold time tCSH 80 ns CAS pulse width tCAS 30 10000 ns RAS to CAS delay time tRCD 25 50 ns 14 35 ns 15 ns ns RAS to column address delay time tRAD 17 CAS to RAS precharge time tCRP 10 ns CAS precharge time tCP 10 ns Row address setup time tASR 0 ns Row address hold time tRAH 12 ns Column address setup time tASC 0 ns Column address hold time tCAH 20 ns Column address hold time referenced to RAS tAR 60 ns Column address to RAS lead time tRAL 45 ns Read command setup time tRCS 0 ns Read command hold time referenced to CAS tRCH 0 ns 11 Read command hold time referenced to RAS tRRH 0 ns 11 Write command hold time tWCH 15 ns Write command hold time referenced to RAS tWCR 60 ns Write command pulse width tWP 15 ns Continued on next page. No. 4795-5/30 LC321664AJ, AM, AT-80 Continued from preceding page. Parameter Symbol min max Unit Note Write command to RAS lead time tRWL 20 ns Write command to CAS lead time tCWL 20 ns Data input setup time tDS 0 ns 12 Data input hold time tDH 20 ns 12 Data input hold time referenced to RAS tDHR 60 ns Refresh period tREF Write command setup time tWCS 4 ms 0 ns 13 CAS to UW, LW delay time tCWD 50 ns 13 RAS to UW, LW delay time tRWD 100 ns 13 Column address to UW, LW delay time tAWD 65 ns 13 CAS precharge to UW, LW delay time (fast page mode cycle only) tCPWD 70 ns 13 CAS setup time for CAS-before-RAS refresh tCSR 10 ns CAS hold time for CAS-before-RAS refresh tCHR 15 ns RAS precharge time to CAS active time tRPC 10 ns CAS precharge time for CAS-before-RAS counter test tCPT 40 ns RAS hold time referenced to OE tROH 15 ns OE access time tOEA OE delay time tOED 15 OE to output buffer turn-off delay time tOEZ 0 OE command hold time tOEH 20 ns Data input to CAS delay time tDZC 0 ns 16 Data input to OE delay time tDZO 0 ns 16 Masked write setup time tMCS 0 ns Masked write hold time referenced to RAS tMRH 0 ns Masked write hold time referenced to CAS tMCH 0 ns 25 ns 9 ns 15 ns 10 Input/Output Capacitance at Ta = 25°C, f = 1 MHz, VCC = 5 V ± 10% Parameter Symbol min max Unit Input capacitance (A0 to A7, RAS, CAS, UW, LW, OE) CIN 7 pF I/O capacitance (I/O1 to I/O16) CI/O 7 pF No. 4795-6/30 LC321664AJ, AM, AT-80 Notes: 6) After the power is turned on, 200 µs are required after the arrival of VCC stabilized current before memory is initialized and begins operation. In addition, before memory operation initializes, approximately 8 cycles worth of RAS dummy cycles are required. When the on-chip refresh counter is applied, approximately 8-cycles worth of CAS-before-RAS dummy cycles are required instead of the RAS dummy cycles. 7) Measured at tT = 5 ns. 8) When measuring input signal timing, VIH (min) and VIL (max) are used for reference points. In addition, rise and fall time are defined between VIH and VIL. 9) Measured using an equivalent of 50 pF and one standard TTL load. 10) tOFF (max) and tOEZ (max) are defined as the time until output voltage can no longer be measured when output switches to a high impedance condition. 11) Operation is guaranteed if either tRRH or tRCH are satisfied. 12) These parameters are measured from the falling edge of CAS for an early-write cycle, and from the falling edge of UW and LW for a read-write/read-modify-write cycle. 13) tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters for memory in that they specify the operating mode. If tWCS ≥ tWCS (min), the cycle switches to an early-write cycle and output pins switch to high impedance throughout the cycle. If tCWD ≥ tCWD (min), tRWD ≥ tRWD (min), tAWD ≥ tAWD (min) and tCPWD ≥ tCPWD (min), the cycle switches to a read-write/read-modify-write cycle and data outputs equal information in the selected cells. If neither of the above conditions are satisfied, output pins are in an undefined state. 14) tRCD (max) does not indicate a restrictive operating parameter but instead represents the point at which the access time tRAC (max) is guaranteed. If tRCD ≥ tRCD (max), access time is determined according to tCAC. 15) tRAD (max) does not indicate a restrictive operating parameter but instead represents the point at which the access time tRAC (max) is guaranteed. If tRAD ≥ tRAD (max), access time is determined according to tAA. 16) Operation is guaranteed if either tDZC or tDZO are satisfied. No. 4795-7/30 LC321664AJ, AM, AT-80 Timing Chart Read Cycle No. 4795-8/30 LC321664AJ, AM, AT-80 Early Write Cycle No. 4795-9/30 LC321664AJ, AM, AT-80 Upper Byte Early Write Cycle No. 4795-10/30 LC321664AJ, AM, AT-80 Lower Byte Early Write Cycle No. 4795-11/30 LC321664AJ, AM, AT-80 Write Cycle (OE Control) No. 4795-12/30 LC321664AJ, AM, AT-80 Upper Byte Write Cycle (OE Control) No. 4795-13/30 LC321664AJ, AM, AT-80 Lower Byte Write Cycle (OE Control) No. 4795-14/30 LC321664AJ, AM, AT-80 Read-Modify-Write Cycle No. 4795-15/30 LC321664AJ, AM, AT-80 Read-Modify Upper Byte Write Cycle No. 4795-16/30 LC321664AJ, AM, AT-80 Read-Modify Lower Byte Write Cycle No. 4795-17/30 LC321664AJ, AM, AT-80 Fast Page Mode Read Cycle No. 4795-18/30 LC321664AJ, AM, AT-80 Fast Page Mode Early Write Cycle No. 4795-19/30 LC321664AJ, AM, AT-80 Fast Page Mode Upper Byte Early Write Cycle No. 4795-20/30 LC321664AJ, AM, AT-80 Fast Page Mode Lower Byte Early Write Cycle No. 4795-21/30 LC321664AJ, AM, AT-80 Fast Page Mode Read-Modify-Write Cycle No. 4795-22/30 LC321664AJ, AM, AT-80 Fast Page Mode Read-Modify Upper Byte Write Cycle No. 4795-23/30 LC321664AJ, AM, AT-80 Fast Page Mode Read-Modify Lower Byte Write Cycle No. 4795-24/30 LC321664AJ, AM, AT-80 Hidden Refresh Cycle No. 4795-25/30 LC321664AJ, AM, AT-80 RAS-Only Refresh Cycle CAS-Before-RAS Refresh Cycle No. 4795-26/30 LC321664AJ, AM, AT-80 CAS-Before-RAS Refresh Counter Test Cycle (read) No. 4795-27/30 LC321664AJ, AM, AT-80 CAS-Before-RAS Refresh Counter Test Cycle (write) No. 4795-28/30 LC321664AJ, AM, AT-80 CAS-Before-RAS Refresh Counter Test Cycle (read-modify-write) No. 4795-29/30 LC321664AJ, AM, AT-80 ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of March 1996. Specifications and information herein are subject to change without notice. PS No. 4795-30/30