Ordering number : EN5944 CMOS IC LC5824, LC5823, LC5822 4-Bit Single-Chip Microcontrollers Featuring 4 KB to 8 KB of ROM, 1 Kbit of RAM, and an LCD Driver for Medium Speed Small-Scale Control Applications Overview Features The LC5822, LC5823, and LC5824 are CMOS microcontrollers that feature the low-voltage operation required for battery-power applications and that provide 4 KB, 6 KB, or 8 KB of ROM, 1 kilobit of RAM, and an LCD driver. • These microcontrollers are high-end versions of the LC5800 and provide the following features. These microcontrollers support an instruction set based on that of the earlier LC5800, LC5812, and LC5814 for excellent efficiency in software development. Applications • LCD display in multi-function watches, timers, and other products • Control and LCD display in timers • Control and LCD display in miniature test equipment, health maintenance equipment, and other products • These microcontrollers are optimal for products that include an LCD display, especially battery powered products. Wide Allowable Operating Ranges Power options supply Cycle times Supply voltage range EXT-V 10 µs VDD = 2.3 to 3.6 V When an 800-kHz ceramic oscillator is used EXT-V 20 µs VDD = 2.3 to 3.6 V When an 400-kHz ceramic oscillator is used EXT-V 61 µs VDD = 2.3 to 3.6 V When an 65-kHz crystal oscillator is used EXT-V 122 µs VDD = 2.0 to 3.6 V When an 32-kHz crystal oscillator is used Li 122 µs VDD = 2.6 to 3.6 V* When an 32-kHz crystal oscillator is used Ag 122 µs VDD = 1.3 to 1.65 V When an 32-kHz crystal oscillator is used Notes Low Current Drain * In halt mode (typical) • Ceramic oscillator 400 kHz (3.0 V) 200 µA • Crystal oscillator 32 kHz (1.5 V, Ag specifications) 3.0 µA (LCD biases other than 1/3) 4.5 µA (LCD drive: 1/3 bias) • Crystal oscillator 32 kHz (3.0 V, Li specifications) 2.0 µA (LCD biases other than 1/3) 6.0 µA (LCD drive: 1/3 bias) Timer and Counter Functions • One 8-bit programmable timer (May be used as an event counter) • One 8-bit programmable reload timer • Time base timer (for clocks) • Watchdog timer • 8-bit serial I/O (3-pin synchronous system) Standby Functions • Clock standby function (halt mode) Only the oscillator circuits, the divider circuit, and the LCD driver operate. All other internal operations are stopped. This provides a power-saving function in which current drain is minimized, and allows a clock function to be implemented easily with low power dissipation. Furthermore, low-speed and high-speed modes can be implemented by setting the operating modes of the two oscillator circuits. • Full standby function (hold mode) • Halt mode can be cleared by any of two external and two internal interrupts. Note*: When the backup flag is set, the BAK pin is connected to VDD. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 82198RM (OT) No. 5944-1/24 LC5824, LC5823, LC5822 Improved I/O Functions • External interrupt pins • Input pins that can clear halt mode: 10 pins (maximum) • Input ports with input resistors that can be controlled from software: 8 pins (maximum) • Pins with a function that prevents the input port floating state: 8 pins (maximum) • LCD drive pins: 4 pins (common), 42 pins (segment outputs) • General-purpose I/O ports: 16 pins (when all 4 P port pins are used) • General-purpose inputs: 8 pins • General-purpose outputs (1): 1 pin (the ALM pin) • General-purpose outputs (2): 42 pins (when all 42 of the LCD segment outputs are switched over to function as general-purpose outputs) • 8-bit serial output port: 1 set (3 pins: output, input, and clock) Functional Overview • Program ROM: 4096 × 16 bits LC5824 3072 × 16 bits LC5823 2048 × 16 bits LC5822 • Internal RAM: 256 × 4 bits • All instructions execute in a single cycle. • Extensive set of interrupt functions for clearing halt and hold mode — 8 halt mode clearing functions — 5 hold mode clearing functions — 6 interrupt functions — Subroutines can be nested up to 8 levels (Specialpurpose registers that are shared with the interrupt function are built in.) • Powerful hardware to increase system processing capacity — Segment port related hardware Built-in segment PLA circuit Built-in segment decoder Support for six different LCD drive specifications Outputs can be switched to CMOS levels — Built-in 8-bit synchronous serial I/O circuit — 8-bit read/write timer (plus a separate 8-bit prescaler; can be used as and event counter) — 8-bit reload timer (plus built-in 8-bit prescaler) — Built-in 8-bit prescaler (for use with timer 1, timer 2, and the serial counter) — All of RAM can be used a working area (RAM bank system) — Dedicated data pointer register for RAM access — 15-stage divider circuit for clocks (also used as the LCD voltage alternation frequency generator) — 8-bit table reference function (reads 8-bit ROM data) — Chattering prevention circuit (on two ports) — Alarm signal generation circuit • LCD panel drive output pins with high flexibility (42 pins) Drive system bias · duty bias · duty bias · duty bias · duty bias · duty Static drive Number of driven segments Required number of common pins 168 segments 4 pins 126 segments 3 pins 168 segments 4 pins 126 segments 3 pins 84 segments 2 pins 42 segments 1 pin — The LCD output pins can be switched to function as general-purpose outputs. CMOS/p-channel/n-channel type combinations: Up to 42 pins — An alternation frequency appropriate for the LCD panel used can be selected. • An oscillator appropriate for your system’s specifications can be selected. — A 32- or 65-kHz crystal oscillator can be selected (Used when a clock function is required or for low current drain operation.) — A ceramic oscillator with a frequency from 400 kHz to 2 MHz can be selected (when high-speed operation is required.) Available delivery formats: QIP-80 and chip Package Dimensions unit: mm 3174-QFP80E [LC5824, 5823, 5822] SANYO: QIP80E No. 5944-2/24 LC5824, LC5823, LC5822 Pin Assignment Top view No. 5944-3/24 LC5824, LC5823, LC5822 Pad Arrangement Chip size: 4.92 mm × 5.15 mm Pad size: 120 µm × 120 µm Chip thickness 480 µm (chip specifications) Pad Coordinates 60 Seg 22 Coordinates X µm Y µm –2030 –2178 5 VDD3 Coordinates X µm Y µm 2257 –1212 33 Seg 11 61 Seg 23 –1850 –2178 6 VDD2/BAK 2257 –1032 34 Seg 12 –374 2178 62 Seg 24 –1670 –2178 7 VDD1 2257 –852 35 Seg 13 –546 2178 63 Seg 25 –1490 –2178 8 ALM 2257 –601 36 Seg 14 –726 2178 64 Seg 26 –1310 –2178 9 SO1 2257 –419 37 Seg 15 –906 2178 65 Seg 27 –1130 –2178 10 SO2 I/O port 2257 –236 38 Seg 16 –1086 2178 66 Seg 28 –950 –2178 11 SO3 I/O port 2257 56 39 Seg 17 –1266 2178 67 Seg 29 –770 –2178 12 SO4 I/O port 2257 132 40 Seg 18 –1446 2178 68 Seg 30 –590 –2178 13 M1 2257 364 41 Seg 19 –1626 2178 69 Seg 31 –410 –2178 14 M2 I/O port 2257 544 42 Seg 20 –1806 2178 70 Seg 32 –230 –2178 15 M3 I/O port 2257 724 43 Seg 21 –1986 2178 71 Seg 33 –50 –2178 16 M4 I/O port 2257 904 44 COM1 –2270 1871 72 Seg 34 122 –2178 17 RES I/O port 2257 1636 45 COM2 –2270 1628 73 Seg 35 302 –2178 18 Test 2330 1998 46 S1 –2270 1367 74 Seg 36 482 –2178 19 Test 2330 2178 47 S2 Input port –2270 1140 75 Seg 37 662 –2178 20 TST 2150 2178 48 S3 Input port –2270 960 76 Seg 38 842 –2178 21 CUP1 1970 2178 49 S4 Input port –2270 734 328 PAD No. Pin PAD No. Pin PAD No. Pin Coordinates X µm Y µm –194 2178 77 Seg 39 1022 –2178 22 CUP2 1790 2178 50 K1 –2270 78 Seg 40 1202 –2178 23 Seg 1 1606 2178 51 K2 Input port –2270 88 79 Seg 41 1382 –2178 24 Seg 2 1426 2178 52 K3 Input port –2270 –140 80 Seg 42 1562 –2178 25 Seg 3 1246 2178 53 K4 Input port –2270 –380 81 XC 1774 –2178 26 Seg 4 1066 2178 54 A1 –2270 –593 82 XTOUT 1954 –2178 27 Seg 5 886 2178 55 A2 I/O ports –2270 –773 83 XTIN 2134 –2178 28 Seg 6 706 2178 56 A3 I/O ports –2270 –953 1 VDD 2257 –1959 29 Seg 7 526 2178 57 A4 I/O ports –2270 –1133 2 VSS 2257 –1779 30 Seg 8 346 2178 58 COM3/P3 –2270 –1602 3 CFIN/P1 2257 –1599 31 Seg 9 166 2178 59 COM4/P4 –2270 –1846 4 CFOUT/P2 2257 –1402 32 Seg 10 –14 2178 Note: • • • • • The pin numbers are the QIP-80E mass-production package pin numbers. The test pin (TST) must be connected to VSS. Pads number 42 and 43 in the chip version must be left open. Do not use solder dip techniques to mount the QIP-80E package version. In the chip version, the substrate must be either connected to VSS or left open. No. 5944-4/24 LC5824, LC5823, LC5822 System Block Diagram Data I/O - D bus OPG (2 bits) Address B register (4 bits) Program counter (13 bits) Table reference Interrupt control Accumulator (AC) (4 bits) Alarm tone Buffer generator Watchdog timer Timer 1 Reset circuit Crystal oscillator circuit (32 kHz/65 kHz) Clock timer (15 bits) Serial I/O Timer 2 Segment decoder strobe decoder Chronograph circuit Carrier control circuit CF/RC oscillator circuit (400 kHz to 4 MHz) Chronograph control circuit Voltage step- LCD driver RAM: Data memory ROM: Program memory DP: Data pointer register BNK: Bank register APG: RAM page flag AC: Accumulator ALU: Arithmetic and logic unit B: B register OPG: ROM page flag Switching circuit System clock generator PC: Program counter IR: Instruction register STS1: Status register 1 STS2: Status register 2 STS3: Status register 3 STS4: Status register 4 PLA: Programmed logic array used for segment data and strobe functions WAIT.C: Wait time counter No. 5944-5/24 LC5824, LC5823, LC5822 Pin Functions Pin No. Pin I/O 24 25 VDD VSS — — Function Options Status at reset Power supply LCD drive power supply 30 VDD1 — 29 VDD2/BAK — 28 VDD3 — 42 43 CUP1 CUP2 — — Power supply specifications Pin • Ag specifications • Li specifications • EXT-V specifications Connections of the LCD power supply step-up (step-down) capacitors CFIN CFOUT System clock oscillator connections • Ceramic element connections (CF specifications) Input • RC component connections (RC specifications) Output *: This oscillator circuit is stopped when a STOP or SLOW instruction is executed. • CF specifications • RC specifications • Unused 23 22 XTIN XTOUT Used for reference counting (clock specifications, LCD alternation frequency) and as the system clock. Input • 32-kHz crystal oscillator Output • 65-kHz crystal oscillator *: This oscillator circuit is stopped when a STOP instruction is executed. • 32-kHz specifications • 65-kHz specifications • 38-kHz specifications • Unused — XC 67 68 69 70 S1 S2 S3 S4 71 72 73 74 K1 K2 K3 K4 26 27 36 37 38 39 M1 M2 M3 M4 26 27 79 80 P1 P2 P3 P4 76 77 78 79 A1 A2 A3 A4 — Used for the phase compensation capacitor connected between this pin and XTOUT and XTIN. This pin is only used in the chip product. Input Input-only port • Input pins used to acquire input data to RAM • 1.95-ms and 7.8-ms chattering exclusion circuits included. • Pull-down resistors are built in. Note: the 1.95 ms and 7.8 ms values are for a ø0 of 32.768 kHz. • Pull-down resistors • Presence or absence of enabled low-level hold Note: After a reset is transistors cleared, these pins go to the floating state. Input Input-only port • Input pins used to acquire input data to RAM • 1.95-ms and 7.8-ms chattering exclusion circuits included. • Pull-down resistors are built in. Note: the 1.95 ms and 7.8 ms values are for a ø0 of 32.768 kHz. • Pull-down resistors • Presence or absence of enabled low-level hold Note: After a reset is transistors cleared, these pins go to the floating state. I/O I/O port • Input pins used to acquire input data to RAM. • Presence or absence of • Output pins used to output RAM data. low-level hold • M4 is also used as the TM1 external clock input in TM1 mode 3. transistors • M3 is also used for HEF8 halt mode clear control. • Output type: CMOS or *: The minimum period for clock signal inputs is twice the cycle p-channel time • Pull-down resistors are built in. • Pull-down resistors enabled Note: After a reset is cleared, these pins go to the floating state. • Input mode • The output latch data is set to 1. I/O I/O port • Input pins used to acquire input data to RAM. • Output pins used to output RAM data. • Pull-down resistors are built in. The same as those for M1 to M4. However, only for valid ports. The same as those for M1 to M4. However, only for valid ports. I/O I/O port • Input pins used to acquire input data to RAM. • Output pins used to output RAM data. • Pull-down resistors are built in. • A1 is also used as the external interrupt request control input signal (INT). The same as those for M1 to M4. The same as those for M1 to M4. Continued on next page. No. 5944-6/24 LC5824, LC5823, LC5822 Continued from preceding page. Pin No. Pin 32 33 34 35 SO1 SO2 SO3 SO4 31 ALM 40 RES 44 Seg 22 64 Seg 21 1 Seg 22 21 Seg 42 I/O I/O Function I/O port • Input pins used to acquire input data to RAM. • Output pins used to output RAM data. • Pull-down resistors are built in. SO1 to SO3 are also used as the serial interface pins. • The serial interface function can be selected under program control. • Pin functions: SO1: Serial input SO2: Serial output SO3: Serial clock The serial clock can be taken from either internal or external sources, and can be set up to detect either rising or falling edges under program control. Options Status at reset Identical to M1 through M4 Identical to M1 through M4 Output-only pin Output • A signal modulated by ø0, ø3, or ø4 can be output under program control. Input IC internal reset input • The program counter is set to point to location 00H. • The reset input level can be set to be either high or low. • Either a pull-up or a pull-down resistor is built in. Note: Applications must apply the reset signal level for at least 500 µs to effect a reset. Low-level output • Selection of a pull-up or pull-down resistor • Selection of active-low or active-high reset logic LCD panel drive outputs/general-purpose outputs • LCD panel drive (1) Static (2) 1/2 bias 1/2 duty (3) 1/2 bias 1/3 duty (4) 1/2 bias 1/4 duty (5) 1/3 bias 1/3 duty (6) 1/3 bias 1/4 duty One of items (1) through (5) is selected as a mask option. • When used for LCD drive: • Switching between LCD —All lit drive output and —All off general-purpose output * Determined by the • Switching between the master options LCD drive type options • When used as general—Static purpose outputs: —1/2 bias 1/2 duty —High level —1/2 bias 1/3 duty —Low level • General-purpose output ports —1/2 bias 1/4 duty * Determined by the Output (1) CMOS output —1/3 bias 1/3 duty master options (2) p-channel open-drain output —1/3 bias 1/4 duty Note: When a (3) n-channel open-drain output • General-purpose output combination of LCD drive One of items (1) through (3) is selected as a mask option. type switching and general-purpose —CMOS outputs is selected, these • The adoption of the segment PLA in these microcontrollers —p-channel open-drain pins will be either: means that there is no need for programs to control the —n-channel open-drain All lit/high-level output, or LCD/general-purpose output states of these pins. • Standby mode output All off/low-level output. • Output latch control is supported in the oscillator stopped latch control • During the reset period, standby states and during a reset. the LCD drive functions • Any combination of LCD and general-purpose output functions as static drive. may be used. Common drive outputs for the LCD panel The table below lists which pins are used in each of the drive types. However, note that the listed alternation frequencies are the typical specifications when ø0 is 32.768 kHz. 65 66 79 80 COM1 COM2 COM3 COM4 COM1 Output Static 1/2 duty 1/3 duty 1/4/duty ● ● ● ● ● COM2 ✕ ● ● COM3 ✕ ✕ ● ● COM4 ✕ ✕ ✕ ● 32 Hz 32 Hz 42.7 Hz 64 Hz Alternation frequency * In products with the CF specifications, the alternation frequency signal stops briefly. Note: Note that the “✕” symbol indicates that the corresponding common pin cannot be used in that drive type. 41 TST Input — — TEST TEST — — Test input • In the QIP-80 version, this pin must be connected to VSS. • In the chip version, this pin must be left open or connected to VSS. Test pins. (These are not used in the device user interface.) No. 5944-7/24 LC5824, LC5823, LC5822 Sample Application Circuit LCD : 1/2 bias — 1/4 duty No. 5944-8/24 LC5824, LC5823, LC5822 Oscillator Circuit Options Circuit type Notes Timing generator Option • The cycle time is 4 times the f1 period. • The divider circuit outputs (ø1 through ø15) are used as the clock time base, the LCD drive waveform generation clock, and for S/K port chattering prevention. RC & Xtal • OSC1 is stopped by the execution of a SLOW instruction. Timing generator Divider • The cycle time is 4 times n times the f1 period. (n:1) • The divider circuit outputs (ø1 through ø15) are used as the clock time base, the LCD drive waveform generation clock, and for S/K port chattering prevention. CF & Xtal • 400 kHz (CF) • 4 MHz (CF) • OSC1 is stopped by the execution of a SLOW instruction. Timing generator Divider • The cycle time is 4 times the f1 period. • The divider circuit outputs (ø1 through ø15) are used as the clock time base, the LCD drive waveform generation clock, and for S/K port chattering prevention. RC Divider Continued on next page. No. 5944-9/24 LC5824, LC5823, LC5822 Continued from preceding page. Circuit type Notes Timing generator Option • The cycle time is 4 times n times the f1 period. (n:1) CF • The divider circuit outputs (ø1 through ø15) are used as the clock time base, the LCD drive frequency generation clock, and for S/K port chattering prevention. • 400 kHz • 4 MHz Timing generator Divider Xtal • 32 kHz • The cycle time is 4 times the f2 period. • The divider circuit outputs (ø1 through ø15) are used as the clock time base, the LCD drive waveform generation clock, and for S/K port chattering prevention. • 55 kHz Divider Note that the CFIN and CFOUT pins are switched over to function as the P1 and P2 pins. No. 5944-10/24 LC5824, LC5823, LC5822 Crystal Oscillator Circuit Options Option Circuit type Notes The resistor RD is built into the IC when this circuit is used at 32 kHz. Used at 32 kHz • The cycle time is 4 times n times the f1 period. (n:2) • The divider circuit outputs (ø1 through ø15) are used as the clock time base, the LCD drive frequency generation clock, and for S/K port chattering prevention. Used at 38 kHz Used at 65 kHz • OSC1 is stopped by the execution of a SLOW instruction. Input Port Options Option Circuit type Notes Bus • When the input open specifications are selected, before reading the input, the pulldown transistor is turned on. Then the input state is read and the pull-down transistor is turned off. If the input was in the floating state, the low level hold transistor operates to hold the level. Low level hold transistor Low level hold transistor selection SF2/RF2, D2 to D7 Pull-down resistor When use of the hold transistor is selected, it is used to minimize the current drain that flows in the pull-down resistor when a pushbutton switch is used with S1 or a slide switch is used with S2. Output mode If use of the hold transistor is not selected: • The circuit is used with the pull-down transistor turned on. • Select unused if the external control signal line connected to this input will never be in the floating state. RES Pin Option Circuit type Notes Pull-up resistor Internal resistor and polarity selections Pull-up resistor, pull-down resistor, resistors left open, and level selections • Reset on low, pull-up resistor included • Reset on high, pull-down resistor included • Reset on low, no resistors connected • Reset on high, no resistors connected Pull-down resistor No. 5944-11/24 LC5824, LC5823, LC5822 Mask Option List Voltage specifications • Ag specifications • Li specifications • EXT-V specifications LCD driver • Static • 1/2 bias — 1/2 duty • 1/2 bias — 1/3 duty • 1/2 bias — 1/4 duty • 1/3 bias — 1/3 duty • 1/3 bias — 1/4 duty • Unused Segment port states during a reset LCD driver pins • All lit • All off CMOS p/n-channel pins • High level • Low level Oscillator specifications • CF only (ceramic oscillator element) • RC only (using a resistor and a capacitor) • Crystal only • CF + crystal • RC + crystal CF • 400 kHz • 800 kHz • 1 MHz • 2 MHz • 4 MHz RC • 400 kHz • 800 kHz • 1 MHz Crystal • 32 kHz • 65 kHz • 38 kHz LCD alternation frequency • SLOW • TYP • FAST External reset circuit • RES pin • RES pin + S1 to S4 pressed at the same time Internal reset circuit (power on reset) • Selected • Disabled RES pin • Reset on low, pull-up resistor included • Reset on high, pull-down resistor included • Reset on low, no resistors connected • Reset on high, no resistors connected Alarm output initial level • Low level • High level Chronometer and strobe selection • 00H • 10H • 00H & 10H • Unused Port S low level hold transistors • Low level hold transistors present • Low level hold transistors disabled Port K low level hold transistors • Low level hold transistors present • Low level hold transistors disabled Port M low level hold transistors • Low level hold transistors present • Low level hold transistors disabled Port P low level hold transistors • Low level hold transistors present • Low level hold transistors disabled Port SO low level hold transistors • Low level hold transistors present • Low level hold transistors disabled Port A low level hold transistors • Low level hold transistors present • Low level hold transistors disabled M1 to M4 outputs • CMOS • p-channel • n-channel P1 to P4 outputs • CMOS • p-channel • n-channel A1 to A4 outputs • CMOS • p-channel • n-channel No. 5944-12/24 LC5824, LC5823, LC5822 These electrical characteristics are provisional and the values are subject to change. Ag Specifications Absolute Maximum Ratings at Ta = 25°C ±2°C, VSS = 0 V Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Symbol Conditions and applicable pins Ratings min typ Unit max VDD –0.3 +4.0 V VDD1 –0.3 +4.0 V VDD2 –0.3 +5.5 V VDD3 For 1/3-bias LCD drive techniques –0.3 +4.0 V VDD3 For LCD drive techniques other than 1/3 bias –0.3 +4.0 V –0.3 VDD + 0.3 V VIN1 VOUT1 VOUT2 S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4, RES,TST M1 to M4, A1 to A4, SO1 to SO4, ALM, CUP2 (With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) SEGOUT, COM1 to COM4, CUP1 –0.3 +0.3 V –0.3 VDD3 + 0.3 V Operating temperature Topg –20 +65 °C Storage temperature Tstg –30 +125 °C Allowable Operating Ranges at Ta = 25°C ±2°C, VSS = 0 V Parameter Symbol VDD VDD1 Supply voltage Conditions and applicable pins VDD3 Unit max 1.3 2.4 3.3 V For 1/3-bias LCD drive techniques 3.7 4.95 V For LCD drive techniques other than 1/3 bias High-level input voltage VIH S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) RES Low-level input voltage VIL S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) RES fopg typ VBAK = VDD1 VDD2 VDD3 Operating frequency Ratings min 1.65 V 2.4 3.3 VDD – 0.2 VDD V 0 0.2 V 32 33 kHz Ta = –20 to +65°C Electrical Characteristics at Ta = 25°C ±2°C, VSS = 0 V, VDD = VDD1 Parameter Symbol Conditions and applicable pins Ratings min typ Unit max RIN1A VDD = 1.5 V, Low level hold transistor VIN = 0.35 VDD *1 Figure 1 50 500 kΩ RIN1B VDD = 1.5 V, Programmable pull-down resistor VIN = 0.7 VDD *1 Figure 1 50 1000 kΩ RIN2A VDD = 1.5 V, Low level hold transistor VIN = 0.35 VDD, Input mode *2, Figure 1 50 500 kΩ RIN2B VDD = 1.5 V, Programmable pull-down resistor VIN = 0.7 VDD, Input mode *2, Figure 1 50 1000 kΩ RIN3 VDD = 1.5 V, The RES pin pull-up/pull-down resistor VIN = 0.7 VDD/0.3 VDD 10 300 kΩ High-level output voltage VOH1 VDD = 1.3 V, IOH = –250 µA, ALM Low-level output voltage VOL1 VDD = 1.3 V, IOL = 250 µA, ALM High-level output voltage VOH2 VDD = 1.5 V, M1 to 4, A1 to 4, SO1 to 4 IOH = –20 µA, (With M1 to M4, A1 to A4, and SO1 to SO4 in output mode) Low-level output voltage VOL2 VDD = 1.5 V, M1 to 4, A1 to 4, SO1 to 4 IOL = 20 µA, (With M1 to M4, A1 to A4, and SO1 to SO4 in output mode) Input resistance VDD – 0.65 V 0.65 VDD – 0.2 V V 0.2 V Continued on next page. No. 5944-13/24 LC5824, LC5823, LC5822 Continued from preceding page. Parameter Symbol Conditions and applicable pins Ratings min typ Unit max Segment driver output impedance [When Set Up as CMOS Output Ports] High-level output voltage VOH3 VDD = 1.5 V, IOH = –3 µA, Segment 1 to 42 Low-level output voltage VOL3 VDD = 1.5 V, IOL = 3 µA, Segment 1 to 42 VDD – 1.0 V 1.0 V [When Set Up as P-Channel Open-Drain Output Ports] High-level output voltage VOH3 VDD = 1.5 V, IOH = –3 µA, Segment 1 to 42 Output off leakage current IOFF VDD = 1.5 V, VOL = VSS, Segment 1 to 42 0.3 1.0 V 1.0 µA [Static Drive] High-level output voltage VOH3 VDD = 1.5 V, IOH = –0.4 µA, SEGOUT Low-level output voltage VOL3 VDD = 1.5 V, IOL = 0.4 µA, SEGOUT High-level output voltage VOH4 VDD = 1.5 V, IOH = –4 µA, COM1 Low-level output voltage VOL4 VDD = 1.5 V, IOL = 4 µA, COM1 VDD2 – 0.2 V 0.2 VDD2 – 0.2 V V 0.2 V [Duplex Drive (1/2 bias - 1/2 duty)] High-level output voltage VOH3 VDD = 1.5 V, IOH = –0.4 µA, SEGOUT Low-level output voltage VOL3 VDD = 1.5 V, IOL = 0.4 µA, SEGOUT High-level output voltage VOH4 VDD = 1.5 V, IOH = –4 µA, COM1 to COM2 VDD2 – 0.2 VDD1 – 0.2 Middle-level output voltage VOM VDD = 1.5 V, IOH = –4 µA, IOL = 4 µA, COM1 to COM2 Low-level output voltage VOL4 VDD = 1.5 V, IOL = 4 µA, COM1 to COM2 VDD2 – 0.2 V 0.2 V V VDD1 + 0.2 V 0.2 V [1/2 Bias - 1/3 Duty and 1/2 Bias - 1/4 Duty Drive] High-level output voltage VOH3 VDD = 1.5 V, IOH = –0.4 µA, SEGOUT Low-level output voltage VOL3 VDD = 1.5 V, IOL = 0.4 µA, SEGOUT VOH4 VDD = 1.5 V, IOH = –4 µA, COM1 to COM3 (1/3 duty) COM1 to COM4 (1/4 duty) VDD2 – 0.2 VDD1 – 0.2 High-level output voltage Middle-level output voltage VOM VDD = 1.5 V, IOH = –4 µA, IOL = 4 µA, COM1 to COM3 (1/3 duty), COM1 to COM4 (1/4 duty) Low-level output voltage VOL4 VDD = 1.5 V, IOL = 4 µA, COM1 to 2 COM1 to COM3 (1/3 duty), COM1 to COM4 (1/4 duty) VDD2 – 0.2 V 0.2 V V VDD1 + 0.2 V 0.2 V [1/3 Bias - 1/3 Duty and 1/3 Bias - 1/4 Duty Drive] High-level output voltage VOH3 VDD = 1.5 V, IOH = –0.4 µA, SEGOUT VDD3 – 0.2 M1-level output voltage VOM1–3 VDD = 1.5 V, IOH = –0.4 µA, IOL = 0.4 µA, SEGOUT VDD2 – 0.2 VDD2 + 0.2 V M2-level output voltage VOM2–3 VDD = 1.5 V, IOH = –0.4 µA, IOL = 0.4 µA, SEGOUT VDD1 – 0.2 VDD1 + 0.2 V Low-level output voltage VOL3 VDD = 1.5 V, IOL = 0.4 µA, SEGOUT 0.2 V VOH4 VDD = 1.5 V, IOH = –4 µA, COM1 to COM3 (1/3 duty) COM1 to COM4 (1/4 duty) VDD3 – 0.2 M1-level output voltage VOM1–4 VDD = 1.5 V, IOH = –4 µA, IOL = 4 µA, COM1 to COM3 (1/3 duty), COM1 to COM4 (1/4 duty) VDD2 – 0.2 VDD2 + 0.2 V M2-level output voltage VOM2–4 VDD = 1.5 V, IOH = –4 µA, IOL = 4 µA, COM1 to COM3 (1/3 duty), COM1 to COM4 (1/4 duty) VDD1 – 0.2 VDD1 + 0.2 V Low-level output voltage VOL4 0.2 V High-level output voltage VDD = 1.5 V, IOL = 4 µA, COM1 to COM3 (1/3 duty), COM1 to COM4 (1/4 duty) V V Continued on next page. No. 5944-14/24 LC5824, LC5823, LC5822 Continued from preceding page. Parameter Symbol Conditions and applicable pins Ratings min typ Unit max [Output Voltage] LCD drive method: 1/3 bias (doubler) VDD2 VDD = 1.35 V, fopg = 32.768 kHz, C1 to C3 = 0.1 µF Figure 2 2.5 V (tripler) VDD3 VDD = 1.35 V, fopg = 32.768 kHz, C1 to C3 = 0.1 µF Figure 2 3.75 V VDD2 VDD = 1.35 V, fopg = 32.768 kHz, C1 to C2 = 0.1 µF Figure 3 2.5 V LCD drive method: 1/2 bias (doubler) [Current Drain (with the backup flag cleared)] LCD drive method: 1/3 bias | IDD | VDD = 1.5 V, In halt mode, C1 to C3 = 0.1 µF, CI = 25 kΩ, Figure 2, Co = Cg = 20 pF, 32.768 kHz Xtal 3.5 µA LCD drive methods other than 1/3 bias | IDD | VDD = 1.5 V, In halt mode, C1 = C2 = 0.1 µF, CI = 25 kΩ, Figure 3, Co = Cg = 20 pF, 32.768 kHz Xtal 2.0 µA Oscillator start voltage | Vstt | Co = Cg = 20 pF, CI = 25 kΩ, Figure 3, 32.768 kHz Xtal Oscillator hold voltage | VHOLD | Oscillator start time Oscillator correction capacitance VBAK = VDD1, CI = 25 kΩ, Figures 2 and 3 Co = Cg = 20 pF, 32.768 kHz Xtal Tstt VDD = 1.35 V, CI = 25 kΩ, Figure 4, Co = Cg = 20 pF, 32.768 kHz Xtal 10P XC 20P XTOUT 1.3 1.35 V 1.65 V 10 sec 8 10 12 pF 16 20 24 pF No. 5944-15/24 LC5824, LC5823, LC5822 Li Specifications Absolute Maximum Ratings at Ta = 25°C ±2°C, VSS = 0 V Parameter Symbol Conditions and applicable pins VDD VDD1 Maximum supply voltage Maximum input voltage Maximum output voltage (LCD drive method: 1/3 bias) (LCD drive methods other than 1/3 bias) VBAK = VDD1 or VDD2 VDD2 Ratings min typ Unit max –0.3 +4.0 –0.3 +4.0 V V –0.3 +4.0 V VDD3 (LCD drive method: 1/3 bias) –0.3 +5.5 V VDD3 (LCD drive methods other than 1/3 bias) –0.3 +4.0 V VIN1 S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) RES, TST –0.3 VDD + 0.3 V M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in output mode) ALM, CUP2 –0.3 VDD + 0.3 V VOUT2 SEGOUT, COM1 to COM4, CUP1 –0.3 VDD3 + 0.3 V VOUT2 M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in output mode) ALM, SEGOUT, COM1 to COM4, CUP1, CUP2 –0.3 VDD + 0.3 V VOUT1 Operating temperature Topg –20 +65 °C Storage temperature Tstg –30 +125 °C Allowable Operating Ranges at Ta = 25°C ±2°C, VSS = 0 V Parameter Supply voltage Symbol Conditions and applicable pins VDD VBAK = VDD /2 VDD2 (With the backup flag cleared) VDD VDD2 Ratings min typ 2.0 3.6 V VBAK = VDD (With the backup flag uncleared) 1.3 3.6 V VDD3 (LCD drive method: 1/3-bias) 3.9 5.0 V VDD3 (LCD drive methods other than 1/3 bias) VDD3 = VDD2 High-level input voltage VIH S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) VDD – 0.4 RES Low-level input voltage VIL S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) RES Operating frequency Unit max fopg Ta = –20 to +65°C V VDD V 0 0.4 V 32 33 kHz Electrical Characteristics at Ta = 25°C ±2°C, VSS = 0 V, VDD = VDD2 Parameter Input resistance Symbol Conditions and applicable pins Ratings min typ max Unit RIN1A VDD = 3.0 V, VIN = 0.35 VDD Low level hold transistor *1, Figure 5 50 500 kΩ RIN1B VDD = 3.0 V, VIN = 0.7VDD Programmable pull-down resistor *1, Figure 5 50 1000 kΩ RIN2A VDD = 3.0 V, input mode, Low level hold transistor *1, VIN = 0.35 VDD, Figure 5 50 500 kΩ RIN2B VDD = 3.0 V, Programmable pull-down resistor, *2, VIN = 0.7 VDD, input mode, Figure 5 50 1000 kΩ 10 300 kΩ RIN3 VDD = 3.0 V, RES pin pull-up/pull-down resistor VIN = 0.7 VDD/0.3 VDD No. 5944-16/24 LC5824, LC5823, LC5822 Electrical Characteristics at Ta = 25°C ±2°C, VSS = 0 V, VDD = VDD2 Parameter Symbol Conditions and applicable pins High-level output voltage VOH1 VDD = 2.5 V, IOH = –250 µA, ALM Low-level output voltage VOL1 VDD = 2.5 V, IOL = 250 µA, ALM High-level output voltage VOH2 VDD = 3.0 V, IOH = –40 µA, M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in output mode) Low-level output voltage VOL2 VDD = 3.0 V, IOL = 40 µA, M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in output mode) High-level output voltage VOH3 VDD = 3.0 V, IOH = –5 µA, Segment 1 to 42 Low-level output voltage VOL3 VDD = 3.0 V, IOL = 5 µA, Segment 1 to 42 Ratings min typ Unit max VDD – 0.65 V 0.65 VDD – 0.4 V V 0.4 V 1 V Segment driver output impedance [When Set Up as CMOS Output Ports] VDD – 1 V [When Set Up as P-Channel Open-Drain Output Ports] High-level output voltage VOH3 VDD = 2.5 V, IOH = –10 µA, Segment 1 to 42 Output off leakage current IOFF VDD = 3.0 V, VOL = VSS 0.3 1 V 1 µA [Static Drive] High-level output voltage VOH3 VDD = 3.0 V, IOH = –0.4 µA, SEGOUT Low-level output voltage VOL3 VDD = 3.0 V, IOL = 0.4 µA, SEGOUT High-level output voltage VOH4 VDD = 3.0 V, IOH = –4 µA, COM1 Low-level output voltage VOL4 VDD = 3.0 V, IOL = 4 µA, COM1 VDD – 0.2 V 0.2 VDD – 0.2 V V 0.2 V [Duplex Drive (1/2 bias - 1/2 duty)] High-level output voltage VOH3 VDD = 3.0 V, IOH = –0.4 µA, SEGOUT Low-level output voltage VOL3 VDD = 3.0 V, IOL = 0.4 µA, SEGOUT High-level output voltage VOH4 VDD = 3.0 V, IOH = –4 µA, COM1 to COM2 Middle-level output voltage VOM VDD = 3.0 V, IOH = –4 µA, IOL = 4 µA, COM1 to COM2 Low-level output voltage VOL4 VDD = 3.0 V, IOL = 4 µA, COM1 to COM2 VDD – 0.2 V 0.2 VDD – 0.2 VDD1 – 0.2 V V VDD1 + 0.2 V 0.2 V [1/2 Bias - 1/3 Duty and 1/2 Bias - 1/4 Duty Drive] High-level output voltage VOH3 VDD = 3.0 V, IOH = –0.4 µA, SEGOUT Low-level output voltage VOL3 VDD = 3.0 V, IOL = 0.4 µA, SEGOUT High-level output voltage VOH4 VDD = 3.0 V, IOH = –4 µA, COM1 to COM3 (1/3 duty) COM1 to COM4 (1/4 duty) Middle-level output voltage VOM VDD = 3.0 V, IOH = –4 µA, IOL = 4 µA, COM1 to COM3 (1/3 duty) COM1 to COM4 (1/4 duty) Low-level output voltage VOL4 VDD = 3.0 V, IOL = 4 µA, COM1 to COM3 (1/3 duty) COM1 to COM4 (1/4 duty) VDD – 0.2 V 0.2 VDD – 0.2 VDD1 – 0.2 V V VDD1 + 0.2 V 0.2 V Continued on next page. No. 5944-17/24 LC5824, LC5823, LC5822 Continued from preceding page. Parameter Symbol Conditions and applicable pins Ratings min typ Unit max [1/3 Bias - 1/3 Duty and 1/3 Bias - 1/4 Duty Drive] High-level output voltage VOH3 VDD = 3.0 V, IOH = –0.4 µA, SEGOUT VDD3 – 0.2 M1-level output voltage VOM1–3 VDD = 3.0 V, IOH = –0.4 µA, IOL = 0.4 µA, SEGOUT VDD2 – 0.2 VDD2 + 0.2 V M2-level output voltage VOM2–3 VDD = 3.0 V, IOH = –0.4 µA, IOL = 0.4 µA, SEGOUT VDD1 – 0.2 VDD1 + 0.2 V Low-level output voltage VOL3 VDD = 3.0 V, IOL = 0.4 µA, SEGOUT 0.2 V VOH4 VDD = 3.0 V, IOH = –4 µA, COM1 to COM3 (in 1/3 duty mode) COM1 to COM4 (in 1/4 duty mode) VDD3 – 0.2 High-level output voltage V V M1-level output voltage VOH1–4 VDD = 3.0 V, IOH = –4 µA, IOL = 4 µA, COM1 to COM3 (in 1/3 duty mode) COM1 to COM4 (in 1/4 duty mode) VDD2 – 0.2 VDD2 + 0.2 V M2-level output voltage VOM2–4 VDD = 3.0 V, IOH = –4 µA, IOL = 4 µA, COM1 to COM3 (in 1/3 duty mode) COM1 to COM4 (in 1/4 duty mode) VDD1 – 0.2 VDD1 + 0.2 V Low-level output voltage VOL4 VDD = 3.0 V, IOL = 4 µA, COM1 to COM3 (in 1/3 duty mode) COM1 to COM4 (in 1/4 duty mode) 0.2 V (halver) VDD1 VDD = 3.0 V, fopg = 32.768 kHz, C1 to C4 = 0.1 µF, Figure 6 1.35 V (tripler) VDD3 VDD = 3.0 V, fopg = 32.768 kHz, C1 to C4 = 0.1 µF, Figure 6 4.1 V VDD1 VDD = 3.0 V, fopg = 32.768 kHz, C1 = C2 = 0.1 µF, Figure 7 1.35 V [Output Voltage] LCD drive method: 1/3 bias LCD drive method: 1/2 bias (halver) [Current Drain (With the backup flag cleared)] LCD drive method: 1/3 bias | IDD | VDD = 3.0 V, Halt mode C1 to C4 = 0.1 µF, C1 = 25 kΩ, Figure 6 Co = Cg = 20 pF, 32.768 kHz Xtal 2.0 µA LCD drive methods other than 1/3 bias | IDD | VDD = 3.0 V, Halt mode C1 = C2 = 0.1 µF, CI = 25 kΩ, Figure 7 Co = Cg = 20 pF, 32.768 kHz Xtal 1.0 µA Oscillator start capacitor | Vstt | VDD1 = VDD, CI = 25 kΩ, Figure 4 Co = Cg = 20 pF, 32.768 kHz Xtal Oscillator hold voltage (with the backup flag cleared) VHOLD VBAK = VDD1 = VDD/2, CI = 25 kΩ, Figures 6 and 7 Co = Cg = 20 pF, 32.768 kHz Xtal Oscillator start time Oscillator correction capacitance Tstt VDD1 = VDD = 1.35 V, CI = 25 kΩ, Figure 4 Co = Cg = 20 pF, 32.768 kHz Xtal 10P XC 20P XTOUT 1.35 2.6 V V 10 sec 8 10 12 pF 16 20 24 pF No. 5944-18/24 LC5824, LC5823, LC5822 EXT-V Specifications Absolute Maximum Ratings at Ta = 25°C ±2°C, VSS = 0 V Parameter Maximum supply voltage Maximum input voltage Maximum output voltage (LCD drive method: 1/3 bias) (LCD drive methods other than 1/3 bias) Symbol Conditions and applicable pins Ratings min typ max Unit VDD –0.3 +4.0 V VDD1 –0.3 +4.0 V VDD2 –0.3 +4.0 V VDD3 (LCD drive method: 1/3 bias) –0.3 +5.5 V VDD3 (LCD drive methods other than 1/3 bias) –0.3 +4.0 V VIN2 S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) RES, TST –0.3 VDD + 0.3 V M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in output mode) ALM, CUP2 –0.3 VDD + 0.3 V VOUT3 SEGOUT, COM1 to COM4, CUP1 –0.3 VDD3 + 0.3 V VOUT2 M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in output mode) ALM, SEGOUT, COM1 to COM4, CUP1 –0.3 VDD + 0.3 V VOUT2 Operating temperature Topg –20 +65 °C Storage temperature Tstg –30 +125 °C Allowable Operating Ranges at Ta = 25°C ±2°C, VSS = 0 V Parameter Supply voltage Symbol Conditions and applicable pins typ max Unit VDD1 1.3 3.6 V VDD VDD2 2.0 3.6 V 3.9 5.0 V VDD3 (LCD drive method: 1/3-bias) VDD3 (LCD drive methods other than 1/3 bias) High-level input voltage VIH S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) RES Low-level input voltage VIL S1 to S4, K1 to K4, M1 to M4, A1 to A4, SO1 to SO4, (With M1 to M4, A1 to A4, and SO1 to SO4 in input mode) RES Operating frequency Ratings min fopg VDD3 = VDD2 V VDD – 0.4 VDD V 0 0.4 V 32 33 kHz Ta = –20 + 65°C Electrical Characteristics at Ta = 25°C ±2°C, VSS = 0 V, VDD = VDD2 Parameter Input resistance Symbol Conditions and applicable pins Ratings min typ max Unit RIN1A VDD = 3.0 V, VIN = 0.35 VDD, Low level hold transistor *1, Figure 5 50 500 kΩ RIN1B VDD = 3.0 V, VIN = 0.7 VDD, Programmable pull-down resistor *1, Figure 5 50 1000 kΩ RIN2A VDD = 3.0 V, VIN = 0.35 VDD, Input mode, Low level hold transistor *1, Figure 5 50 500 kΩ RIN2B VDD = 3.0 V, VIN = 0.7 VDD, input mode, Programmable pull-down resistor *2, Figure 5 50 1000 kΩ VDD = 3.0 V, VIN = 0.7 VDD/0.3 VDD RES pin pull-up/pull-down resistor 10 300 kΩ RIN3 Continued on next page. No. 5944-19/24 LC5824, LC5823, LC5822 Continued from preceding page. Parameter Symbol Conditions and applicable pins High-level output voltage VOH1 VDD = 2.5 V, IOH = –250 µA, ALM Low-level output voltage VOL1 VDD = 2.5 V, IOL = 250 µA, ALM VOH2 VDD = 3.0 V, IOH = –40 µA, M1 to M4, A1 to A4, SO1 to SO4 (With M1 to M4, A1 to A4, and SO1 to SO4 in output mode) VOL2 VDD = 3.0 V, IOL = 40 µA, M1 to M4, A1 to A4, SO1 to SO4 (With M1 to M4, A1 to A4, and SO1 to SO4 in output mode) High-level output voltage Low-level output voltage Ratings min typ Unit max VDD – 0.65 V 0.65 VDD – 0.4 V V 0.4 V 1 V 1 V Segment driver output impedance [When Set Up as CMOS Output Ports] High-level output voltage VOH3 VDD = 2.4 V, IOH = –10 µA, Segment 1 to 42 Low-level output voltage VOL3 VDD = 2.4 V, IOL = 40 µA High-level output voltage VOH4 VDD = 2.4 V, IOH = –5 µA, Segment 1 to 42 Low-level output voltage VOL4 VDD = 2.4 V, IOL = 20 µA VDD – 1 V VDD – 1 V [When Set Up as P-Channel Open-Drain Output Ports] High-level output voltage VOH3 VDD = 2.4 V, IOH = –10 µA, Segment 1 to 42 Output off leakage current IOFF VDD = 2.6 V, VOL = VSS VDD – 0.2 0.3 1 V 1 µA [Static Drive] High-level output voltage VOH5 VDD = 3.0 V, IOH = –0.4 µA, SEGOUT Low-level output voltage VOL5 VDD = 3.0 V, IOL = 0.4 µA, SEGOUT High-level output voltage VOH6 VDD = 3.0 V, IOH = –4 µA, COM1 Low-level output voltage VOL6 VDD = 3.0 V, IOL = 4 µA, COM1 VDD – 0.2 V 0.2 VDD – 0.2 V V 0.2 V [Duplex Drive (1/2 bias - 1/2 duty)] High-level output voltage VOH5 VDD = 3.0 V, IOH = –0.4 µA, SEGOUT Low-level output voltage VOL5 VDD = 3.0 V, IOL = 0.4 µA, SEGOUT High-level output voltage VOH6 VDD = 3.0 V, IOH = –4 µA, COM1 to COM2 Middle-level output voltage VOM VDD = 3.0 V IOH = –4 µA, IOL = 4 µA, COM1 to COM2 Low-level output voltage VOL6 VDD = 3.0 V, IOL = 4 µA, COM1 to COM2 VDD2 – 0.2 V 0.2 VDD1 – 0.2 V V VDD1 + 0.2 V 0.2 V [1/2 Bias - 1/3 Duty and 1/2 Bias - 1/4 Duty Drive] High-level output voltage VOH5 VDD = 3.0 V, IOH = –0.4 µA, SEGOUT Low-level output voltage VOL5 VDD = 3.0 V, IOL = 0.4 µA, SEGOUT High-level output voltage VOH6 VDD = 3.0 V, IOH = –4 µA, COM1 to COM3 (1/3 duty) COM1 to COM4 (1/4 duty) VDD2 – 0.2 Middle-level output voltage VOM VDD = 3.0 V IOH = –4 µA, IOL = 4 µA, COM1 to COM3 (1/3 duty) COM1 to COM4 (1/4 duty) VDD1 – 0.2 Low-level output voltage VOL6 VDD = 3.0 V, IOL = 4 µA, COM1 to COM3 (1/3 duty) COM1 to COM4 (1/4 duty) VDD – 0.2 V 0.2 V V VDD1 + 0.2 V 0.2 V Continued on next page. No. 5944-20/24 LC5824, LC5823, LC5822 Continued from preceding page. Parameter Symbol Conditions and applicable pins Ratings min typ Unit max [1/3 Bias - 1/3 Duty and 1/3 Bias - 1/4 Duty Drive] High-level output voltage Middle-level output voltage Low-level output voltage High-level output voltage VOH5 VOM1–5 VOM2–5 VDD3 + 0.2 VDD = 3.0 V, IOH = –0.4 µA, IOL = 0.4 µA, SEGOUT VDD2 – 0.2 VDD2 + 0.2 V V VDD = 3.0 V, IOH = –0.4 µA, IOL = 0.4 µA, SEGOUT VDD1 – 0.2 VDD1 + 0.2 V 0.2 V VOL5 VDD = 3.0 V, IOL = 0.4 µA, SEGOUT VOH6 VDD = 3.0 V, IOH = –0.4 µA, COM1 to COM3 (in 1/3 duty mode) COM1 to COM4 (in 1/4 duty mode) VDD3 + 0.2 VOM1–6 VDD = 3.0 V, IOH = –0.4 µA, IOL = 0.4 µA, COM1 to COM3 (in 1/3 duty mode) COM1 to COM4 (in 1/4 duty mode) VDD2 – 0.2 VDD2 + 0.2 V VOM2–6 VDD = 3.0 V, IOH = –0.4 µA, IOL = 0.4 µA, COM1 to COM3 (in 1/3 duty mode) COM1 to COM4 (in 1/4 duty mode) VDD1 – 0.2 VDD1 + 0.2 V 0.2 V Middle-level output voltage Low-level output voltage VDD = 3.0 V, IOH = –0.4 µA, SEGOUT V VOL6 VDD = 3.0 V, IOL = 0.4 µA (halver) VDD1 VDD = 3.0 V, fopg = 32.768 kHz, C1 to C4 = 0.1 µF, Figure 6 1.35 V (tripler) VDD3 VDD = 3.0 V, fopg = 32.768 kHz, C1 to C4 = 0.1 µF, Figure 6 4.1 V VDD1 VDD = 3.0 V, fopg 32.768 kHz, C1 = C2 = 0.1 µF, Figure 7 1.35 V [Output Voltage] LCD drive method: 1/3 bias LCD drive method: 1/2 bias (halver) [Current Drain (With the backup flag cleared)] LCD drive method: 1/3 bias | IDD | VDD = 3.0 V, Halt mode, C1 to C4 = 0.1 µF, CI = 25 kΩ Co = Cg = 20 pF, 32.768 kHz Xtal, Figure 6 5.0 µA LCD drive methods other than 1/3 bias | IDD | VDD = 3.0 V, Halt mode, C1 to C2 = 0.1 µF, CI = 25 kΩ, Figure 7, Co = Cg = 20 pF, 32.768 kHz, Xtal 5.0 µA Oscillator start voltage Oscillator hold voltage (with the backup flag cleared) Oscillator start time Oscillator correction capacitance Vstt VHOLD VDD = VDD2, CI = 25 kΩ, Figure 4, Co = Cg = 20 pF, 32.768 kHz Xtal VDD = VDD2, CI = 25 kΩ, , Figures 5, 6, 7, and 8, Co = Cg = 20 pF, 32.768 kHz Xtal Tstt VDD = VDD2 = 2.2 V, CI = 25 kΩ, Figure 4 Co = Cg = 20 pF, 32.768 kHz Xtal 10P XC 20P XTOUT 2.2 2.0 V V 10 sec 8 10 12 pF 16 20 24 pF Note : 1. S1 to 4, K1 to 4 2. M1 to 4, A1 to 4, SO1 to 4 No. 5944-21/24 LC5824, LC5823, LC5822 Can be applied by application software Figure 1 S1 to S4, K1 to K4, M1 to M4, A1 to A4, and SO1 to SO4 Figure 2 Output Voltage, Current Drain, and Oscillator Hold Voltage Test Circuit Figure 3 Output Voltage, Current Drain, and Oscillator Hold Voltage Test Circuit No. 5944-22/24 LC5824, LC5823, LC5822 Figure 4 Oscillator Start Voltage, Oscillator Start Time, and Frequency Stability Test Circuit Can be applied by application software Figure 5 S1 to S4, K1 to K4, M1 to M4, A1 to A4, and SO1 to SO4 Figure 6 Output Voltage, Current Drain, and Oscillator Hold Voltage Test Circuit No. 5944-23/24 LC5824, LC5823, LC5822 Figure 7 Output Voltage, Current Drain, and Oscillator Hold Voltage Test Circuit Figure 8 Output Voltage, Current Drain, and Oscillator Hold Voltage Test Circuit Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any and all SANYO products described or contained herein fall under strategic products (including services) controlled under the Foreign Exchange and Foreign Trade Control Law of Japan, such products must not be exported without obtaining export license from the Ministry of International Trade and Industry in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 1998. Specifications and information herein are subject to change without notice. PS No. 5944-24/24