Ordering number : ENN6498 CMOS IC LC651432N/F/L, 651431N/F/L Four-Bit CMOS Microcontrollers for Small-Scale Control Applications Overview The LC651431N/F/L and LC651432N/F/L are the smallscale control models in Sanyo’s LC6500 Series of 4-bit microcontrollers and feature the same basic architecture and instruction set. These microcontrollers are appropriate for a wide range of applications, from applications that require only a limited number of circuits and controls and were previously implemented in standard logic to larger application such as audio equipment, including tape decks and disc players, office equipment, communication equipment, automotive equipment, and home appliances. Furthermore, since these products have equivalent basic functions (although there are differences in some functions and characteristics) and are pin compatible with the earlier LC6543N/F/L and LC6546N/F/L products, they can be used to replace those devices. Features • Fabricated in a CMOS process for low power operation (Standby mode can be controlled by CPU instructions.) • ROM/RAM LC651432N/F/L —ROM: 2 K × 8 bits, RAM: 128 × 4 bits LC651431N/F/L —ROM: 1 K × 8 bits, RAM: 64 × 4 bits • Instruction set: The 80-instruction set common to the whole LC6500 Series • Wide operating supply voltage range of 2.2 to 6.0 V (L versions) • Instruction cycle time of 0.92 µs (F versions) • On-chip serial I/O function • Highly flexible I/O ports Number of ports — 7 ports (Up to 25 pins) All ports — Can be used for either input or output — Voltage handling capability (input and output): 15 V maximum (For open-drain specification ports) — Output current: 20 mA maximum sink current (Capable of directly driving an LED.) I/O port options to match application requirements: — Open-drain output and pull-up resistor specification: Can be specified for all ports in bit units. — Output level at reset specification: Either a high or low level can be specified for ports C and D in 4-bit units each. • Interrupts Timer overflow vector interrupt (can also be tested by CPU instructions) INT pin or serial I/O full/empty vector interrupt (can also be tested by CPU instructions) • Stack levels: 4 levels (also used by interrupts) • Timers: 8-bit programmable timer with 4-bit prescaler • Clock oscillator options to match application requirements: Oscillator circuit option: — Two-pin RC oscillator (N and L versions) Two-pin ceramic oscillator or single external clock input pin (N, F, and L versions) — Divider circuit option: No divider, built-in divideby-three circuit, built-in divide-by-four circuit (N and L versions) • Continuous square-wave output with a period 64 times the cycle time. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 40700RM (OT) No. 6498-1/39 LC651432N/F/L, 651431N/F/L Package Dimensions unit : mm 3196A-DIP30SD unit : mm 3191A-SSOP30 [LC651432N/F/L, 651431N/F/L] [LC651432N/F/L, 651431N/F/L] 27.0 1 15 0.5 1.5max (3.25) 0.95 0.15 0.1 (1.3) 0.51min 9.75 0.48 (1.04) 7.6 5.6 10.16 15 0.25 1 3.0 3.95max 16 16 8.6 30 30 0.22 1.78 SANYO: DIP30SD 0.65 (0.33) SANYO: SSOP30 unit : mm 3216B-MFP30S [LC651432N/F/L, 651431N/F/L] 10.5 16 15 0.15 0.4 1.0 (0.6) 0.1 (2.15) 15.2 0.65 1 2.45max 7.9 30 SANYO: MFP30S No. 6498-2/39 LC651432N/F/L, 651431N/F/L Function Overview Parameter LC651432N/1431N ROM RAM 128 × 4 bits (1432N/F/L) 64 × 4 bits (1431N/F/L) Memory Instructions Instruction set Provided One external, one internal Timers 8-bit timer with 4-bit prescaler Stack levels 4 HALT instruction based standby function Provided Standby function Number of ports Up to 25 I/O pins Serial ports I/O in 4-bit or 8-bit units I/O voltage I/O ports 15 V max. Output current 10 mA typ. 20 mA max. I/O circuit types Open drain (n channel) or built-in pull-up resistor output can be specified in 1-bit units. Output level at reset High or low can be specified in port units (C and D ports only) Square-wave output Oscillator 0.92 µs (VDD ≥ 3 V) 3.84 µs (VDD ≥ 2.2 V) Supply voltage 3 to 6 V 3 to 6 V 2.2 to 6 V Supply current 1 mA typ. 1.5 mA typ. Oscillator element Divider circuit option Other features Possible 2.77 µs (VDD ≥ 3 V) Minimum cycle time Characteristics LC651432L/1431L 80 Table reference Interrupts On-chip functions LC651432F/1431F 2048 × 8 bits (1432N/F/L) 1024 × 8 bits (1431N/F/L) Package RC oscillator (400 or 800 kHz typical) Ceramic oscillator (400 kHz, 800 kHz, 1 MHz, or 4 MHz) 1/1, 1/3, 1/4 Ceramic oscillator: 4 MHz 1/1 1 mA typ. RC oscillator (400 kHz typical) Ceramic oscillator (400 kHz or 4 MHz) 1/1, 1/3, 1/4 DIP30S-D, MFP30S, SSOP30 Note: Sanyo will be providing details on oscillator elements and oscillator circuit constants as recommended circuits are developed. Contact your Sanyo representative for more information. No. 6498-3/39 LC651432N/F/L, 651431N/F/L Differences between the LC651432N/LC651431N and the LC6543N/LC6546N This table lists the points that require care when replacing the LC6543N/LC6546N with the LC651432N/LC651431N in completes end products. Parameter Allowable power dissipation LC651432N/1431N LC6543N/46N Pdmax(1) : DIP 310 mW 250 mW Pdmax(2) : MFP 220 mW 150 mW Pdmax(3) : SSOP 160 mW (This package not available.) VIO(3) added High-level input voltage VIH(n) VIH(1) to VIH(7) (Associated with the I/O voltage (PI0) changes mentioned above.) VIH(1) to VIH(6) High-level input current IIH(n) IIH(1) to IIH(3) (Associated with the I/O voltage (PI0) changes mentioned above.) IIH(1) to IIH(2) Oscillator frequency precision: ±2% Recommended oscillator circuit constants (under evaluation) Oscillator frequency precision: ±4% 800 kHz typical (VDD = 3 to 6 V) Circuit constant changes: Rext = 6.8 kΩ ±1% Sample-to-sample frequency variation: 595 to 1274 kHz 850 kHz typical (VDD = 4 to 6 V) Circuit constant changes: Rext = 4.7 kΩ ±1% Sample-to-sample frequency variation: 619 to 1144 kHz 400 kHz typical (VDD = 3 to 6 V) Sample-to-sample frequency variation: 284 to 790 kHz 400 kHz typical (VDD = 3 to 6 V) Sample-to-sample frequency variation: 305 to 546 kHz fCFOSC [OSC1, OSC2] Oscillator characteristics Ceramic oscillator Oscillator frequency 2-pin RC oscillator Oscillator frequency fMOSC [OSC1, OSC2] Current drain IDD Serial clock input clock cycle time tCKCY(1)[SCK] Package –0.3 to VDD + 0.3 –0.3 to +15 V (When open-drain output is used.) I/O voltage (PIO) –0.3 to VDD + 0.3 (When a pull-up resistor is used.) 1 mA typ. 2 mA typ. min. 2.0 µs min 3.0 µs DIP30S-D, MFP30S, SSOP30 added DIP30S-D, MFP30S Differences between the LC651432F/LC651431F and the LC6543F/LC6546F This table lists the points that require care when replacing the LC6543F/LC6546F with the LC651432F/LC651431F in completes end products. Parameter Allowable power dissipation Operating supply voltage I/O voltage (PI0) LC651432F/1431F LC6543F/46F Pdmax(1) : DIP 310 mW 250 mW Pdmax(2) : MFP 220 mW 150 mW Pdmax(3) : SSOP 160 mW (This package not available.) VDD 3 to 6 V VIO(3) added –0.3 to VDD + 0.3 4.5 to 6 V –0.3 to +15 V (When open-drain output is used.) –0.3 to VDD + 0.3 (When a pull-up resistor is used.) High-level input voltage VIH(n) VIH(1) to VIH(7) (Associated with the I/O voltage (PI0) changes mentioned above.) High-level input current IIH(n) IIH(1) to IIH(3) (Associated with the I/O voltage (PI0) changes mentioned above.) IIH(1) to IIH(2) Low-level input voltage VIL(n) IIH(1) to IIH(3) Specifications when VDD = 4 to 6 V Specifications added for VDD = 3 to 6 V Specifications when VDD = 4 to 6 V Oscillator characteristics Ceramic oscillator Oscillator frequency fCFOSC [OSC1, OSC2] Oscillator frequency precision: ±2% Oscillator frequency precision: ±4% Current drain IDD 1.5 mA typ. 2.5 mA typ. Serial clock input clock cycle time tCKCY(1)[SCK] min. 2.0 µs min 3.0 µs DIP30S-D, MFP30S, SSOP30 added DIP30S-D, MFP30S Package VIH(1) to VIH(6) No. 6498-4/39 LC651432N/F/L, 651431N/F/L Differences between the LC651432L/LC651431L and the LC6543L/LC6546L This table lists the points that require care when replacing the LC6543L/LC6546L with the LC651432L/LC651431L in completes end products. Parameter Allowable power dissipation LC651432L/1431L LC6543L/46L Pdmax(1) : DIP 310 mW 250 mW Pdmax(2) : MFP 220 mW 150 mW Pdmax(3) : SSOP 160 mW (This package not available.) –0.3 to +15 V (When open-drain output is used.) I/O voltage (PI0) VIO(3) added High-level input voltage VIH(n) VIH(1) to VIH(7) (Associated with the I/O voltage (PI0) changes mentioned above.) VIH(1) to VIH(6) High-level input current IIH(n) IIH(1) to IIH(3) (Associated with the I/O voltage (PI0) changes mentioned above.) IIH(1) to IIH(2) fCFOSC [OSC1, OSC2] Oscillator frequency precision: ±2% Recommended oscillator circuit constants (under evaluation) Oscillator frequency precision: ±4% fMOSC [OSC1, OSC2] 400 kHz typical (VDD = 2.2 to 6 V) Circuit constant changes: Rext = 15 kΩ ±1% Sample-to-sample frequency variation: 200 to 790 kHz 400 kHz typical (VDD = 2.2 to 6 V) Circuit constant changes: Rext = 12 kΩ ±1% Sample-to-sample frequency variation: 284 to 546 kHz 1 mA typ. 2 mA typ. DIP30S-D, MFP30S, SSOP30 added DIP30S-D, MFP30S Oscillator characteristics Ceramic oscillator Oscillator frequency 2-pin RC oscillator Oscillator frequency Current drain –0.3 to VDD + 0.3 IDD Package –0.3 to VDD + 0.3 (When a pull-up resistor is used.) Caution: Always test the end product thoroughly after changing the microcontroller used. Pin Assignment 20 PC0 19 RES 18 VSS 17 TEST 16 OSC1 PA0 11 PA1 12 PA2 13 PA3 14 PI0/OSC2 15 21 PC1 22 PC2 23 PC3 24 PD0 25 PD1 26 PD2 27 PD3 28 PE0 29 PE1 30 PE2 The same pin assignment is used for the DIP, MFP, and SSOP packages. PG3 10 PG2 9 PG1 8 PG0 7 PF3/INT 6 PF2/SCK 5 PF1/SO 4 PF0/SI 3 VDD 2 PE3 1 LC651432N/F/L LC651431N/F/L No. 6498-5/39 LC651432N/F/L, 651431N/F/L Pin Nomenclature OSC1, OSC2: Connections for capacitor and resistor oscillator components or a ceramic oscillator element. PG0 to 3: Shared-function I/O port G0 to 3 PI0: Shared-function I/O port IO RES: Reset TEST: Test PA0 to 3: Shared-function I/O port A0 to 3 INT: Interrupt request PC0 to 3: Shared-function I/O port C0 to 3 SI: Serial input PD0 to 3: Shared-function I/O port D0 to 3 SO: Serial output PE0 to 3: Shared-function I/O port E0 to 3 SCK: Serial clock input or output pin PF0 to 3: Shared-function I/O port F0 to 3 Notes: 1. The SI, SO, SCK, and INT pins are shared-function pins also used as PF0 to 3. 2. OSC2 and PIO are a single pin set exclusively to one or the other function as a user option. System Block Diagram LC651432N/F/L, LC651431N/F/L PC0 to 3 Port C PD0 to 3 Port D PE0 to 3 Port E PF0 to 3 Port F Shared with port F PF1/SO 4/8 bits RAM F WR Port A Serial shift register I/O buffer PA0 to 3 PC ROM STACK 1 STACK 2 STACK 3 STACK 4 DP IR System bus E AC ALU Serial mode register STS CF ZF EXTF TMF CSF ZSF 4 bits OSC Port I PG0-3 PI0 * CTL OSC1 OSC2* RES TEST VDD VSS I/O bus Port G TM INT Serial mode register Lower digit Serial shift register I.DEC Higher PF0/SI 4/8 bits PF2/SCK PF3/INT Note: * OSC2 and PIO are a single pin set exclusively to one or the other function as a user option. RAM: F: WR: AC: ALU: DP: E: CTL: OSC: TM: STS: Data memory Flags Working register Accumulator Arithmetic and logic unit Data pointer E register Control register Oscillator circuit Timer Status register ROM: PC: INT: IR: I.DEC: CF, CSF: ZF, ZSF: EXTF: TMF: Program memory Program counter Interrupt control Instruction register Instruction decoder Carry flag, carry save flag Zero flag, zero save flag External interrupt request flag Internal interrupt request flag No. 6498-6/39 LC651432N/F/L, 651431N/F/L Development Support The following are available to support the development of LC651431 and LC651432 applications. • User’s manual “LC6543/46 User’s Manual” No. E71 • Development tool manual See the “EVA86000 Development Tool Manual for 4-Bit Microcontrollers.” • Software manual “LC65/66 Series Software Manual” • Development tools Program development: EVA86000 System Program evaluation: LC65E43 on-chip EPROM microcontroller Pins Functions Function Options Pin I/O 1 VDD — 1 VSS — 1 OSC1 Input 4 PA0 to PA3 I/O • I/O port A0 to 3 1. Open-drain output • High-level Input in 4-bit units (IP instruction) 2. Built-in pull-up resistor output (with Output in 4-bit units (OP instruction) Options 1 and 2 may be specified the output nTest in single-bit units (BP and BNP instructions) in bit units. channel Set/reset in single-bit units (SPB and RPB transistor off) instructions) • PA3 (Any one of PA0 to 3 can be selected) is used for standby mode control. • Applications must assure that key bounce or similar noise does not occur on PA3 (or PA0 to 3) during a HALT instruction execution cycle. The open-drain output option must be selected and the pin connected to VSS. 4 PC0 to PC3 I/O • I/O port C0 to 3 Provides the same functions as PA0 to 3. (See note.) • The output level at reset can be specified to be either high or low. Note: This port does not have the standby mode control function. 1. Open-drain output 2. Built-in pull-up resistor 3. High-level output at reset 4. Low-level output at reset • Options 1 and 2 may be specified in bit units. • Options 3 and 4 are specified in a single 4-bit group • High-level output • Low-level output (Specified as a user option.) The same as that for PC0 to 3 4 PD0 to PD3 I/O • I/O port D0 to 3 Provides the same functions as PC0 to 3. The same as those for PC0 to 3. The same as The same as those for PC0 to 3. those for PC0 to 3. Power supply — • Connection for the external system clock RC or ceramic oscillator element • When a single pin is used for external clock input, the PI0/OSC2 pin is used as the PI0 I/O port. • When a 2-pin RC oscillator or a 2-pin ceramic oscillator is used, the PI0/OSC2 pin is used as the OSC2 oscillator pin. 1. 2. 3. 4. Single-pin external clock input 2-pin RC oscillator 2-pin ceramic oscillator Divider circuit option • No divider • Divide-by-three circuit • Divide-by-four circuit Reset state Handling when unused Count — — — — Continued on next page. No. 6498-7/39 LC651432N/F/L, 651431N/F/L Continued from preceding page. Options Reset state Handling when unused Count Pin I/O Function 4 PE0 to PE3 I/O • I/O port E0 to 3 Input in 4-bit units (IP instruction) Output in 4-bit units (OP instruction) Set/reset in single-bit units (SPB and RPB instructions) Test in single-bit units (BP and BNP instructions) • PE0 also has a continuous pulse (64Tcyc) output function. 1. Open-drain output • High-level 2. Built-in pull-up resistor output (with Options 1 and 2 may be specified the output nin bit units. channel transistor off) 4 PF0/SI PF1/SO PF2/SCK PF3/INT I/O • I/O port F0 to 3 Functions and options identical to PE0 to 3. (See note.) • PF0 to 3 have shared functions as the serial interface pins and the INT input. Either function can be selected under program control. SI ... Serial input port SO ... Serial output port SCK ... Serial clock input or output INT ... Interrupt request input Serial input/output is switched between 4-bit and 8-bit units under program control. Note: This port does not have a continuous pulse output function. The same as those for PE0 to 3. The same as The same as that for PE0 to 3. that for The serial port PA0 to 3. is disabled and INT is the interrupt source. 4 PG0 to PG3 I/O • I/O port G0 to 3 Functions and options identical to PE0 to 3. (See note.) Note: This port does not have a continuous pulse output function. The same as those for PE0 to 3. The same as those for PE0 to 3. The same as that for PA0 to 3. 1 PI0/OSC2 I/O • I/O port IO Output Functions and options identical to PG0 to 3. • However, consists of a single bit. • When a 2-pins oscillator is used, this pin functions as the OSC2 pin, and the I/O port function is not available. The same as those for PG0 to 3. The same as those for PG0 to 3. The same as that for PA0 to 3. 1 RES Input • System reset input • Connect an external capacitor to implement a power-on reset. • The reset start operation requires that a low level be held for at least 4 clock cycles. — — — 1 TEST Input • IC test pin This pin must be connected to VSS during normal operation. — — This pin must be connected to VSS. The same as that for PA0 to 3. No. 6498-8/39 LC651432N/F/L, 651431N/F/L Oscillator Circuit Options Option Circuit Conditions and notes OSC1 External clock The PI0/OSC2 pin is used as the PI0 pin. OSC1 Cext The PI0/OSC2 pin is used as the OSC2 pin and the port function is unavailable. Two-pin RC oscillator PI0/OSC Rext C1 Ceramic oscillator OSC1 Ceramic oscillator element The PI0/OSC2 pin is used as the OSC2 pin and the port function is unavailable. PI0/OSC R C2 Divider Circuit Options Option Circuit Conditions and notes Timing generator No divider circuit (1/1) Oscillator circuit • Applicable to all three oscillator options. fOSC • The oscillator frequency or the external clock must not exceed 1444 kHz. (LC651431N and LC651432N) • The oscillator frequency or the external clock must not exceed 4330 kHz. (LC651431F and LC651432F) fOSC fOSC 3 Divide-by-three circuit Divide-by-four circuit fOSC 4 Timing generator Oscillator circuit Divide-by-four circuit (1/4) fOSC • Only applicable to the external clock and the ceramic oscillator option. Timing generator Divide-by-three circuit (1/3) Oscillator circuit • The oscillator frequency or the external clock must not exceed 1040 kHz. (LC651431L and LC651432L) • Only applicable to the external clock and the ceramic oscillator option. • The oscillator frequency or the external clock must not exceed 4330 kHz. • The oscillator frequency or the external clock must not exceed 4330 kHz. Caution: The following table summarizes the oscillator and divider option combinations. Use care when selecting these options. No. 6498-9/39 LC651432N/F/L, 651431N/F/L Oscillator Divider Options for the LC651431N/LC651432N, LC651431F/LC651432F, and LC651431L/LC651432L LC651432N, LC651431N Oscillator type Ceramic oscillator Frequency 400 kHz 800 kHz 1 MHz 4 MHz Single-pin external clock input Divider option (cycle time) 1/1 (10 µs) VDD range 3 to 6 V 1/1 (5 µs) 3 to 6 V 1/3 (15 µs) 3 to 6 V 1/4 (20 µs) 3 to 6 V 1/1 (4 µs) 3 to 6 V 1/3 (12 µs) 3 to 6 V 1/4 (16 µs) 3 to 6 V 1/3 (3 µs) 3 to 6 V 1/4 (4 µs) 3 to 6 V 200 to 1444 kHz 1/1 (20 to 2.77 µs) 3 to 6 V 600 to 4330 kHz 1/3 (20 to 2.77 µs) 3 to 6 V 800 to 4330 kHz 1/4 (20 to 3.70 µs) 3 to 6 V Notes The divide-by-three and divide-by-four circuits cannot be used. The no-divider (1/1) option cannot be used. External clock provided by a 2-pin RC oscillator circuit As above 2-pin RC oscillator Using the no-divider (1/1) option and the 3 to 6 V recommended circuit constants. If the use of circuit values other than the recommended values is unavoidable, the frequencies, divider options, and VDD ranges specified for the single-pin external clock input option must be strictly observed. External clock used with the ceramic oscillator option The IC cannot be driven by an external clock with this option. If external clock drive is required, select either the external clock option or the 2-pin RC oscillator option LC651432F, LC651431F Oscillator type Ceramic oscillator Frequency Divider option (cycle time) VDD range Notes 4 MHz 1/1 (1 µs) 3 to 6 V Single-pin external clock input 200 to 4330 kHz 1/1 (20 to 0.92 µs) 3 to 6 V External clock used with the ceramic oscillator circuit The IC cannot be driven by an external clock with this option. If external clock drive is required, select the external clock option. LC651432L, LC651431L Oscillator type Ceramic oscillator Single-pin external clock input Frequency Divider option (cycle time) VDD range Notes 400 kHz 1/1 (10 µs) 2.2 to 6 V The divide-by-three and divide-by-four circuits cannot be used. 4 MHz 1/4 (4 µs) 2.2 to 6 V The no-divider (1/1) and divide-by-three option cannot be used. 200 to 1040 kHz 1/1 (20 to 3.84 µs) 2.2 to 6 V 600 to 3120 kHz 1/3 (20 to 3.84 µs) 2.2 to 6 V 800 to 4160 kHz 1/4 (20 to 3.84 µs) 2.2 to 6 V External clock provided by a 2-pin RC oscillator circuit As above 2-pin RC oscillator Using the no-divider (1/1) option and the 2.2 to 6 V recommended circuit constants. If the use of circuit values other than the recommended values is unavoidable, the frequencies, divider options, and VDD ranges specified for the single-pin external clock input option must be strictly observed. External clock used with the ceramic oscillator option The IC cannot be driven by an external clock with this option. If external clock drive is required, select either the external clock option or the 2-pin RC oscillator option No. 6498-10/39 LC651432N/F/L, 651431N/F/L Port C and D Output Level at Reset Option One of the following two options for the output level at reset may be chosen for the I/O ports C and D in 4-bit group units. Option Conditions and notes High-level output at reset Ports C and D in 4-bit units Low-level output at reset Ports C and D in 4-bit units Port Output Circuit Type Option One of the following two options for the circuit type can be selected for the I/O ports in bit units. Option Circuit Applicable ports Open-drain output • Not applicable to the PI0/OSC2 pin if either the 2-pin RC oscillator or the ceramic oscillator is selected as the oscillator circuit. Built-in pull-up resistor output No. 6498-11/39 LC651432N/F/L, 651431N/F/L Specifications LC651432N, 651431N Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Maximum supply voltage Output voltage Input voltage I/O voltage Symbol Conditions Applicable pins VDD max VO OSC2 Allowable power dissipation V Voltages up to the voltage generated are allowed. V VI(1) OSC1 *1 –0.3 to VDD +0.3 V TEST, RES –0.3 to VDD +0.3 V –0.3 to +15 V V VIO(1) Ports with open-drain specifications VIO(2) Ports with pull-up resistor specifications –0.3 to VDD +0.3 PI0 –0.3 to VDD +0.3 V I/O ports –2 to +20 mA Per single pin, the average over a 100 ms period I/O ports –2 to +20 mA ΣIOA(1) The total current for PC0 to 3, PD0 to 3, and PE0 to 3*2 PC0 to 3 PD0 to 3 PE0 to 3 –15 to +100 mA ΣIOA(2) The total current for PF0 to 3, PG0 to 3, PA0 to 3, and PI0*2 PF0 to 3, PI0 PG0 to 3 PA0 to 3 –15 to +100 mA Pd max(1) Ta = –40 to +85°C (DIP package) 310 mW Pd max(2) Ta = –40 to +85°C (MFP package) 220 mW Pd max(3) Ta = –40 to +85°C (SSOP package) 160 mW IOP IOA Average output current Unit –0.3 to +7.0 VI(2) VIO(3) Peak output current Ratings VDD Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to 125 °C Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V, VDD = 3.0 to 6.0 V (unless otherwise specified) Parameter Operating supply voltage Standby supply voltage High-level input voltage Symbol Conditions VDD Applicable pins Ratings min typ max Unit VDD 3.0 6.0 V VST RAM and register contents retained. *3 VDD 1.8 6.0 V VIH(1) With the n-channel output transistors off Ports with open-drain specifications (except for I0) 0.7 VDD 13.5 V VIH(2) With the n-channel output transistors off Ports with pull-up resistor specifications (except for I0) 0.7 VDD VDD V VIH(3) With the n-channel output transistors off Port I0 0.7 VDD VDD V VIH(4) With the n-channel output transistors off The INT, SCK, and SI pins with open-drain specifications 0.8 VDD 13.5 V VIH(5) With the n-channel output transistors off The INT, SCK, and SI pins with pull-up resistor specifications 0.8 VDD VDD V VIH(6) VDD = 1.8 to 6 V RES 0.8 VDD VDD V VIH(7) External clock specifications OSC1 0.8 VDD VDD V Continued on next page. No. 6498-12/39 LC651432N/F/L, 651431N/F/L Continued from preceding page. Parameter Symbol Pulse width Rise and fall time Ratings min typ max Unit With the n-channel output transistors off VDD = 4 to 6 V Port VSS 0.3 VDD V VIL(2) With the n-channel output transistors off 3 to 6 V Port VSS 0.25 VDD V VIL(3) With the n-channel output transistors off VDD = 4 to 6 V INT, SCK, SI VSS 0.25 VDD V VIL(4) With the n-channel output transistors off 3 to 6 V INT, SCK, SI VSS 0.2 VDD V VIL(5) External clock specifications VDD = 4 to 6 V OSC1 VSS 0.25 VDD V VIL(6) External clock specifications 3 to 6 V OSC1 VSS 0.2 VDD V VIL(7) VDD = 4 to 6 V TEST VSS 0.3 VDD V VIL(8) 3 to 6 V TEST VSS 0.25 VDD V VIL(9) VDD = 4 to 6 V RES VSS 0.25 VDD V VIL(10) 3 to 6 V RES VSS 0.2 VDD V 200 (20) 1444 (2.77) kHz (µs) OSC1 200 4330 kHz OSC1 69 fop (Tcyc) External clock conditions Frequency Applicable pins VIL(1) Low-level input voltage Operating frequency (cycle time) Conditions A clock frequency of up to 4.33 MHz may be used when either the divide-by-three circuit or the divide-by-four circuit is used. See figure 1. text The divide-by-three circuit or the divide-by-four circuit textH, textL must be used if the clock frequency exceeds 1.444 textR, textF MHz. ns OSC1 50 ns Recommended oscillator circuit constants Two-pin RC oscillator Cext See figure 2. OSC1, OSC2 Rext Cext See figure 2. Rext Ceramic oscillator*4 See figure 3. OSC1, OSC2 220 ± 5% pF 12 ±1% kΩ 220 ±5% pF 6.8 ±1% kΩ See table 1. No. 6498-13/39 LC651432N/F/L, 651431N/F/L Electrical Characteristics at Ta = –40 to +85°C, VSS = 0 V, VDD = 3.0 to 6.0 V (unless otherwise specified) Parameter Conditions Applicable pins Open-drain specification ports (except I0) IIH(1) • With the output n-channel transistors off (Including the n-channel transistor off leakage current.) • VIN = 13.5 V The I0 port with open-drain specifications IIH(2) • With the output n-channel transistors off (Including the n-channel transistor off leakage current.) • VIN = VDD IIH(3) • External clock mode • VIN = VDD OSC1 IIL(1) • With the output n-channel transistors off • VIN = VSS Open-drain specification ports –1.0 IIL(2) • With the output n-channel transistors off • VIN = VSS Built-in pull-up resistor specification ports –1.3 –0.35 mA IIL(3) VIN = VSS RES –45 –10 µA IIL(4) • External clock mode • VIN = VSS OSC1 –1.0 µA VOH(1) • IOH = –50 µA • VDD =4.0 to 6.0 V Built-in pull-up resistor specification ports VDD – 1.2 V VOH(2) • IOH = –10 µA Built-in pull-up resistor specification ports VDD – 0.5 V VOL(1) • IOL = 10 mA • VDD = 4.0 to 6.0 V Ports 1.5 V VOL(2) IOL = 1 mA, when IOL for all ports is less than or equal to 1 mA. Ports 0.5 V High-level input current Low-level input current High-level output voltage Low-level output voltage Schmitt characteristics Ratings Symbol Hysteresis voltage VHIS High-level threshold voltage VtH Low-level threshold voltage VtL min typ Unit max 5.0 µA 1.0 µA 1.0 µA µA V 0.1 VDD RES, INT, SCK, SI, and OSC1 with Schmitt trigger specifications*5 0.4 VDD 0.8 VDD V 0.2 VDD 0.6 VDD V Current drain*6 Two-pin RC oscillator IDDOP(1) Ceramic oscillator External clock Standby mode • While operating, with the output n-channel transistors off • Port voltage = VDD • Figure 2, fosc = 800 kHz (typical) VDD 1 3 mA IDDOP(2) See figure 2. fosc = 400 kHz (typical) VDD 0.8 2.5 mA IDDOP(3) • Figure 3, 4 MHz, divideby-three circuit used. VDD 1 3 mA IDDOP(4) • Figure 3, 4 MHz, divideby-four circuit used. VDD 1 3 mA IDDOP(5) See figure 3. 400 kHz VDD 1 2.5 mA IDDOP(6) See figure 3. 800 kHz VDD 1 3 mA IDDOP(7) • 200 to 1444 kHz, no divider • 600 to 4330 kHz, divideby-three circuit used VDD • 800 to 4330 kHz, divideby-four circuit used 1 4 mA VDD 0.05 10 µA VDD 0.025 5 µA IDDst Output n-channel transistors off, VDD = 6 V Port voltage = VDD, VDD = 3 V Continued on next page. No. 6498-14/39 LC651432N/F/L, 651431N/F/L Continued from preceding page. Parameter Symbol Conditions Applicable pins Ratings min typ 392 784 980 3920 400 800 1000 4000 max Unit Oscillator characteristics Ceramic oscillator Oscillator frequency fCFOSC*7 Oscillator stabilization time*8 tCFS Two-pin RC oscillator Oscillator frequency Built-in pull-up resistor I/O ports RES External reset characteristics Reset time Pin capacitance fMOSC • • • • Figure 3, fo = 400 kHz Figure 3, fo = 800 kHz Figure 3, fo = 1 MHz Figure 3, fo = 4 MHz, divide-by-three or divideby-four circuit used. OSC1, OSC2 OSC1, OSC2 OSC1, OSC2 OSC1, OSC2 • Figure 4, fo = 400 kHz • Figure 4, fo = 800 kHz, 1 MHz, or 4 MHz, divideby-three or divide-by-four circuit used. kHz kHz kHz kHz 10 10 ms ms • Figure 2, Cext = 220 pF ±5% OSC1, OSC2 • Figure 2, Rext = 6.8 kΩ ±1% 595 800 1274 kHz • Figure 2, Cext = 220 pF ±5% OSC1, OSC2 • Figure 2, Rext = 12 kΩ ±1% 284 400 790 kHz 8 14 30 kΩ 200 500 800 kΩ RPP • Output n-channel transistors off • VIN = VSS, VDD = 5 V Ports with built-in pull-up resistor specifications Ru • VIN = VSS, VDD = 5 V RES See figure 5. tRST Cp 408 816 1020 4080 • f = 1 MHz • With all pins except the pin being tested at VIN = VSS. 10 pF Serial clock Input clock cycle time Output clock cycle time tCKCY(1) See figure 6. SCK tCKCY(2) See figure 6. tCKL(1) See figure 6. Output clock low-level pulse width tCKL(2) See figure 6. SCK Input clock high-level pulse width tCKH(1) See figure 6. SCK Output clock high-level pulse width tCKH(2) See figure 6. SCK Input clock low-level pulse width 2.0 SCK SCK µs 64 × µs TCYC*9 1.0 µs 32 × TCYC µs 1.0 µs 32 × TCYC µs Serial input Data setup time tICK Stipulated with respect to the SCK rising edge. SI 0.5 µs Data hold time tCKI See figure 6. SI 0.5 µs tCKO • Stipulated with respect to the SCK falling edge. • With external 1 kΩ resistors and 50 pF capacitors on the n-channel open-drain outputs only. • See figure 6. Serial output Output delay time SO 0.5 µs Continued on next page. No. 6498-15/39 LC651432N/F/L, 651431N/F/L Continued from preceding page. Parameter Symbol Pulse output Period tPCY High-level pulse width tPH Low-level pulse width tPL Conditions • See figure 7 Applicable pins Ratings min typ max Unit PE0 64 × TCYC µs PE0 • With external 1 kΩ resistors and external 50 pF capacitors on the nchannel open-drain outputs PE0 only. 32 × TCYC ±10% µs 32 × TCYC ±10% µs • TCYC = 4 × <system clock period> Notes: 1. Voltages up to the generated oscillation amplitude are allowed with internal drive using the oscillator circuit of figure 3 and the recommended circuit constants. 2. The average over a 100 ms period. 3. Applications must hold the operating supply voltage VDD level from the point a HALT instruction is executed until the IC enters the standby state. Also, switch bounce and similar noise must not appear on PA3 (or PA0 to 3) during the HALT instruction execution cycle. 4. The recommended circuit constants for which stable oscillation has been verified with the manufacturer of the oscillator element using the Sanyo specified oscillator characteristics evaluation board. 5. The OSC1 pin has Schmitt trigger characteristics when either 2-pin RC oscillator or external clock input is specified as the oscillator option. 6. The result of measurement when the recommended external circuit constants are used with the Sanyo characteristics evaluation board. The current due to the IC output transistors and pull-up resistor transistors is not included. 7. Indicates the frequency when fCFOSC is due to the use of the recommended circuit constants in table 1. 8. Indicates the required time for oscillation to stabilize starting from the point when VDD first exceeds the lower limit of the operating supply voltage range. (See figure 4.) 9. TCYC = 4 × <system clock period> No. 6498-16/39 LC651432N/F/L, 651431N/F/L OSC1 (OSC2) Open External clock VDD 0.8 VDD 0.2 VDD text text text VSS text text Figure 1 External Clock Input Waveform OSC1 OSC2 OSC2 OSC1 R Rext Cext C1 C2 Ceramic oscillator element Figure 2 Two-Pin RC Oscillator Circuit Figure 3 Ceramic Oscillator Circuit No. 6498-17/39 LC651432N/F/L, 651431N/F/L VDD Lower limit of the operating VDD range 0V OSC Oscillator stabilization time tCFS Stable oscillation Figure 4 Oscillator Stabilization Time Table 1 Ceramic Oscillator Recommended Circuit Constants 4 MHz (Murata Mfg. Co., Ltd.) C1 33 pF ±10% CSA4.00MG C2 33 pF ±10% CST4.00MGW (Built-in capacitor) R 0Ω 4 MHz (Kyocera Corporation) C1 33 pF ±10% KBR4.0MSB C2 33 pF ±10% KBR4.0MKC (Built-in capacitor) R 0Ω 1 MHz (Murata Mfg. Co., Ltd.) C1 100 pF ±10% CSB1000J C2 100 pF ±10% R 2.2 kΩ 800 kHz (Murata Mfg. Co., Ltd.) C1 100 pF ±10% CSB800J C2 100 pF ±10% R 2.2 kΩ 400 kHz (Murata Mfg. Co., Ltd.) C1 220 pF ±10% CSB400P C2 220 pF ±10% R 2.2 kΩ RES CRES ( = 0.1 µF) Figure 5 Reset Circuit Note: When the power supply rise time is effectively zero, the reset time for a CRES of 0.1 µF will be between 10 and 100 ms. If the power supply rise time is relatively long, increase the value of CRES so that the reset time is over 10 ms. No. 6498-18/39 LC651432N/F/L, 651431N/F/L tCKCY 0.8 VDD tCKL tCKH 0.2 VDD SCK tICK tCKI VDD Input data SI Load circuit 1 kΩ tCKO 50 pF Output data SO Figure 6 Serial I/O Timing tPCY tPH The load conditions are the same as those in figure 6. 0.7 VDD 0.25 VDD tPL Figure 7 Port PE0 Pulse Output Timing No. 6498-19/39 LC651432N/F/L, 651431N/F/L LC651431N and LC651432N RC Oscillator Characteristics Figure 8 shows the LC651431N and LC651432N RC oscillator characteristics. However, the LC651431N and LC651432N have the following RC oscillator frequency sample-to-sample variations. 1) VDD = 3.0 to 6.0 V, Ta = –40 to 85°C When the external circuit constants are: Cext = 220 pF, and Rext = 12 kΩ, the frequency range will be: 284 kHz ≤ fMOSC ≤ 790 kHz 2) VDD = 3.0 to 6.0 V, Ta = –40 to 85°C When the external circuit constants are: Cext = 220 pF, and Rext = 6.8 kΩ, the frequency range will be: 595 kHz ≤ fMOSC ≤ 1274 kHz Note that only the above circuit constants are guaranteed. If using other values for these constants is unavoidable, use values in the following ranges. Cext = 150 to 390 pF Rext = 3 to 20 kΩ (See figure 8.) Notes: 10. The oscillator frequency must be in the range 350 to 750 kHz when VDD = 5.0 V and Ta = 25°C. 11. Applications must assure adequate margins so that oscillator frequency falls in the operating clock frequency range (in the oscillator divider option table) for the ranges VDD = 3.0 to 6.0 V and Ta = –40 to 85°C. f MOSC–Rext 1.5 These characteristics curves are for reference purposes only. These characteristics are not guaranteed. f MOSC [kHz] C = 150p 1000 9 8 7 6 5 C = 270p 4 3 C = 390p 2 VDD = 5 (V) Ta = 25°C 1000 3 4 5 1 2 3 4 5 10 Rext [kΩ] Figure 8 RC Oscillator Frequency Data (representative values) No. 6498-20/39 LC651432N/F/L, 651431N/F/L LC651432F, 651431F Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Maximum supply voltage Output voltage Input voltage I/O voltage Symbol Conditions Applicable pins VDD max VO OSC2 Allowable power dissipation V Voltages up to the voltage generated are allowed. V VI(1) OSC1 *1 –0.3 to VDD +0.3 V TEST, RES –0.3 to VDD +0.3 V –0.3 to +15 V V VIO(1) Ports with open-drain specifications VIO(2) Ports with pull-up resistor specifications –0.3 to VDD +0.3 PI0 –0.3 to VDD +0.3 V I/O ports –2 to +20 mA Per single pin, the average over a 100 ms period I/O ports –2 to +20 mA ΣIOA(1) The total current for PC0 to 3, PD0 to 3, and PE0 to 3*2 PC0 to 3 PD0 to 3 PE0 to 3 –15 to +100 mA ΣIOA(2) The total current for PF0 to 3, PG0 to 3, PA0 to 3, and PI0*2 PF0 to 3, PI0 PG0 to 3 PA0 to 3 –15 to +100 mA Pd max(1) Ta = –40 to +85°C (DIP package) 310 mW Pd max(2) Ta = –40 to +85°C (MFP package) 220 mW Pd max(3) Ta = –40 to +85°C (SSOP package) 160 mW IOP IOA Average output current Unit –0.3 to +7.0 VI(2) VIO(3) Peak output current Ratings VDD Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to 125 °C Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V, VDD = 3.0 to 6.0 V (unless otherwise specified) Parameter Operating supply voltage Standby supply voltage High-level input voltage Symbol Conditions VDD Applicable pins Ratings min typ max Unit VDD 3.0 6.0 V VST RAM and register contents retained.*3 VDD 1.8 6.0 V VIH(1) With the n-channel output transistors off Ports with open-drain specifications (except for I0) 0.7 VDD 13.5 V VIH(2) With the n-channel output transistors off Ports with pull-up resistor specifications (except for I0) 0.7 VDD VDD V VIH(3) With the n-channel output transistors off Port I0 0.7 VDD VDD V VIH(4) With the n-channel output transistors off The INT, SCK, and SI pins with open-drain specifications 0.8 VDD 13.5 V VIH(5) With the n-channel output transistors off The INT, SCK, and SI pins with pull-up resistor specifications 0.8 VDD VDD V VIH(6) VDD = 1.8 to 6 V RES 0.8 VDD VDD V VIH(7) External clock specifications OSC1 0.8 VDD VDD V Continued on next page. No. 6498-21/39 LC651432N/F/L, 651431N/F/L Continued from preceding page. Parameter Symbol Applicable pins Ratings min typ max Unit VIL(1) With the n-channel output transistors off VDD = 4 to 6 V Port VSS 0.3 VDD V VIL(2) With the n-channel output transistors off 3 to 6 V Port VSS 0.25 VDD V VIL(3) With the n-channel output transistors off VDD = 4 to 6 V INT, SCK, SI VSS 0.25 VDD V VIL(4) With the n-channel output transistors off 3 to 6 V INT, SCK, SI VSS 0.2 VDD V VIL(5) External clock specifications VDD = 4 to 6 V OSC1 VSS 0.25 VDD V VIL(6) External clock specifications 3 to 6 V OSC1 VSS 0.2 VDD V Low-level input voltage Operating frequency (cycle time) Conditions VIL(7) VDD = 4 to 6 V TEST VSS 0.3 VDD V VIL(8) 3 to 6 V TEST VSS 0.25 VDD V VIL(9) VDD = 4 to 6 V RES VSS 0.25 VDD V VIL(10) 3 to 6 V RES VSS 0.2 VDD 200 (20) 4330 (0.92) kHz (µs) OSC1 200 4330 kHz 69 fop (Tcyc) V External clock conditions Frequency text Pulse width textH, textL See figure 1. OSC1 Rise and fall time textR, textF OSC1 Recommended oscillator circuit constants Ceramic oscillator*4 See figure 2. ns 50 ns See table 1. No. 6498-22/39 LC651432N/F/L, 651431N/F/L Electrical Characteristics at Ta = –40 to +85°C, VSS = 0 V, VDD = 3.0 to 6.0 V (unless otherwise specified) Parameter Conditions Applicable pins Open-drain specification ports (except I0) IIH(1) • With the output n-channel transistors off (Including the n-channel transistor off leakage current.) • VIN = 13.5 V The I0 port with open-drain specifications IIH(2) • With the output n-channel transistors off (Including the n-channel transistor off leakage current.) • VIN = VDD IIH(3) External clock mode VIN = VDD OSC1 IIL(1) • With the output n-channel transistors off • VIN = VSS Open-drain specification ports –1.0 IIL(2) • With the output n-channel transistors off • VIN = VSS Built-in pull-up resistor specification ports –1.3 –0.35 mA IIL(3) VIN = VSS RES –45 –10 µA IIL(4) External clock mode VIN = VSS OSC1 –1.0 µA VOH(1) • IOH = –50 µA Built-in pull-up resistor specification ports VDD – 1.2 V VOH(2) • IOH = –10 µA Built-in pull-up resistor specification ports VDD – 0.5 V VOL(1) • IOL = 10 mA Ports 1.5 V VOL(2) IOL = 1 mA, when IOL for all ports is less than or equal to 1 mA. Ports 0.5 V High-level input current Low-level input current High-level output voltage Low-level output voltage Schmitt characteristics Ratings Symbol Hysteresis voltage VHIS High-level threshold voltage VtH Low-level threshold voltage VtL min typ Unit max 5.0 µA 1.0 µA 1.0 µA µA V 0.1 VDD RES, INT, SCK, SI, and OSC1 with Schmitt trigger specifications*5 0.4 VDD 0.8 VDD V 0.2 VDD 0.6 VDD V Current drain*6 Ceramic oscillator External clock IDDOP(1) IDDOP(2) Standby mode IDDst • Figure 2, 4 MHz* • 200 to 4330 kHz* *: Operating, with the output n-channel transistors off, port voltage = VDD VDD 1.5 4 mA VDD 1 4 mA With the output n-channel transistors off, VDD = 6 V VDD 0.05 10 µA Port voltage = VDD, VDD = 3 V VDD 0.025 5 µA Continued on next page. No. 6498-23/39 LC651432N/F/L, 651431N/F/L Continued from preceding page. Parameter Symbol Conditions Applicable pins Ratings min typ 3920 4000 max Unit Oscillator characteristics • Figure 2, fo = 4 MHz*7 Ceramic oscillator Oscillator frequency Oscillator stabilization time*8 fCFOSC tCFS • Figure 3, fo = 4 MHz Built-in pull-up resistor I/O ports RES RPP • Output n-channel transistors off • VIN = VSS, VDD = 5 V Ports with built-in pull-up resistor specifications Ru • VIN = VSS, VDD = 5 V RES External reset characteristics Reset time Pin capacitance OSC1, OSC2 kHz 10 ms 8 14 30 kΩ 200 500 800 kΩ tRST Cp 4080 See figure 4. • f = 1 MHz • With all pins except the pin being tested at VIN = VSS. 10 pF Serial clock Input clock cycle time Output clock cycle time tCKCY(1) See figure 5. SCK tCKCY(2) See figure 5. tCKL(1) See figure 5. Output clock low-level pulse width tCKL(2) See figure 5. SCK Input clock high-level pulse width tCKH(1) See figure 5. SCK Output clock high-level pulse width tCKH(2) See figure 5. SCK Input clock low-level pulse width 2.0 SCK SCK µs 64 × µs TCYC*9 1.0 µs 32 × TCYC µs 1.0 µs 32 × TCYC µs Serial input Data setup time tICK Stipulated with respect to the SCK rising edge. SI 0.5 µs Data hold time tCKI See figure 5. SI 0.5 µs tCKO • Stipulated with respect to the SCK falling edge. • With external 1 kΩ resistors and 50 pF capacitors on the n-channel open-drain outputs only. • See figure 5 Serial output Output delay time SO 0.5 µs Pulse output Period tPCY High-level pulse width tPH Low-level pulse width tPL • See figure 6 • TCYC = 4 × <system clock period> • With external 1 kΩ resistors and external 50 pF capacitors on the n-channel open-drain outputs only. PE0 64 × TCYC µs PE0 32 × TCYC ±10% µs PE0 32 × TCYC ±10% µs Notes: 1. Voltages up to the generated oscillation amplitude are allowed with internal drive using the oscillator circuit of figure 2 and the recommended circuit constants. 2. The average over a 100 ms period. 3. Applications must hold the operating supply voltage VDD level from the point a HALT instruction is executed until the IC enters the standby state. Also, switch bounce and similar noise must not appear on PA3 (or PA0 to 3) during the HALT instruction execution cycle. 4. The recommended circuit constants for which stable oscillation has been verified with the manufacturer of the oscillator element using the Sanyo specified oscillator characteristics evaluation board. 5. The OSC1 pin has Schmitt trigger characteristics when external clock is specified as the oscillator option. 6. The result of measurement when the recommended external circuit constants are used with the Sanyo characteristics evaluation board. The current due to the IC output transistors and pull-up resistor transistors is not included. 7. Indicates the frequency when fCFOSC is due to the use of the recommended circuit constants in table 1. 8. Indicates the required time for oscillation to stabilize starting from the point when VDD first exceeds the lower limit of the operating supply voltage range. (See figure 3.) 9. TCYC = 4 × <system clock period> No. 6498-24/39 LC651432N/F/L, 651431N/F/L OSC1 (OSC2) Open External clock VDD 0.8 VDD 0.25 VDD text text text VSS text text Figure 1 External Clock Input Waveform OSC2 OSC1 R C1 C2 Ceramic oscillator element Figure 2 Ceramic Oscillator Circuit No. 6498-25/39 LC651432N/F/L, 651431N/F/L VDD Lower limit of the operating VDD range 0V OSC Oscillator stabilization time tCFS Stable oscillation Figure 3 Oscillator Stabilization Time Table 1 Ceramic Oscillator Recommended Circuit Constants 4 MHz (Murata Mfg. Co., Ltd.) C1 33 pF ±10% CSA4.00MG C2 33 pF ±10% CST4.00MGW (Built-in capacitor) R 0Ω 4 MHz (Kyocera Corporation) C1 33 pF ±10% KBR4.0MSB C2 33 pF ±10% KBR4.0MKC (Built-in capacitor) R 0Ω Sanyo is currently requesting evaluation of oscillator element products and recommended circuit constants from Kyocera Corporation for their products, and thus these recommendations are subject to change. Contact your Sanyo representative before using these devices. RES CRES ( = 0.1 µF) Figure 4 Reset Circuit Note: When the power supply rise time is effectively zero, the reset time for a CRES of 0.1 µF will be between 10 and 100 ms. If the power supply rise time is relatively long, increase the value of CRES so that the reset time is over 10 ms. No. 6498-26/39 LC651432N/F/L, 651431N/F/L tCKCY 0.8 VDD tCKL tCKH 0.25 VDD SCK tICK tCKI VDD Input data SI Load circuit 1 kΩ tCKO 50 pF Output data SO Figure 5 Serial I/O Timing tPCY tPH The load conditions are the same as those in figure 5. 0.7 VDD 0.3 VDD tPL Figure 6 Port PE0 Pulse Output Timing No. 6498-27/39 LC651432N/F/L, 651431N/F/L LC651432L, 651431L Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Maximum supply voltage Output voltage Input voltage I/O voltage Symbol Conditions Applicable pins VDD max VO OSC2 Allowable power dissipation V Voltages up to the voltage generated are allowed. V VI(1) OSC1 *1 –0.3 to VDD +0.3 V TEST, RES –0.3 to VDD +0.3 V –0.3 to +15 V V VIO(1) Ports with open-drain specifications VIO(2) Ports with pull-up resistor specifications –0.3 to VDD +0.3 PI0 –0.3 to VDD +0.3 V I/O ports –2 to +20 mA Per single pin, the average over a 100 ms period I/O ports –2 to +20 mA ΣIOA(1) The total current for PC0 to 3, PD0 to 3, and PE0 to 3*2 PC0 to 3 PD0 to 3 PE0 to 3 –15 to +100 mA ΣIOA(2) The total current for PF0 to 3, PG0 to 3, PA0 to 3, and PI0*2 PF0 to 3, PI0 PG0 to 3 PA0 to 3 –15 to +100 mA Pd max(1) Ta = –40 to +85°C (DIP package) 310 mW Pd max(2) Ta = –40 to +85°C (MFP package) 220 mW Pd max(3) Ta = –40 to +85°C (SSOP package) 160 mW IOP IOA Average output current Unit –0.3 to +7.0 VI(2) VIO(3) Peak output current Ratings VDD Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to 125 °C Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V, VDD = 2.2 to 6.0 V (unless otherwise specified) Parameter Operating supply voltage Standby supply voltage High-level input voltage Symbol Conditions VDD Applicable pins Ratings min typ max Unit VDD 2.2 6.0 V VST RAM and register contents retained. *2 VDD 1.8 6.0 V VIH(1) With the n-channel output transistors off Ports with open-drain specifications (except for I0) 0.7 VDD 13.5 V VIH(2) With the n-channel output transistors off Ports with pull-up resistor specifications (except for I0) 0.7 VDD VDD V VIH(3) With the n-channel output transistors off Port I0 0.7 VDD VDD V VIH(4) With the n-channel output transistors off The INT, SCK, and SI pins with open-drain specifications 0.8 VDD 13.5 V VIH(5) With the n-channel output transistors off The INT, SCK, and SI pins with pull-up resistor specifications 0.8 VDD VDD V VIH(6) VDD = 1.8 to 6 V RES 0.8 VDD VDD V VIH(7) External clock specifications OSC1 0.8 VDD VDD V VIL(1) With the n-channel output transistors off Ports VSS 0.2 VDD V VIL(2) With the n-channel output transistors off INT, SCK, SI VSS 0.2 VDD V VIL(3) External clock specifications Low-level input voltage OSC1 VSS 0.15 VDD V VIL(4) TEST VSS 0.22 VDD V VIL(5) RES VSS 0.15 VDD V Continued on next page. No. 6498-28/39 LC651432N/F/L, 651431N/F/L Continued from preceding page. Parameter Operating frequency (cycle time) External clock conditions Frequency Pulse width Rise and fall time Symbol fop (Tcyc) Conditions Applicable pins When the built-in divide-byfour circuit is selected, the clock frequency upper limit is 4.16 MHz. Figure 1. If the clock frequency exceeds 1.040 MHz, either the divide-bytextH, textL three or the divide-by-four divider circuit option must be textR, textF selected. text Ratings min typ max Unit 200 (20) 1040 (3.84) kHz (µs) OSC1 200 4160 kHz OSC1 120 ns OSC1 100 ns Recommended oscillator circuit constants Two-pin RC oscillator Cext See figure 2. Rext Ceramic oscillator*4 See figure 3. OSC1, OSC2 220 ± 5% pF 12 ±1% kΩ See table 1. No. 6498-29/39 LC651432N/F/L, 651431N/F/L Electrical Characteristics at Ta = –40 to +85°C, VSS = 0 V, VDD = 2.2 to 6.0 V (unless otherwise specified) Parameter Conditions Applicable pins Open-drain specification ports (except I0) IIH(1) • With the output n-channel transistors off (Including the n-channel transistor off leakage current.) • VIN = 13.5 V The I0 port with open-drain specifications IIH(2) • With the output n-channel transistors off (Including the n-channel transistor off leakage current.) • VIN = VDD IIH(3) External clock mode VIN = VDD OSC1 IIL(1) • With the output n-channel transistors off • VIN = VSS Open-drain specification ports –1.0 IIL(2) • With the output n-channel transistors off • VIN = VSS Built-in pull-up resistor specification ports –1.3 –0.35 mA IIL(3) VIN = VSS RES –45 –10 µA IIL(4) External clock mode VIN = VSS OSC1 –1.0 VOH High-level input current Low-level input current High-level output voltage Schmitt characteristics Low-level output voltage Ratings Symbol min typ Unit max 5.0 µA 1.0 µA 1.0 µA µA µA • IOH = –10 µA Built-in pull-up resistor VOL(1) • IOL = 3 mA Ports 1.5 V VOL(2) IOL = 1 mA, when IOL for all ports is less than or equal to 1 mA. Ports 0.4 V Hysteresis voltage VHIS High-level threshold voltage VtH Low-level threshold voltage VtL VDD – 0.5 V V 0.1 VDD RES, INT, SCK, SI, and OSC1 with Schmitt trigger specifications*5 0.4 VDD 0.8 VDD V 0.2 VDD 0.6 VDD V Current drain*6 Two-pin RC oscillator IDDOP(1) Ceramic oscillator External clock Standby mode IDDOP(2) IDDOP(3) • While operating, with the output n-channel transistors off • Port voltage = VDD • Figure 2, fosc = 400 kHz (typical) • Figure 3, 4 MHz, divideby-four circuit used. • Figure 3, 4 MHz, divideby-four circuit used. VDD = 2.2 V VDD 0.8 2.5 mA VDD 1 3 mA VDD 0.3 1 mA IDDOP(4) See figure 3. 400 kHz VDD 1 2.5 mA IDDOP(5) • 200 to 1024 kHz, no divider • 600 to 3120 kHz, divideby-three circuit used VDD • 800 to 4160 kHz, divideby-four circuit used 1.5 4 mA VDD 0.05 10 µA VDD 0.025 5 µA IDDst Output n-channel transistors off, VDD = 6 V Port voltage = VDD, VDD = 2.2 V Continued on next page. No. 6498-30/39 LC651432N/F/L, 651431N/F/L Continued from preceding page. Parameter Symbol Conditions Applicable pins Ratings min typ 392 3920 400 4000 max Unit Oscillator characteristics Ceramic oscillator Oscillator frequency fCFOSC*7 Oscillator stabilization time*8 tCFS Two-pin RC oscillator Oscillator frequency Built-in pull-up resistor I/O ports RES External reset characteristics Reset time Pin capacitance fMOSC • Figure 3, fo = 400 kHz • Figure 3, fo = 4 MHz, divide-by-four circuit used. OSC1, OSC2 OSC1, OSC2 • Figure 4, fo = 400 kHz • Figure 4, fo = 800 kHz, 1 MHz, or 4 MHz, divideby-four circuit used. • Figure 2, Cext = 220 pF ±5% OSC1, OSC2 • Figure 2, Rext = 12 kΩ ±1% RPP • Output n-channel transistors off • VIN = VSS, VDD = 5 V Ports with built-in pull-up resistor specifications Ru • VIN = VSS, VDD = 5 V RES kHz kHz 10 10 ms ms 200 400 790 kHz 8 14 30 kΩ 200 500 800 tRST Cp 408 4080 See figure 5. • f = 1 MHz • With all pins except the pin being tested at VIN = VSS. 10 pF Serial clock Input clock cycle time Output clock cycle time tCKCY(1) See figure 6. SCK tCKCY(2) See figure 6. tCKL(1) See figure 6. Output clock low-level pulse width tCKL(2) See figure 6. SCK Input clock high-level pulse width tCKH(1) See figure 6. SCK Output clock high-level pulse width tCKH(2) See figure 6. SCK Input clock low-level pulse width 12.0 SCK SCK µs 64 × µs TCYC*9 4.0 µs 32 × TCYC µs 4.0 µs 32 × TCYC µs Serial input Data setup time tICK Stipulated with respect to the SCK rising edge. SI 0.5 µs Data hold time tCKI See figure 6. SI 0.5 µs tCKO • Stipulated with respect to the SCK falling edge. • With external 1 kΩ resistors and 50 pF capacitors on the n-channel open-drain outputs only. • See figure 6 Serial output Output delay time Pulse output SO • See figure 7 Period tPCY High-level pulse width tPH Low-level pulse width tPL • TCYC = 4 × <system clock period> • With external 1 kΩ resistors and external 50 pF capacitors on the n-channel open-drain outputs only. 2.0 µs PE0 64 × TCYC µs PE0 32 × TCYC ±10% µs PE0 32 × TCYC ±10% µs No. 6498-31/39 LC651432N/F/L, 651431N/F/L Notes: 1. Voltages up to the generated oscillation amplitude are allowed with internal drive using the oscillator circuit of figure 3 and the recommended circuit constants. 2. The average over a 100 ms period. 3. Applications must hold the operating supply voltage VDD level from the point a HALT instruction is executed until the IC enters the standby state. Also, switch bounce and similar noise must not appear on PA3 (or PA0 to 3) during the HALT instruction execution cycle. 4. The recommended circuit constants for which stable oscillation has been verified with the manufacturer of the oscillator element using the Sanyo specified oscillator characteristics evaluation board. 5. The OSC1 pin has Schmitt trigger characteristics when either 2-pin RC oscillator or external clock input is specified as the oscillator option. 6. The result of measurement when the recommended external circuit constants are used with the Sanyo characteristics evaluation board. The current due to the IC output transistors and pull-up resistor transistors is not included. 7. Indicates the frequency when fCFOSC is due to the use of the recommended circuit constants in table 1. 8. Indicates the required time for oscillation to stabilize starting from the point when VDD first exceeds the lower limit of the operating supply voltage range. (See figure 4.) 9. TCYC = 4 × <system clock period> No. 6498-32/39 LC651432N/F/L, 651431N/F/L OSC1 (OSC2) Open External clock VDD 0.8 VDD 0.15 VDD text text text VSS text text Figure 1 External Clock Input Waveform OSC1 OSC1 OSC2 OSC2 R Rext Cext C1 C2 Ceramic oscillator element Figure 2 Two-Pin RC Oscillator Circuit Figure 3 Ceramic Oscillator Circuit No. 6498-33/39 LC651432N/F/L, 651431N/F/L VDD Lower limit of the operating VDD range 0V OSC Oscillator stabilization time tCFS Stable oscillation Figure 4 Oscillator Stabilization Time Table 1 Ceramic Oscillator Recommended Circuit Constants 4 MHz (Murata Mfg. Co., Ltd.) C1 33 pF ±10% CSA4.00MGU C2 33 pF ±10% CST4.00MGWU (Built-in capacitor) R 0Ω 400 kHz (Murata Mfg. Co., Ltd.) C1 330 pF ±10% CSB400P C2 330 pF ±10% R 3.3 kΩ RES CRES ( = 0.1 µF) Figure 5 Reset Circuit Note: When the power supply rise time is effectively zero, the reset time for a CRES of 0.1 µF will be between 10 and 100 ms. If the power supply rise time is relatively long, increase the value of CRES so that the reset time is over 10 ms. No. 6498-34/39 LC651432N/F/L, 651431N/F/L tCKCY tCKL 0.8 VDD tCKH 0.2 VDD SCK tICK tCKI VDD Input data SI Load circuit 1 kΩ tCKO 50 pF Output data SO Figure 6 Serial I/O Timing tPCY tPH The load conditions are the same as those in figure 6. 0.7 VDD 0.25 VDD tPL Figure 7 Port PE0 Pulse Output Timing No. 6498-35/39 LC651432N/F/L, 651431N/F/L LC651431L and LC651432L RC Oscillator Characteristics Figure 8 shows the LC651431L and LC651432L RC oscillator characteristics. However, the LC651431L and LC651432L have the following RC oscillator frequency sample-to-sample variations. VDD = 2.2 to 6.0 V, Ta = –40 to 85°C When the external circuit constants are: Cext = 220 pF, and Rext = 12 kΩ, the frequency range will be: 200 kHz ≤ fMOSC ≤ 790 kHz Note that only the above circuit constants are guaranteed. If using other values for these constants is unavoidable, use values in the following ranges. Cext = 150 to 390 pF Rext = 3 to 20 kΩ (See figure 8.) Notes: 10. The oscillator frequency must be in the range 350 to 500 kHz when VDD = 5.0 V and Ta = 25°C. 11. Applications must assure adequate margins so that oscillator frequency falls in the operating clock frequency range (in the oscillator divider option table) for the ranges VDD = 2.2 to 6.0 V and Ta = –40 to 85°C. f MOSC–Rext 1.5 These characteristics curves are for reference purposes only. These characteristics are not guaranteed. f MOSC [kHz] C = 150p 1000 9 8 7 6 5 C = 270p 4 3 C = 390p 2 VDD = 5 (V) Ta = 25°C 1000 3 4 5 1 2 3 4 5 10 Rext [kΩ] Figure 8 RC Oscillator Frequency Data (representative values) No. 6498-36/39 LC651432N/F/L, 651431N/F/L Notes on PCB Construction This section presents notes on noise as seen from the microcontroller itself and methods for reducing such noise when designing the printed circuit board for a mass-produced product using these microcontrollers. The design techniques presented here can be effective for preventing or avoiding problems (such as microcontroller malfunction and program runaway) due to noise. 1. VDD and VSS: Power supply pins Insert capacitors that meet the following conditions between the VDD and VSS pins. • For each of the capacitors C1 and C2, make the wiring lengths from the IC as close to equal as possible (L1 = L1’ and L2 = L2’), and keep these lines as short as possible as well. • Insert the capacitors C1, a large capacitor, and C2, a small capacitor, in parallel. • The VDD and VSS lines in the printed circuit board pattern should be wider than any other lines. L2 L1 C1 VSS C2 + VDD L1’ L2’ LVSS L1 VSS C1 L2 OSC1 C2 Rd OSC2 LOSC Figure 2-1 Oscillator Circuit Example 1 (ceramic oscillator) LVSS Lc 2. OSC1 and OSC2: Clock input and output pins When the ceramic oscillator option is selected (figure 2-1) • Keep the length (LOSC) of the connection lines between the clock I/O pins (input: OSC1, output: OSC2) and the external components as short as possible. • Keep the length (LVSS + L1 (L2)) from the VSS side of the capacitor connected to the oscillator element to the VSS pin as short as possible. • VSS line for the oscillator circuit and other VSS lines should branch from a point nearest to the VSS pin. • There are cases where the values of the oscillator circuit components (the capacitors C1 and C2, the limit resistor Rd, and other components) must be modified from the values recommended in this document to adjust the oscillator frequency. Consult with the oscillator element manufacturer when determining the component values. VSS Cext OSC1 Rext OSC2 When the 2-pin RC oscillator option is selected (figure 2-2) LOSC • Keep the length (LOSC) of the connection lines between the clock I/O pins (input: OSC1, output: OSC2) and the Figure 2-2 Oscillator Circuit Example 2 external components (the capacitor Cext and the resistor (2-pin RC oscillator) Rext) as short as possible. • Keep the length (LVSS + Lc) from the VSS side of the capacitor connected to the oscillator element to the VSS pin as short as possible. • VSS line for the oscillator circuit and other VSS lines should branch from a point nearest to the VSS pin. No. 6498-37/39 LC651432N/F/L, 651431N/F/L When the external oscillator option is selected (figure 2-3) • Keep the length (LOSC) of the line between the external oscillator and the IC clock input pin (OSC1) as short as possible. • Also keep the length (LOSC) of the lines between the external oscillator and the VDD and VSS used as short as possible. LOS VSS External oscillator OSC1 PI0 VDD Other common points: • Keep signals that change rapidly and large-amplitude signals connected to medium-voltage handling ports as far away from the oscillator circuit as possible and do not allow such lines to cross lines related to clock signals. Figure 2-3 Oscillator Circuit Example 3 (external oscillator) 3. RES: Reset pin • Keep the line from the external reset circuit to the RES pin as short as possible. • Keep the length (L1, L2) of the lines from the capacitor (Cres) inserted between RES and VSS as short as possible. L2 External circuit VSS Cres RES L1 Lres Figure 3 RES Pin Wiring 4. TEST: Test pin • Keep the line that connects the TEST pin to VSS as short as possible. • Take the line that connects the TEST pin to VSS from a location as close to the VSS pin as possible. VSS L TEST Figure 4 TEST Pin Wiring No. 6498-38/39 LC651432N/F/L, 651431N/F/L 5. I/O pins All of the pins on these microcontrollers are shared-function I/O pins. • When used as input pins, insert limiting resistors and keep the connection lines as short as possible. Supplement: This can be effective in preventing or avoiding microcontroller problems (such as malfunctions and program runaway), not only in printed circuit board design, but in selecting the microcontroller option types discussed below and when considering application program specifications. • If signals are input when the microcontroller power supply is unstable, select the medium-voltage (n-channel open drain) output as the output circuit type for that pin, and also insert a limiting resistor as close to the pin as possible. • Always adopt key bounce elimination techniques when inputting external signals to any microcontroller pin. • Periodically refresh the pin output data with an output instruction (OP or SPB). • When reading data input to a shared-function (bidirectional) I/O pin, set the value of the output data for that pin to 1 on every read operation with an output instruction (OP or SPB). 6. Unused pins • Refer to the pin functions table in the user’s manual for the product itself or in the relevant Sanyo Semiconductor Development Report. The information presented in this document consists of examples, and its use is not guaranteed in mass-produced end products. In actual product design (including the selection of circuit component values), we strongly recommend using the materials presented here as a reference and performing thorough evaluation and testing. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of April, 2000. Specifications and information herein are subject to change without notice. PS No. 6498-39/39