Ordering number : EN*5190 CMOS LSI LC651204N/F/L, LC651202N/F/L 4-Bit Single-Chip Microcontrollers for Small-Scale Control Applications Preliminary Overview The LC651204N/F/L and LC651202N/F/L are small-scale application microcontroller products in Sanyo's LC6500 series of 4-bit single-chip CMOS microcontrollers, and as such they fully support the basic architecture and instruction set of that series. These microcontrollers are provided in a 30-pin package and include 2 kilobytes (KB) and 4 KB of on-chip ROM. These products are appropriate for use in a wide range of applications, from applications that use a small number of controls and circuits that were previously implemented in standard logic to larger scale applications including audio equipment such as decks and players, office equipment, communications equipment, automotive equipment, and home appliances. Except for the lack of an A/D converter, these microcontrollers provide the same functionality as the LC651104, 02N/F/L. Features • • • • • • Fabricated in a CMOS process for low power (An instruction-controlled standby function is provided.) • ROM/RAM LC651204N/F/L - ROM: 4K × 8 bits, RAM: 256 × 4 bits LC651202N/F/L - ROM: 2K × 8 bits, RAM: 256 × 4 bits • Instruction set: The 80-instruction set provided by all members of the LC6500 series. • Wide operating power-supply voltage range of 2.5 to 5.5 volts (L version) • Instruction cycle time: 0.92 µs (F version) • On-chip serial I/O circuit • Highly flexible I/O ports — Number of ports: 6 ports with a total of 22 pins — All ports: Can be used for both input and output I/O voltage: 15 V maximum (Only for C, D, E, and F ports with opendrain output specifications) Output current:20 mA maximum sink current (Capable of directly driving LEDs.) — Options that allow specifications to be customized to match those of the application system. Specification of open-drain output or built-in pullup resistor: can be specified for all ports in bit units. • • Specification of the output level at reset: Can be specified to be high or low for ports C and D in port units. Interrupt functions — Timer overflow vector interrupt (The interrupt state can be tested by the CPU.) — Vector interrupts initiated by the INT pin or full/empty states of the serial I/O circuit. (The interrupt state can be tested by the CPU.) Stack levels: 8 levels (shared with interrupts) Timers: 4-bit prescaler plus 8-bit programmable timers Clock oscillator options to match application system specifications. — Oscillator circuit options: 2-pin ceramic oscillator (N, F, and L versions) — Divider circuit option: No divider, built-in divide-bythree circuit, built-in divide-by-four circuit (N and L versions) Supports continuous output of a square wave signal (with a period 64 times the cycle time) Watchdog timer — RC time constant scheme — A watchdog timer function can be allocated to one of the external pins as an option. EP version: LC65E1104, OTP version: LC65P1104 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 93096HA (OT) No. 5190-1/35 LC651204N/F/L, LC651202N/F/L Package Dimensions unit : mm 3196-DIP30SD unit : mm 3073A-MFP30S [LC651204N/F/L, 651202N/F/L] [LC651204N/F/L, 651202N/F/L] SANYO: DIP30SD SANYO: MFP30S Note: The package drawings shown above are provided without error tolerances and are for reference purposes only. Contact Sanyo for official package drawings. Function Overview Item Memory 2048 × 8 bits (1202N) 2048 × 8 bits (1202F) 2048 × 8 bits (1202L) 256 × 4 bits (1204/1202N) 256 × 4 bits (1204/1202F) 256 × 4 bits (1204/1202L) Table reference Timers Stack levels Standby function Number of ports Serial ports I/O voltage I/O ports Characteristics Output current Other functions 80 80 80 Supported Supported Supported 1 external, 1 internal 1 external, 1 internal 1 external, 1 internal 4-bit prescaler + 8-bit timer 4-bit prescaler + 8-bit timer 4-bit prescaler + 8-bit timer 8 8 8 Supports standby mode entered by the HALT instruction Supports standby mode entered by the HALT instruction Supports standby mode entered by the HALT instruction 22 I/O pins 22 I/O pins 22 I/O pins 4-bit or 8-bit I/O 4-bit or 8-bit I/O 4-bit or 8-bit I/O 15 V max. 15 V max. 15 V max. 10 mA typ. 20 mA max. 10 mA typ. 20 mA max. 10 mA typ. 20 mA max. I/O circuit types Open drain (n-channel) or built-in pull-up resistor output selectable on a per-bit basis. Output levels at reset High or low can be selected in port units. (ports C and D only) Square wave output Supported Supported Supported Minimum cycle time 2.77 µs (VDD ≥ 3 V) 0.92 µs (VDD ≥ 3 V) 3.84 µs (VDD ≥ 2.5 V) Power-supply voltage 3 to 5.5 V 3 to 5.5 V 2.5 to 5.5 V Power-supply current 1.5 mA typ. 2 mA typ. 1.5 mA typ. Ceramic (800 kHz, 1 MHz, 4 MHz) Ceramic (4 MHz) Ceramic (800 kHz, 1 MHz, 4 MHz) Oscillator Oscillator LC651204L/1202L 4096 × 8 bits (1204L) RAM Interrupts Built-in functions LC651204F/1202F 4096 × 8 bits (1204F) ROM Instruction set Instruction LC651204N/1202N 4096 × 8 bits (1204N) Divider circuit option Package 1/1, 1/3, 1/4 1/1 1/1, 1/3, 1/4 DIP30S-D MFP30S DIP30S-D MFP30S DIP30S-D MFP30S Note: Sanyo will announce details on oscillator elements and oscillator circuit constants as recommended application circuits are developed. Customers should check with Sanyo for the latest information as the development process progresses. No. 5190-2/35 LC651204N/F/L, LC651202N/F/L Pin Assignment Common assignments for the DIP and MFP packages Note: NC pins must be connected to VSS. Top view Pin Functions Pin Function OSC1, OSC2 Connections for a ceramic oscillator element RES Reset PA0 to 3 I/O dual-function port A0 to A3 PC0 to 3 I/O dual-function port C0 to C3 PD0 to 3 I/O dual-function port D0 to D3 PE0 to 1 I/O dual-function port E0 to E1 PF0 to 3 I/O dual-function port F0 to F3 PG0 to 3 I/O dual-function port G0 to G3 TEST Test INT Interrupt request SI Serial input SO Serial output SCK Serial clock input and output NC No connection WDR Watchdog reset Note: The SI, SO, SCK, and INT pins are shared function pins that are also used as PF0 to PF3. No. 5190-3/35 LC651204N/F/L, LC651202N/F/L System Block Diagram RAM: Data memory F: Flag WR: Working register AC: Accumulator ALU: Arithmetic and logic unit ROM: Program memory PC: Program counter INT: Interrupt control IR: Instruction register I.DEC: Instruction decoder DP: Data pointer CF, CSF: Carry flag, carry save flag E: E register ZF, ZSF: Zero flag, zero save flag CTL: Control register EXTF: External interrupt request flag OSC: Oscillator circuit TMF: Internal interrupt request flag TM: Timer STS: Status register No. 5190-4/35 LC651204N/F/L, LC651202N/F/L Development Support Sanyo provides the following items to support application development using the LC651204 and LC651202. 1. User’s manual The “LC651104/1102 User’s Manual” is used with these microcontrollers. 2. Development tool manual See the “EVA800 - LC651104/1102 Development Tool Manual” for details on use of the EVA-800 system. 3. Development tool • Program development (using the EVA-800 system) — MS-DOS host computer system *1 — Cross assembler ... MS-DOS-based cross assembler: LC65S.EXE — Evaluation chip: LC6595 — Emulator: The EVA-800 main unit plus the evaluation chip • Program development (using the EVA-86000 system): Use the EVA86K-ECB651100. • Program evaluation The <LC65E1104> on-chip EPROM microcontroller Development Support System EVA-800 System Note: 1. MS-DOS is a registered trademark of Microsoft Corporation 2. Here, “EVA-800” is a generic term for several emulators. Suffixes (A, B, etc.) will be attached to the name as new versions are developed. Note that the EVA-800 emulator (i.e., the model with no suffix) is an old version and cannot be used. No. 5190-5/35 LC651204N/F/L, LC651202N/F/L Pin Functions Pin Pin no. I/O VDD 1 — VSS 1 — OSC1 1 Input Function Power supply • System clock oscillator OSC2 1 Output Connect an external ceramic oscillator element to these pins • Leave OSC2 open if an external clock is supplied. Options State at reset Handling when unused — — — — — High-level output (i.e., the output n-channel transistor will be off.) Open drain output select the options, connect to VSS. • High-level output The same as PA0 to PA3. (1) External clock (2) Two-pin ceramic oscillator (3) Divider circuit option 1. No divider circuit 2. Divide-by-three circuit 3. Divide-by-four circuit • I/O port A0 to A3 Input in 4-bit units using the IP instruction Output in 4-bit units using the OP instruction (1) Output open drain (2) Built-in pull-up resistor • Options (1) and (2) can be specified in bit units. Port bits can be tested in bit units using the BP and BNP instructions. PA0 to PA3 4 I/O Port bits can be set or cleared in bit units using the SPB and RPB instructions. • PA3 is used for standby control. • Applications must be designed so that no chattering (e.g. switch bounce) occurs on the PA3 pin during a HALT instruction execution cycle. • I/O port C0 to C3 PC0 to PC3 4 I/O • I/O port D0 to D3 PD0 to PD3 4 I/O (1) Output open drain The PC0 to PC3 pin functions are (2) Built-in pull-up resistor identical to those of the PA0 to 3 pins.* (3) High-level output at reset • High or low can be specified as the (4) Low-level output at reset output at reset as an option. • Options (1) and (2) can be Note: These pins do not have a specified in bit units. standby control function. • Option (3) and (4) are specified in 4-bit units. The PD0 to PD3 pin functions and options are identical to those of the PC0 to PC3 pins. The same as PC0 to PC3. • Low-level output (Depending on the option specified.) The same as PC0 to PC3. The same as PA0 to PA3. Continued on next page. No. 5190-6/35 LC651204N/F/L, LC651202N/F/L Continued from preceding page. Pin Pin no. I/O Function • I/O port E0 to E1 Input in 4-bit units using the IP instruction Output in 4-bit units using the OP instruction PE0 to PE1 /WDR Port bits can be set or cleared in bit units using the SPB and RPB instructions. 2 I/O Options (1) Output open drain (2) Built-in pull-up resistor • Options (1) and (2) can be specified in bit units. State at reset Handling when unused High-level output (i.e., the output n-channel transistor will be off.) The same as PA0 to PA3. The same as PA0 to PA3. The same as PA0 to PA3. (3) Normal port PE1 (4) Watchdog timer reset WDR (5) (3) or (4) can be specified. Port bits can be tested in bit units using the BP and BNP instructions. • The PE0 pin also has a continuous pulse (64·Tcyc) output function. • The PE1 pin can be set to function as the WDR watchdog timer reset pin as an option. • I/O port F0 to F3 The same as PA0 to PA3. This port has the same functions and options as PE0 to PE1. * The serial port function is disabled. • The pins PF0 to PF3 are also used as the serial interface and the INT pin. PF1/SO PF2/SCK The interrupt source is INT. The function used can be selected under program control. PF0/SI 4 I/O SI ······Serial input port SO·····Serial output port PF3/INT SCK ··Serial clock input or output INT ····Interrupt request input Serial I/O can be switched between 4bit and 8-bit operation under program control. Note: This port does not provide a continuous pulse output function. • I/O port G0 to G3 PG0 to PG3 4 NC 2 I/O The same as PA0 to PA3. This port has the same functions and options as PE0 to PE1. * The same as PA0 to PA3. The same as PA0 to PA3. Note: This port does not provide a continuous pulse output function. • NC pin. This pin must be connected to VSS in the EP and OTP versions. — — — — — — Connect to VSS. • System reset input RES 1 Input TEST 1 Input • Connect an external capacitor for the power up reset. • A low level must be applied for at least four clock cycles for the reset startup sequence to operate correctly. • LSI test pin Must be connected to VSS. — Must be connected to VSS. No. 5190-7/35 LC651204N/F/L, LC651202N/F/L Oscillator Circuit Options Option Circuit Conditions and notes The OSC2 pin must be left open. External clock Ceramic oscillator Divider Options Option Circuit Conditions and notes • Supports both oscillator options. • The oscillator frequency or the external clock frequency must not exceed 1444 kHz (LC651204N and LC651202N) No divider (1/1) • The oscillator frequency or the external clock frequency must not exceed 4330 kHz (LC651204F and LC651202F) • The oscillator frequency or the external clock frequency must not exceed 1040 kHz (LC651204L and LC651202L) • Supports both oscillator options. • The oscillator frequency or the external clock frequency must not exceed 4330 kHz Built-in divide-by-three circuit • Supports both oscillator options. • The oscillator frequency or the external clock frequency must not exceed 4330 kHz Built-in divide-by-four circuit Caution: The oscillator and divider options are summarized in the following tables. The information presented in those tables is crucial when using these products. No. 5190-8/35 LC651204N/F/L, LC651202N/F/L Divider Options for the LC651204N/1202N, LC651204F/1202F, and LC651204L/1202L LC651204N, LC651202N Circuit type Frequency Divider option (cycle time) VDD range Notes 800 kHz 1/1 (5 µs) 3 to 5.5 V 1 MHz 1/1 (4µs) 3 to 5.5 V 4 MHz 1/3 (3µs) 1/4 (4µs) 3 to 5.5 V 3 to 5.5 V External clock generated by a two-terminal RC oscillator circuit 670 k to 1444 kHz 2000 k to 4330 kHz 2600 k to 4330 kHz 1/1 (6 to 2.77 µs) 1/3 (6 to 2.77 µs) 1/4 (6 to 3.70 µs) 3 to 5.5 V 3 to 5.5 V 3 to 5.5 V Use of an external clock with the ceramic oscillator option selected Driving the circuit with an external clock is not possible. To use external clock drive, specify the two-terminal RC oscillator option. Ceramic oscillator This frequency cannot be used with the 1/1 divider (i.e., no divider circuit) option. LC651204F, LC651202F Circuit type Frequency Divider option (cycle time) VDD range Notes Ceramic oscillator 4 MHz 1/1 (1 µs) 3 to 5.5 V External clock generated by a two-terminal RC oscillator circuit 670 k to 4330 kHz 1/1 (6 to 0.92 µs) 3 to 5.5 V Use of an external clock with the ceramic oscillator circuit Driving the circuit with an external clock is not possible. To use external clock drive, specify the two-terminal RC oscillator option. LC651204L LC651202L Circuit type Frequency Divider option (cycle time) VDD range Notes 800 kHz 1/1 (5 µs) 2.5 to 5.5 V 1 MHz 1/1 (4µs) 2.5 to 5.5 V 4 MHz 1/4 (4µs) 2.5 to 5.5 V External clock generated by a two-terminal RC oscillator circuit 670 k to 1040 kHz 2000 k to 3120 kHz 2600 k to 4160 kHz 1/1 (6 to 3.84 µs) 1/3 (6 to 3.84 µs) 1/4 (6 to 3.84 µs) 2.5 to 5.5 V 2.5 to 5.5 V 2.5 to 5.5 V Use of an external clock with the ceramic oscillator option selected Driving the circuit with an external clock is not possible. To use external clock drive, specify the two-terminal RC oscillator option. Ceramic oscillator This frequency cannot be used with the 1/1, 1/3 divider (i.e., no divider circuit) option. No. 5190-9/35 LC651204N/F/L, LC651202N/F/L Port C and D Output State at Reset Options The output levels at reset of the I/O ports C and D can be selected from the following two options, which are specified in 4-bit units. Option Conditions and notes High-level output at reset Ports C and D in 4-bit units Low-level output at reset Ports C and D in 4-bit units Port Output Circuit Type Option The output circuit types of the I/O ports can be selected from the following two options in bit units. Option Circuit Conditions and notes Ports A, C, D, E, F, and G Open drain output Pull-up resistor output Watchdog Timer Reset Option Whether the PE1/WDR pin functions as the normal port PE1 or as the WDR watchdog timer reset pin can be selected as an option. No. 5190-10/35 LC651204N/F/L, LC651202N/F/L LC651204N, 651202N Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Conditions Maximum supply voltage VDD max Output voltage Input voltage I/O voltage Peak output current Ratings Unit –0.3 to +7.0 V VO OSC2 Voltages up to any generated voltage are allowed. V VI (1) OSC1 *1 –0.3 to VDD +0.3 V VI (2) TEST, RES –0.3 to VDD +0.3 V VIO (1) PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3 OD specification ports –0.3 to + 15 V VIO (2) PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3 PU specification ports –0.3 to VDD +0.3 V VIO (3) PA0 to 3, PG0 to 3 IOP IOA Average output current Applicable pins/notes VDD –0.3 to VDD +0.3 –2 to +20 mA Average value per pin over a 100-ms period I/O ports –2 to +20 mA –15 to +100 mA –15 to +100 mA ΣI (1) Total current for pins PC0 to 3, PD0 to 3, and PE0 to 1*2 PC0 to PC3 PD0 to PD3 PE0 to PE1 ΣI (2) Total current for pins PF0 to 3, PG0 to 3, and PA0 to 3*2 PF0 to PF3 PG0 to PG3 PA0 to PA3 OA OA V I/O ports Allowable power Pd max (1) Ta = –40 to +85°C (DIP package) 250 mW dissipation Pd max (2) Ta = –40 to +85°C (MFP package) 150 mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C Allowable Operating Ranges at Ta = –40 to 85°C, VSS = 0 V, VDD = 3.0 to 5.5 V (unless otherwise specified) Parameter Symbol Operating power-supply voltage VDD Standby power-supply voltage VST Input high-level voltage Conditions Applicable pins/notes Ratings min typ max Unit VDD 3.0 5.5 V RAM and register values retained *3 VDD 1.8 5.5 V VIH (1) Output n-channel transistors off OD specification ports C, D, E, and F 0.7 VDD 13.5 V VIH (2) Output n-channel transistors off PU specification ports C, D, E, and F 0.7 VDD VDD V VIH (3) Output n-channel transistors off Port A, G 0.7 VDD VDD V VIH (4) Output n-channel transistors off The INT, SCK, and SI pins with OD specifications 0.8 VDD 13.5 V VIH (5) Output n-channel transistors off The INT, SCK, and SI pins with PU specifications 0.8 VDD VDD V VIH (6) VDD = 1.8 to 5.5 V RES 0.8 VDD VDD V VIH (7) External clock specifications OSC1 0.8 VDD VDD V Continued on next page. No. 5190-11/35 LC651204N/F/L, LC651202N/F/L Continued from preceding page. Parameter Input low-level voltage Operating frequency (cycle time) Symbol Conditions Rise and fall times Guaranteed oscillator constants Ceramic oscillator Ratings max Unit VIL (1) Output n-channel transistor off VDD = 4 to 5.5 V Port VSS 0.2VDD V VIL (2) Output n-channel transistor off VDD = 3 to 5.5 V Port VSS 0.2VDD V VIL (3) Output n-channel transistor off VDD = 4 to 5.5 V INT, SCk, SI VSS 0.2VDD V VIL (4) Output n-channel transistor off VDD = 3 to 5.5 V INT, SCk, SI VSS 0.2VDD V VIL (5) External clock specifications VDD = 4 to 5.5 V OSC1 VSS 0.2VDD V VIL (6) External clock specifications VDD = 3 to 5.5 V OSC1 VSS 0.2VDD V VIL (7) VDD = 4 to 5.5 V TEST VSS 0.2VDD V VIL (8) VDD = 3 to 5.5 V TEST VSS 0.2VDD V VIL (9) VDD = 4 to 5.5 V RES VSS 0.2VDD V VIL (10) VDD = 3 to 5.5 V RES VSS 0.2VDD V 670 (6) 1444 (2.77) kHz (µs) 670 4330 kHz fop (Tcyc) Frequencies up to 4.33 MHz are supported if the divide-bythree or divide-by-four divider circuit option is used. External clock conditions text Frequency Pulse width Applicable pins/notes Figure 1. The divide-by-three or divide-by-four divider circuit textH, textL option must be used if the clock frequency exceeds textR, textF 1.444 MHz. Figure 2 VDD = 3 to 5.5 V VDD = 3 to 5.5 V OSC1 VDD = 3 to 5.5 V OSC1 VDD = 3 to 5.5 V OSC1 min typ ns 69 50 ns See Table 1. No. 5190-12/35 LC651204N/F/L, LC651202N/F/L Electrical Characteristics at Ta = –40 to +85°C, VSS = 0 V, VDD = 3.0 to 5.5 V (unless otherwise specified) Parameter Symbol Schmitt characteristics Hysteresis voltage Ratings max Unit IIH (1) Ports C, D, E, and F with open-drain specifications 5.0 µA IIH (2) Output n-channel transistor off (Includes the n-channel transistor off leakage current.) VIN = VDD Ports A and G with open-drain specifications 1.0 µA IIH (3) External clock mode, VIN = VDD OSC1 1.0 µA IIL (1) Output n-channel transistor off VIN = VSS Ports with open-drain specifications –1.0 IIL (2) Output n-channel transistor off VIN = VSS Ports with pull-up resistor specifications –1.3 –0.35 mA IIL (3) VIN = VSS RES –45 –10 µA IIL (4) External clock mode, VIN = VSS OSC1 –1.0 VOH (1) IOH = –50 µA VDD = 4.0 to 5.5 V Ports with pull-up V –1.2 resistor specifications DD V VOH (2) IOH = –10 µA VDD = 3.0 to 5.5 V Ports with pull-up V –0.5 resistor specifications DD V VOL (1) IOL = 10 mA, VDD = 4.0 to 5.5 V Port 1.5 V VOL (2) IOL = 1 mA, with the IOL for all ports no more than 1 mA. VDD = 3.0 to 5.5 V Port 0.5 V Output high-level voltage Output low-level voltage Applicable pins/notes Output n-channel transistor off (Includes the n-channel transistor off leakage current.) VIN = 13.5 V Input high-level current Input low-level current Conditions min VtH Low-level threshold voltage VtL µA µA 0.1 VDD VHIS High-level threshold voltage typ RES, INT, SCK, 0.4 VDD and SI OSC1 with Schmitt specifications 0.2 VDD *4 V 0.8 VDD V 0.6 VDD V Current drain IDDOP (1) Operating, output n-channel transistors off, Ports = VDD Figure 2, 4 MHz, divide-by-three circuit VDD 1.5 5 mA Ceramic oscillator IDDOP (2) Figure 2, 4 MHz, divide-by-four circuit VDD 1.5 4 mA IDDOP (3) Figure 2, 800 kHz VDD 1.5 4 mA External clock IDDOP (4) 670 to 1444 kHz, no divider circuit 2000 to 4330 kHz, divide-by-three circuit 2600 to 4330 kHz, divide-by-four circuit VDD 1.5 5 mA Standby mode IDDst Output n-channel transistor off, VDD = 5.5 V Ports = VDD, VDD = 3 V VDD VDD 0.05 0.025 10 5 µA µA Continued on next page. No. 5190-13/35 LC651204N/F/L, LC651202N/F/L Continued from preceding page. Parameter Symbol Conditions Applicable pins/notes Ratings min typ max Unit 768 960 3840 800 1000 4000 832 1040 4160 kHz kHz kHz 5 ms Oscillator characteristics Figure 2, fo = 800 kHz Figure 2, fo = 1 MHz Figure 2, fo = 4 MHz, divide-by-three or divide-by-four circuit OSC1, OSC2 OSC1, OSC2 OSC1, OSC2 Ceramic oscillator Oscillator frequency fCFOSC *5 Oscillator stabilization time tCFS Figure 3, fo = 800 kHz, 1 MHz, 4 MHz Divide-by-three or divide-by-four circuit Pull-up resistors I/O ports RPP Output n-channel transistor off Vin = VSS, VDD = 5 V Ports with pull-up resistor specifications RES Ru Vin = VSS, VDD = 5 V RES 8 14 30 kΩ 100 250 400 kΩ External reset characteristics See Figure 4. Reset time tRST Pin capacitance Cp f = 1 MHz With all pins other than the pin being measured at VIN = VSS Serial clock Input clock cycle time tCKCY (1) Figure 5 SCK Output clock cycle time tCKCY (2) Figure 5 SCK Input clock low-level pulse width tCKL (1) Figure 5 SCK Output clock low-level pulse width tCKL (2) Figure 5 SCK Input clock high-level pulse width tCKH (1) Figure 5 SCK Output clock high-level pulse width tCKH (2) Figure 5 SCK 10 3.0 pF µs 64×TCYC *6 1.0 µs µs 32×TCYC 1.0 µs µs 32×TCYC µs Continued on next page. No. 5190-14/35 LC651204N/F/L, LC651202N/F/L Continued from preceding page. Parameter Symbol Conditions VDD (v) Applicable pins/notes Ratings min typ max Unit Serial input Data setup time tICK Stipulated with respect to the rising edge of SCK. SI 0.4 µs Data hold time tCKI Figure 5 SI 0.4 µs tCKO Stipulated with respect to the falling edge of SCK. For n-channel open-drain outputs only: External resistance: 1 kΩ, external capacitance: 50 pF Figure 5 Serial output Output delay time Pulse output Period High-level pulse width Low-level pulse width Guaranteed constants *7 tPCY tPL Figure 6 Tcyc = 4 x the system clock period For n-channel open-drain outputs only: External resistance: 1 kΩ, external capacitance: 50 pF CW When PE1 has open-drain output specifications RW When PE1 has open-drain output specifications tPH Watchdog timer Rl When PE1 has open-drain output specifications SO 0.6 64 × TCYC PE0 µs 32 × TCYC ±10% 32 × TCYC ±10% PE0 PE0 µs µs µs WDR 0.1±5% µF WDR 680±1% kΩ WDR 100±1% Ω 3 to 5.5 Clear time (discharge) tWCT See Figure 7. WDR 100 µs Clear period (charge) tWCCY See Figure 7. WDR 29 ms CW When PE1 has open-drain output specifications WDR 0.047±5% µF RW When PE1 has open-drain output specifications WDR 680±1% kΩ WDR 100±1% Ω Guaranteed constants *7 Rl Clear time (discharge) tWCT Clear period (charge) tWCCY When PE1 has open-drain output specifications 4 to 5.5 See Figure 7. WDR 40 µs See Figure 7. WDR 15 ms Note: 1. When driven internally using the oscillator circuit shown in Figure 3 with guaranteed constants, values up to the amplitude of the generated oscillation are allowed. 2. The average over a 100-ms period 3. The operating power-supply voltage VDD must be maintained from the point where a HALT instruction is executed until the point where the device has fully entered the standby state. Also, applications must be designed so that no chattering (e.g. switch bounce) occurs on the PA3 pin during a HALT instruction execution cycle. 4. When external clock is selected as the oscillator option, the OSC1 pin has Schmitt characteristics. 5. The values shown for fCFOSC are the frequencies for which oscillation is possible. The center frequency when a ceramic oscillator is used may differ by about 1% from the nominal value listed by the manufacturer of the ceramic oscillator element. See the specifications of the ceramic oscillator element for details. 6. Tcyc = 4 × the system clock period 7. If this device is used in an environment subject to condensation, extra care is required concerning leakage between PE1 and adjacent pins and leakage associated with external capacitors. No. 5190-15/35 LC651204N/F/L, LC651202N/F/L Figure 1 External Clock Input Waveform Figure 2 Ceramic Oscillator Circuit No. 5190-16/35 LC651204N/F/L, LC651202N/F/L Figure 3 Oscillator Stabilization Period Table 1: Guaranteed Ceramic Oscillator Constants 4 MHz (Murata Mfg. Co., Ltd.) CSA4.00MG CST4.00MGW (built-in capacitor version) 4 MHz (Kyocera Corporation) KBR4.0MSA KBR4.0MKS (built-in capacitor version) 1 MHz (Murata Mfg. Co., Ltd.) CSB1000J 1 MHz (Kyocera Corporation) KBR1000F 800 kHz (Murata Mfg. Co., Ltd.) CSB800J 800 kHz (Kyocera Corporation) KBR800F C1 33 pF ± 10% C2 33 pF ± 10% R 0Ω C1 33 pF ± 10% C2 33 pF ± 10% R 0Ω C1 100 pF ± 10% C2 100 pF ± 10% R 2.2 kΩ C1 100 pF ± 10% C2 100 pF ± 10% R 0Ω C1 100 pF ± 10% C2 100 pF ± 10% R 2.2 kΩ C1 220 pF ± 10% C2 220 pF ± 10% R 0Ω Figure 4 Reset Circuit Note: When the power supply rise time is zero, the reset time with CRES = 0.1 µF will be between 5 and 50 ms. If the power supply rise time is comparatively long, increase the value of CRES so that the reset time is over 5 ms. No. 5190-17/35 LC651204N/F/L, LC651202N/F/L Figure 5 Serial I/O Timing With load conditions identical to those shown in Figure 5 Figure 6 Port PE0 Pulse Output Timing tWCCY: Charge time due to the external components CW, RW, and Rl. tWCT: Discharge time due to program processing Figure 7 Watchdog Timer Waveform No. 5190-18/35 LC651204N/F/L, LC651202N/F/L LC651204F, 651202F Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Conditions Maximum supply voltage VDD max Output voltage Input voltage I/O voltage Peak output current Applicable pins/notes Ratings Unit VDD –0.3 to +7.0 V VO OSC2 Voltages up to any generated voltage are allowed. V VI (1) OSC1 *1 –0.3 to VDD +0.3 V VI (2) TEST, RES –0.3 to VDD +0.3 V VIO (1) PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3 OD specification ports –0.3 to + 15 V VIO (2) PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3 PU specification ports –0.3 to VDD +0.3 V VIO (3) PA0 to 3, PG0 to 3 IOP –0.3 to VDD +0.3 V I/O ports –2 to +20 mA Average value per pin over a 100-ms period I/O ports –2 to +20 mA Σ IOA (1) Total current for pins PC0 to 3, PD0 to 3, and PE0 to 1 *2 PC0 to 3 PD0 to 3 PE0 to 1 –15 to +100 mA Σ IOA (2) Total current for pins PF0 to 3, PG0 to 3, and PA0 to 3*2 PF0 to 3 PG0 to 3 PA0 to 3 –15 to +100 mA IOA Average output current Allowable power dissipation Pd max (1) Ta = –40 to +85°C (DIP package) 250 mW Pd max (2) Ta = –40 to +85°C (MFP package) 150 mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V, VDD = 3.0 to 5.5 V (unless otherwise specified) Parameter Symbol Operating power-supply voltage VDD Standby power-supply voltage VST Input high-level voltage Input low-level voltage Conditions Applicable pins/notes Ratings min typ max Unit VDD 3.0 5.5 V RAM and register values retained *3 VDD 1.8 5.5 V VIH (1) Output n-channel transistors off OD specification ports C, D, E, and F 0.7 VDD 13.5 V VIH (2) Output n-channel transistors off PU specification ports C, D, E, and F 0.7 VDD VDD V VIH (3) Output n-channel transistors off Port A, G 0.7 VDD VDD V VIH (4) Output n-channel transistors off The INT, SCK, and SI pins with OD specifications 0.8 VDD 13.5 V VIH (5) Output n-channel transistors off The INT, SCK, and SI pins with PU specifications 0.8 VDD VDD V VIH (6) VDD = 1.8 to 5.5 V RES 0.8 VDD VDD V VIH (7) External clock specifications OSC1 0.8 VDD VDD V VIL (1) Output n-channel transistors off Port VSS 0.2 VDD V VIL (2) Output n-channel transistors off INT, SCK, SI VSS 0.2 VDD V VIL (3) External clock specifications OSC1 VSS 0.2 VDD V VIL (4) TEST VSS 0.2 VDD V VIL (5) RES VSS 0.2 VDD V Continued on next page. No. 5190-19/35 LC651204N/F/L, LC651202N/F/L Continued from preceding page. Parameter Operating frequency (cycle time) Symbol Conditions Applicable pins/notes fop (T cyc) Ratings min typ max Unit 670 (6) 4330 (0.97) kHz (µs) 4330 kHz External clock conditions Frequency text OSC1 670 Pulse width textH, textL Figure 1 OSC1 69 Rise and fall times textR, textF OSC1 Guaranteed oscillator constants Ceramic oscillator ns 50 Figure 2 ns See table 1. Electrical Characteristics at Ta = –40 to +85°C, VSS = 0 V, VDD = 3.0 to 5.5 V (unless otherwise specified) Parameter Symbol Schmitt characteristics Hysteresis voltage Ratings max Unit IIH (1) Ports C, D, E, and F with open-drain specifications 5.0 µA IIH (2) Output n-channel transistor off (Includes the n-channel transistor off leakage current.) VIN = VDD Ports A and G with open-drain specifications 1.0 µA IIH (3) External clock mode, VIN = VDD OSC1 1.0 µA IIL (1) Output n-channel transistor off VIN = VSS Ports with open-drain specifications –1.0 IIL (2) Output n-channel transistor off VIN = VSS Ports with pull-up resistor specifications –1.3 –0.35 mA IIL (3) VIN = VSS RES –45 –10 µA IIL (4) External clock mode, VIN = VSS OSC1 –1.0 VOH (1) IOH = –50 µA Ports with pull-up V –1.2 resistor specifications DD V VOH (2) IOH = –10 µA Ports with pull-up V –0.5 resistor specifications DD V VOL (1) IOL = 10 mA Port 1.5 V IOL = 1 mA, with the IOL for all ports no more than Port 0.5 V Output high-level voltage Output low-level voltage Applicable pins/notes Output n-channel transistor off (Includes the n-channel transistor off leakage current.) VIN = 13.5 V Input high-level current Input low-level current Conditions VOL (2) min VtH Low-level threshold voltage VtL µA µA 1 mA. VHIS High-level threshold voltage typ 0.1 VDD RES, INT, SCK, 0.4 VDD and SI OSC1 with Schmitt specifications *4 0.25VDD V 0.8 VDD V 0.6 VDD V Current drain Ceramic oscillator IDDOP (1) Figure 2, 4 MHz VDD 2 6 mA External clock IDDOP (2) 670 to 1444 kHz *1 Operating, output n-channel transistors off, Ports = VDD VDD 2 6 mA Standby mode IDDst Output n-channel transistor off, VDD = 5.5 V Ports = VDD VDD = 3 V VDD 0.05 10 µA VDD 0.025 5 µA Continued on next page. No. 5190-20/35 LC651204N/F/L, LC651202N/F/L Continued from preceding page. Parameter Symbol Conditions Applicable pins/notes Ratings min typ max Unit 3840 4000 4160 kHz 5 ms Oscillator characteristics Ceramic oscillator Oscillator frequency fCFOSC Figure 2, fo = 4 MHz *5 Oscillator stabilization time tCFS Figure 3, fo = 4 MHz I/O ports RPP Vin = VSS, VDD = 5 V Ports with pull-up resistor specifications RES Ru Vin = VSS, VDD = 5 V RES Pull-up resistors OSC1, OSC2 Output n-channel transistor off 8 14 30 kΩ 100 250 400 kΩ External reset characteristics Reset time tRST Pin capacitance Cp f = 1 MHz With all pins other than the pin being measured at VIN = VSS Serial clock Input clock cycle time tCKCY (1) Figure 5 SCK tCKCY (2) Figure 5 SCK Input clock low-level pulse width tCKL (1) Figure 5 SCK Output clock low-level pulse width tCKL (2) Figure 5 SCK Input clock high-level pulse width tCKH (1) Figure 5 SCK Output clock high-level pulse width tCKH (2) Figure 5 SCK Serial input Data setup time tICK Stipulated with respect to the rising edge of SCK. SI 0.2 µs Data hold time tCKI Figure 5 SI 0.2 µs Serial output Output delay time tCKO Stipulated with respect to the falling edge of SCK. For n-channel open-drain outputs only. External SO resistance: 1 kΩ, external capacitance: 50 pF. Figure 5 Pulse output Period tPCY Figure 6 PE0 64 × TCYC µs High-level pulse width tPH Tcyc = 4 × the system clock period For n-channel open-drain outputs only: External resistance: 1 kΩ, external capacitance: 50 pF PE0 32 × TCYC ±10% µs Low-level pulse width tPL PE0 32 × TCYC ±10% µs Output clock cycle time See Figure 4. 10 pF 2.0 µs 64 × TCYC *6 µs 0.6 µs 32 × TCYC µs 0.6 µs 32 × TCYC µs 0.4 µs Continued on next page. No. 5190-21/35 LC651204N/F/L, LC651202N/F/L Continued from preceding page. Parameter Guaranteed constants *7 Symbol CW When PE1 has open-drain output specifications RW When PE1 has open-drain output specifications Watchdog timer VDD (v) Applicable pins/notes Ratings min typ max Unit WDR 0.01±5% µF WDR 680±1% kΩ When PE1 has open-drain output specifications WDR 100±1% Ω See Figure 7. WDR 10 µs See Figure 7. WDR 3.0 ms CW When PE1 has open-drain output specifications WDR 0.01±5% µF RW When PE1 has open-drain output specifications WDR 680±1% kΩ Rl When PE1 has open-drain output specifications WDR 100±1% Ω Rl Clear time (discharge) tWCT Clear period (charge) tWCCY Guaranteed constants *7 Conditions 3 to 5.5 4.5 to 5.5 Clear time (discharge) tWCT See Figure 7. WDR 10 µs Clear period (charge) tWCCY See Figure 7. WDR 3.3 ms Note: 1. When driven internally using the oscillator circuit shown in Figure 2 with guaranteed constants, values up to the amplitude of the generated oscillation are allowed. 2. The average over a 100-ms period 3. The operating power-supply voltage VDD must be maintained from the point where a HALT instruction is executed until the point where the device has fully entered the standby state. Also, applications must be designed so that no chattering (e.g. switch bounce) occurs on the PA3 pin during a HALT instruction execution cycle. 4. When external clock is selected as the oscillator option, the OSC1 pin has Schmitt characteristics. 5. The values shown for fCFOSC are the frequencies for which oscillation is possible. 6. Tcyc = 4 × the system clock period 7. If this device is used in an environment subject to condensation, extra care is required concerning leakage between PE1 and adjacent pins and leakage associated with external capacitors. No. 5190-22/35 LC651204N/F/L, LC651202N/F/L Figure 1 External Clock Input Waveform Figure 2 Ceramic Oscillator Circuit Figure 3 Oscillator Stabilization Period Table 1: Guaranteed Ceramic Oscillator Constants 4 MHz (Murata Mfg. Co., Ltd.) CSA4.00MG CST4.00MGW (built-in capacitor version) 4 MHz (Kyocera Corporation) KBR4.0MSA KBR4.0MKS (built-in capacitor version) C1 33 pF ± 10% C2 33 pF ± 10% R 0Ω C1 33 pF ± 10% C2 33 pF ± 10% R 0Ω Figure 4 Reset Circuit Note: When the power supply rise time is zero, the reset time with CRES = 0.1 µF will be between 5 and 50 ms. If the power supply rise time is comparatively long, increase the value of CRES so that the reset time is over 5 ms. No. 5190-23/35 LC651204N/F/L, LC651202N/F/L Figure 5 Serial I/O Timing With load conditions identical to those shown in Figure 5 Figure 6 Port PE0 Pulse Output Timing tWCCY: Charge time due to the external components CW, RW, and Rl. tWCT: Discharge time due to program processing Figure 7 Watchdog Timer Waveform No. 5190-24/35 LC651204N/F/L, LC651202N/F/L LC651204L, 651202L Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Conditions Maximum supply voltage VDD max Output voltage Input voltage I/O voltage Peak output current Applicable pins/notes Ratings Unit VDD –0.3 to +7.0 V VO OSC2 Voltages up to any generated voltage are allowed. V VI (1) OSC1*1 –0.3 to VDD +0.3 V VI (2) TEST, RES –0.3 to VDD +0.3 V VIO (1) PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3 OD specification ports –0.3 to + 15 V VIO (2) PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3 PU specification ports –0.3 to VDD +0.3 V VIO (3) PA0 to 3, PG0 to 3 IOP –0.3 to VDD +0.3 V I/O ports –2 to +20 mA Average value per pin over a 100-ms period I/O ports –2 to +20 mA Σ IOA (1) Total current for pins PC0 to 3, PD0 to 3, and PE0 to 1 *2 PC0 to 3 PD0 to 3 PE0 to 1 –15 to +100 mA Σ IOA (2) Total current for pins PF0 to 3, PG0 to 3, and PA0 to 3 *2 PF0 to 3 PG0 to 3 PA0 to 3 –15 to +100 mA IOA Average output current Allowable power dissipation Pd max (1) Ta = –40 to +85°C (DIP package) 250 mW Pd max (2) Ta = –40 to +85°C (MFP package) 150 mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V, VDD = 2.5 to 5.5 V (unless otherwise specified) Parameter Symbol Operating power-supply voltage VDD Standby power-supply voltage VST Input high-level voltage Input low-level voltage Conditions Applicable pins/notes Ratings min typ max Unit VDD 2.5 5.5 V RAM and register values retained *3 VDD 1.8 5.5 V VIH (1) Output n-channel transistors off OD specification ports C, D, E, and F 0.7 VDD 13.5 V VIH (2) Output n-channel transistors off PU specification ports C, D, E, and F 0.7 VDD VDD V VIH (3) Output n-channel transistors off Port A, G 0.7 VDD VDD V VIH (4) Output n-channel transistors off The INT, SCK, and SI pins with OD specifications 0.8 VDD 13.5 V VIH (5) Output n-channel transistors off The INT, SCK, and SI pins with PU specifications 0.8 VDD VDD V VIH (6) VDD = 1.8 to 5.5 V RES 0.8 VDD VDD V VIH (7) External clock specifications OSC1 0.8 VDD VDD V VIL (1) Output n-channel transistors off Port VSS 0.2 VDD V VIL (2) Output n-channel transistors off INT, SCK, SI VSS 0.15 VDD V VIL (3) External clock specifications OSC1 VSS 0.15 VDD V VIL (4) TEST VSS 0.2 VDD V VIL (5) RES VSS 0.15 VDD V No. 5190-25/35 LC651204N/F/L, LC651202N/F/L Continued from preceding page. Parameter Operating frequency (cycle time) Symbol fop (Tcyc) Conditions Frequencies up to 4.16 MHz are supported if the divide-by-four divider circuit option is used. External clock conditions Figure 1. The divide-by- three or divide-by-four Frequency text divider circuit option must be used if the clock Pulse width textH, textL frequency exceeds 1.040 MHz. Rise and fall times textR, textF Guaranteed oscillator constants Ceramic oscillator Applicable pins/notes OSC1 OSC1 OSC1 Ratings min typ max Unit 670 (6) 1040 (3.84) kHz (µs) 670 150 4160 kHz ns ns 100 Figure 2 See table 1. Electrical Characteristics at Ta = –40 to +85°C, VSS = 0 V, VDD = 2.5 to 5.5 V (unless otherwise specified) Parameter Symbol Schmitt characteristics Hysteresis voltage Ratings max Unit IIH (1) Ports C, D, E, and F with open drain specifications 5.0 µA IIH (2) Output n-channel transistor off (Includes the n-channel transistor off leakage current.) VIN = VDD Ports A and G with open drain specifications 1.0 µA IIH (3) External clock mode, VIN = VDD OSC1 1.0 µA IIL (1) Output n-channel transistor off VIN = VSS Ports with open drain specifications –1.0 IIL (2) Output n-channel transistor off VIN = VSS Ports with pull-up resistor specifications –1.3 –0.35 mA IIL (3) VIN = VSS RES –45 –10 µA IIL (4) External clock mode, VIN = VSS OSC1 –1.0 IOH = –10 µA Ports with pull-up V –0.5 resistor specifications DD VOL (1) IOL = 3 mA Port 1.5 V VOL (2) IOL = 1 mA, with the IOL for all ports no more than 1 mA. Port 0.4 V Output high-level voltage VOH (1) Output low-level voltage Applicable pins/notes Output n-channel transistor off (Includes the n-channel transistor off leakage current.) VIN = 13.5 V Input high-level current Input low-level current Conditions min VHIS High-level threshold voltage VtH Low-level threshold voltage VtL typ µA µA V 0.1 VDD RES, INT, SCK, 0.4 VDD and SI OSC1 with Schmitt specifications *4 0.2 VDD V 0.8 VDD V 0.6 VDD V Continued on next page. No. 5190-26/35 LC651204N/F/L, LC651202N/F/L Continued from preceding page. Parameter Symbol Current drain Conditions Applicable pins/notes Ratings min typ max Unit VDD 1.5 4 mA IDDOP (1) Operating, output n-channel transistors off, Ports = VDD Figure 2, 4 MHz, divide-by-four circuit IDDOP (2) Figure 2, 4 MHz, divide-by-four circuit VDD = 2.5 V VDD 0.5 1 mA IDDOP (3) Figure 2, 800 kHz VDD 1.5 4.0 mA External clock IDDOP (4) 670 to 1024 kHz, no divider circuit 2000 to 3120 kHz, divide-by-three circuit 2600 to 4160 kHz, divide-by-four circuit VDD 1.5 4 mA Standby mode IDDst Output n-channel transistor off, VDD = 5.5 V Ports = VDD VDD = 2.5 V VDD 0.05 10 µA VDD 0.020 4 µA Figure 2, fo = 800 kHz Figure 2, fo = 1 MHz Figure 2, fo = 4 MHz, divide-by-four circuit OSC1, OSC2 OSC1, OSC2 OSC1, OSC2 800 1000 4000 832 1040 4160 kHz kHz kHz 5 ms Ceramic oscillator Oscillator characteristics Ceramic oscillator Oscillator frequency fCFOSC *5 Oscillator stabilization time tCFS Figure 3, fo = 800 kHz, 1 MHz, 4 MHz, divide-by-four circuit Pull-up resistors I/O ports RPP Output n-channel transistor off Vin = VSS, VDD = 5 V Ports with pull-up resistor specifications RES Ru Vin = VSS, VDD = 5 V RES 768 960 3840 8 14 30 kΩ 100 250 400 kΩ External reset characteristics Reset time tRST Pin capacitance Cp See Figure 4. f = 1 MHz With all pins other than the pin being measured at VIN = VSS 10 pF Continued on next page. No. 5190-27/35 LC651204N/F/L, LC651202N/F/L Continued from preceding page. Parameter Symbol Conditions Applicable pins/notes Ratings min typ max Unit Serial clock Input clock cycle time tCKCY (1) Figure 5 SCK Output clock cycle time tCKCY (2) Figure 5 SCK Input clock low-level pulse width tCKL (1) Figure 5 SCK Output clock low-level pulse width tCKL (2) Figure 5 SCK Input clock high-level pulse width tCKH (1) Figure 5 SCK Output clock high-level pulse width tCKH (2) Figure 5 SCK Data setup time tICK Stipulated with respect to the rising edge of SCK. SI 0.5 µs Data hold time tCKI Figure 5 SI 0.5 µs 6.0 µs 64 × TCYC *6 µs 2.0 µs 32 × TCYC µs 2.0 µs 32 × TCYC µs Serial input Serial output Stipulated with respect to the falling edge of SCK. Output delay time tCKO For n-channel open-drain outputs only: External SO resistance: 1 kΩ, external capacitance: 50 pF. Figure 5 Pulse output period tPCY Figure 6 PE0 64 × TCYC µs High-level pulse width tPH Tcyc = 4 × the system clock period For n-channel open-drain outputs only: External resistance: 1 kΩ, external capacitance: 50 pF PE0 32 × TCYC ±10% µs Low-level pulse width tPL PE0 32 × TCYC ±10% µs 1.0 µs Continued on next page. No. 5190-28/35 LC651204N/F/L, LC651202N/F/L Continued from preceding page. Parameter Guaranteed constants *7 Symbol CW When PE1 has open-drain output specifications RW When PE1 has open-drain output specifications Watchdog timer VDD (v) Applicable pins/notes Ratings min typ max Unit WDR 0.1±5% µF WDR 680±1% kΩ When PE1 has open-drain output specifications WDR 100±1% Ω See Figure 7. WDR 100 µs See Figure 7. WDR 26 ms CW When PE1 has open-drain output specifications WDR 0.047±5% µF RW When PE1 has open-drain output specifications WDR 680±1% kΩ Rl When PE1 has open-drain output specifications WDR 100±1% Ω Rl Clear time (discharge) tWCT Clear period (charge) tWCCY Guaranteed constants *7 Conditions 2.5 to 5.5 2.5 to 5.5 Clear time (discharge) tWCT See Figure 7. WDR 40 µs Clear period (charge) tWCCY See Figure 7. WDR 12 ms Note: 1. When driven internally using the oscillator circuit shown in Figure 2 with guaranteed constants, values up to the amplitude of the generated oscillation are allowed. 2. The average over a 100-ms period 3. The operating power-supply voltage VDD must be maintained from the point where a HALT instruction is executed until the point where the device has fully entered the standby state. Also, applications must be designed so that no chattering (e.g. switch bounce) occurs on the PA3 pin during a HALT instruction execution cycle. 4. When external clock is selected as the oscillator option, the OSC1 pin has Schmitt characteristics. 5. The values shown for fCFOSC are the frequencies for which oscillation is possible. 6. Tcyc = 4 × the system clock period 7. If this device is used in an environment subject to condensation, extra care is required concerning leakage between PE1 and adjacent pins and leakage associated with external capacitors. No. 5190-29/35 LC651204N/F/L, LC651202N/F/L Figure 1 External Clock Input Waveform Figure 2 Ceramic Oscillator Circuit Figure 3 Oscillator Stabilization Period No. 5190-30/35 LC651204N/F/L, LC651202N/F/L Table 1: Guaranteed Ceramic Oscillator Constants 4 MHz (Murata Mfg. Co., Ltd.) CSA4.00MGU CST4.0MGWU (built-in capacitor version) 1 MHz (Murata Mfg. Co., Ltd.) CSB1000J 1 MHz (Kyocera Corporation) KBR1000F 800 kHz (Murata Mfg. Co., Ltd.) CSB800J 800 kHz (Kyocera Corporation) KBR800F C1 33 pF ± 10% C2 33 pF ± 10% R 0Ω C1 100 pF ± 10% C2 100 pF ± 10% R 2.2 kΩ C1 100 pF ± 10% C2 100 pF ± 10% R 0Ω C1 100 pF ± 10% C2 100 pF ± 10% R 2.2 kΩ C1 220 pF ± 10% C2 220 pF ± 10% R 0Ω Figure 4 Reset Circuit Note: When the power supply rise time is zero, the reset time with CRES = 0.1 µF will be between 5 and 50 ms. If the power supply rise time is comparatively long, increase the value of CRES so that the reset time is over 5 ms. Figure 5 Serial I/O Timing With load conditions identical to those shown in Figure 5 Figure 6 Port PE0 Pulse Output Timing No. 5190-31/35 LC651204N/F/L, LC651202N/F/L tWCCY: Charge time due to the external components CW, RW, and Rl tWCT: Discharge time due to program processing Figure 7 Watchdog Timer Waveform No. 5190-32/35 LC651204N/F/L, LC651202N/F/L LC651204/1202 Instruction Set (by function) Abbreviations D7 D6 D5 D4 D3 D2 D1 D0 Number of cycles Accumulator manipulation instructions Memory manipulation instructions Arithmetic and comparison instructions Load and store instructions M: Memory ZF : M(DP): Memory addressed by DP ( )[ ] : P(DPL): I/O port specified by DPL ← : PC: Program counter + : STACK: Stack pointer – : TM: Timer ^ : TMF: Timer (internal) interrupt request flag ∨ : At, Ha, La: Working registers ∨ : Number of bytes Accumulator Accumulator bit t Carry flag Control register Data pointer E register External interrupt request flag Flag bit n Instruction group AC: ACt: CF: CTL: DP: E: EXTF: Fn: 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Instruction code Mnemonic Operation RAL Rotate AC left through CF 0 0 0 0 0 0 0 1 1 1 TAE XAE INM DEm Transfer AC to E Exchange AC with E Increment M Decrement M 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 AC ← 0 CF ← 0 CF ← 1 AC ← (AC) AC ← (AC) + 1 AC ← (AC) – 1 AC0 ← (CF), ACn+1 ← (ACn), CF ← (AC3) E ← (AC) (AC) ↔ (E) M(DP) ← [M(DP)] + 1 M(DP) ← [M(DP)] – 1 SmB bit Set M data bit 0 0 0 0 1 0 B1 B0 1 1 M(DP, B1 B0) ← 1 RMB bit Reset M data bit 0 0 1 0 1 0 B1 B0 1 1 M(DP, B1 B0) ← 0 AD Add M to AC 0 1 1 0 0 0 0 0 1 1 AC ← (AC) + [M(DP)] ADC Add M to AC with CF 0 0 1 0 0 0 0 0 1 1 AC ← (AC) + [M(DP)] + (CF) DAA DAS Decimal adjust AC in addition Decimal adjust AC in subtraction 1 1 1 1 1 1 0 0 0 1 1 0 1 1 0 0 1 1 1 1 AC ← (AC) + 3 AC ← (AC) + 10 EXL Exclusive or M to AC 1 1 1 1 0 1 0 1 1 1 AC ← (AC) ∨ [M(DP)] AND And M to AC 1 1 1 0 0 1 1 1 1 1 AC ← (AC) ^ [M(DP)] OR Or M to AC 1 1 1 0 0 1 0 1 1 1 AC ← (AC) ∨ [M(DP)] CM Compare AC with M 1 1 1 1 1 0 1 1 1 1 [M(DP)] + (AC) + 1 CLA ClC STC CMA INC DEC Clear AC Clear CF Set CF Complement AC Increment AC Decrement AC 1 1 1 1 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 0 1 1 1 0 1 Zero flag Indicates the contents of the item enclosed. Transfer and direction Addition Subtraction Logical AND Logical OR Logical exclusive OR Description Modified status flags Clears AC. Clears CF. Sets CF. Sets AC to the one's Increments AC. Decrements AC. ZF ZF ZF ZF CF CF Shifts AC together with CF left. ZF CF ZF CF CF ZF ZF ZF Cl data Compare AC with immediate data 0 0 0 1 1 0 0 0 1 I3 1 I2 0 I1 0 I0 2 2 I3 I2 I1 I0 + (AC) + 1 CLI data Compare DPL with immediate data 0 0 0 1 1 0 0 1 1 I3 1 I2 0 I1 0 I0 2 2 (DPL) ∨ I3 I2 I1 I0 LI data Load AC with immediate data 1 1 0 0 I3 I2 I1 I0 1 1 AC ← I3 I2 I1 I0 S L Store AC to M Load AC from M 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 1 1 1 M(DP) ← (AC) AC ← [M(DP)] XM data Exchange AC with M then modify DPH with immediate data 1 0 1 0 0 1 2 (AC) ↔ [M(DP)] DPH ← (DPH) ∨ 0 M2 M1 M0 X Exchange AC with M 1 0 1 0 0 0 0 0 1 2 (AC) ↔ [M(DP)] Exchanges the contents of AC and M(DP). XI Exchange AC with M then increment DPL 1 1 1 1 1 1 1 0 1 2 (AC) ↔ [M(DP)] DPL ← (DPL) + 1 XD Exchange AC with M then Decrement DPL 1 1 1 1 1 1 1 1 1 2 (AC) ↔ [M(DP)] DPL ← (DPL) – 1 RTBl Read table data from program ROM 0 1 1 0 0 0 1 1 1 2 AC, E ↔ ROM (PCh, E, AC) Exchanges the contents of AC and M(DP). Then, increments ZF the contents of DPL. Exchanges the contents of AC and M(DP). Then, Decrements ZF the contents of DPL. Loads into AC and E the ROM data stored at the location given by the lower 8 bits of the PC, E and AC. M 2 M1 M0 CF CF ZF ZF ZF Compares the contents of AC and the immediate data I3 I2 I1 I0 and sets or clears CF and ZF accordingly. Magnitude relationship CF ZF ZF I3 I2 I1 I0 > (AC) 0 0 I3 I2 I1 I0 = (AC) 1 1 I3 I2 I1 I0 < (AC) 1 0 Compares the contents of DPL and the immediate data. Loads AC with the immediate data I3 I2 I1 I0. Stores the contents of AC at M(DP). Loads the contents of M(DP) into AC. Exchanges the contents of AC and M(DP). Then, replaces the contents of DPH with (DPH) ∨ 0 M2 M1 M0. *1 CF CF Moves the contents of AC to E. Exchanges the contents of AC and E. Increments M(DP). ZF Decrements M(DP). ZF Sets the bit in M(DP) specified by B1B0 to 1. Clears the bit in M(DP) specified by B1B0 to 0. Adds the contents of AC and M(DP) as two's complement quantities and stores the result ZF in AC. Adds the contents of AC, CF, and M(DP) as two's complement quantities and stores the result in AC. Adds 6 to AC. Adds 10 to AC. Takes the logical exclusive OR of AC and M(DP) and stores the result in AC. Takes the logical AND of AC and M(DP) and stores the result in AC. Takes the logical OR of AC and M(DP) and stores the result in AC. Compares the contents of AC and M(DP) and sets or clears CF and ZF accordingly. Magnitude relationship CF ZF [M(DP)] > (AC) 0 0 [M(DP)] = (AC) 1 1 [M(DP)] < (AC) 1 0 Notes CF CF ZF ZF *1 ZF ZF ZF ZF is set to indicate the result of the (DPH) ∨ 0 M2 M1 M0 operation. ZF is set according to the contents of DPH at the point the instruction was executed. ZF is set to indicate the result of the DPL +1 operation. ZF is set to indicate the result of the DPL –1 operation. Continued on next page. No. 5190-33/35 LC651204N/F/L, LC651202N/F/L Memory manipulation instructions Jump and subroutine instructions D3 D2 D1 D0 Number of cycles 1 0 0 0 I3 I2 I1 I0 1 1 DPH ← 0 DPL ← I3 I2 I1 I0 Loads 0 into DPH and the immediate data I3I2I1I0 into DPL. 0 1 0 0 I3 I2 I1 I0 1 1 DPH ← I3 I2 I1 I0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 1 0 1 1 1 1 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 DPL ← (DPL) + 1 DPL ← (DPL) – 1 DPL ← (AC) AC ← (DPL) 0 0 1 0 0 0 1 1 1 1 (AC) ↔ (DPH) t0 0 1 0 1 a 0 1 a 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 (AC) ↔ (A0) (AC) ↔ (A1) (AC) ↔ (A2) (AC) ↔ (A3) Loads the immediate data I3 I2 I1 I0 into DPH. Increments the contents of DPL. ZF Decrements the contents of DPL. ZF Moves the contents of AC to DPL. Moves the contents of DPL to AC. ZF Exchanges the contents of AC and DPH. Exchanges the contents of AC and the working register A0, A1, A2, or A3 specified by t1t0. 0 0 0 0 1 1 1 1 (DPH) ↔ (H0) (DPH) ↔ (H1) 0 0 Instruction code Mnemonic IND DED TAL TLA Load DPH with Zero and DPL with immediate data respectively Load DPH with immediate data Increment DPL Decrement DPL Transfer AC to DPL Transfer DPL to AC XAH Exchange AC with DPH LDZ data LHI data XAt XA0 XA1 XA2 XA3 XHa XH0 XH1 XLa XL0 XL1 SFB flag Branch instructions D7 D6 D5 D4 Number of bytes Working register manipulation instructions Data pointer manipulation instructions Instruction group Continued from preceding page. Modified Operation 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 Exchange DPH with working register Ha 1 1 1 1 1 1 1 1 1 1 Exchange DPH with working register Ha 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 (DPL) ↔ (L0) (DPL) ↔ (L1) Set flag bit 0 1 0 1 B3 B2 B1 B0 1 1 Fn ← 1 RFB flag Reset flag bit JMP addr Jumping in the current bank 0 0 0 1 0 1 1 B3 B2 B1 B0 0 1 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 1 Fn ← 0 2 2 PC ← P10 P9 P8 P7 P6 Jumps to the location specified P5 P4 P3 P2 P1 P0 by the immediate data P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0. PC0 to 7 ← (E, AC) Jumping current page modified by E and AC 1 1 1 1 1 0 1 1 CZP addr Call subroutine in the zero page 1 0 1 1 P3 P2 P1 P0 1 1 CAL addr RT Call subroutine Return from subroutine 1 0 0 1 1 1 0 0 1 P10 P9 P8 0 0 1 0 2 1 2 1 RTI Return from interrupt routine 0 0 1 0 0 0 1 0 1 1 BANK Change bank 1 1 1 1 1 1 0 1 1 1 BAt addr Change bank 0 1 1 1 P7 P6 P5 P4 0 0 t1 t0 P3 P2 P1 P0 2 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if ACt = 1 BNAt addr Branch on no AC bit 0 0 1 1 P7 P6 P5 P4 0 0 t1 t0 P3 P2 P1 P0 2 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if ACt = 0 BMt addr Branch on M bit 0 1 1 1 P7 P6 P5 P4 0 1 t1 t0 P3 P2 P1 P0 2 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if [M(DP, t1 t0)] = 1 BNMt addr Branch on no M bit 0 0 1 1 P7 P6 P5 P4 0 1 t1 t0 P3 P2 P1 P0 2 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if [M(DP, t1 t0)] = 0 BPt addr Branch on Port bit 0 1 1 1 P7 P6 P5 P4 1 0 t1 t0 P3 P2 P1 P0 2 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if [P(DPL, t1 t0)] = 1 BNPt addr Branch on no Port bit 0 0 1 1 P7 P6 P5 P4 1 0 t1 t0 P3 P2 P1 P0 2 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if [P(DPL, t1 t0)] = 0 BTM addr Branch on timer 0 1 1 1 P7 P6 P5 P4 1 0 0 0 P3 P2 P1 P0 2 2 1 Exchanges the contents of DPH and the working register H0 or H1 specified by a. Exchanges the contents of DPL and the working register L0 or L1 specified by a. Sets the flag specified by B3 B2 B1 B0 to 1. Clears the flag specified by B3 B2 B1 B0 to 0. 1 JPEA 0 status Notes flags t1 0 0 1 1 Exchange AC with working register At Description STACK ← (PC) + 1 PC10 to 6 , PC1 to 0 ← 0 PC5 to 2 ← P3 P2 P1 P0 STACK ← (PC) + 2 PC ← (STACK) PC ← (STACK) CF, ZF ← CSF, ZSF PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if TMF = 0 then TMF ← 0 The flags are divided into four groups, F0 to F3, F4 to F7, F8 to F11, and F12 to F15. ZF is set or cleared according to the 4 bits included in the specified flags. ZF Jumps to the location given by replacing the lower 8 bits of the PC with E and AC. Calls a subroutine on page 0. Calls a subroutine. Returns from a subroutine. Returns from an interrupt handling routine. Specifies a pseudo I/O port and changes the bank. ZF CF Only valid for the immediately following JMP, I/O, or branch instruction. Branches to the location on the same page specified by P7 to P0 if the bit in AC specified by the immediate data t1t0 is 1. Branches to the location on the same page specified by P7 to P0 if the bit in AC specified by the immediate data t1t0 is 0. Branches to the location on the same page specified by P7 to P0 if the bit in M(DP) specified by the immediate data t1 t0 is 1. Branches to the location on the same page specified by P7 to P0 if the bit in M(DP) specified by the immediate data t1 t0 is 0. Branches to the location on the same page specified by P7 to P0 if the bit in port P(DPL) specified by the immediate data t1 t0 is 1. Branches to the location on the same page specified by P7 to P0 if the bit in port P(DPL) specified by the immediate data t1 t0 is 0. Branches to the location on the same page specified by P7 to P0 TMF if TMF is 1. Also clears TMF. The mnemonics are BA0 to BA3, reflecting the value of t. The mnemonics are BNA0 to BNA3, reflecting the value of t. The mnemonics are BM0 to BM3, reflecting the value of t. The mnemonics are BNM0 to BNM3, reflecting the value of t. The mnemonics are BP0 to BP3, reflecting the value of t. The mnemonics are BNP0 to BNP3, reflecting the value of t. Continued on next page. No. 5190-34/35 LC651204N/F/L, LC651202N/F/L Number of cycles BNTM addr Branch on no timer 0 0 1 1 P7 P6 P5 P4 1 1 0 0 P3 P2 P1 P0 2 2 BI addr Branch on interrupt 0 1 1 1 P7 P6 P5 P4 1 1 0 1 P3 P2 P1 P0 2 2 BNI addr Branch on no interrupt 0 0 1 1 P7 P6 P5 P4 1 1 0 1 P3 P2 P1 P0 2 2 BC addr Branch on CF 0 1 1 1 P7 P6 P5 P4 1 1 1 1 P3 P2 P1 P0 2 2 BNC addr Branch on no CF 0 0 1 1 P7 P6 P5 P4 1 1 1 1 P3 P2 P1 P0 2 2 BZ addr Branch on ZF 0 1 1 1 P7 P6 P5 P4 1 1 1 0 P3 P2 P1 P0 2 2 BNZ addr Branch on no ZF 0 0 1 1 P7 P6 P5 P4 1 1 1 0 P3 P2 P1 P0 2 2 BFn addr Branch on flag bit 1 1 0 1 P7 P6 P5 P4 n3 n 2 n 1 n 0 P3 P2 P1 P0 2 2 BNFn addr Branch on no flag bit 1 0 0 1 P7 P6 P5 P4 n3 n 2 n 1 n 0 P3 P2 P1 P0 2 2 IP Input port to AC 0 0 0 0 1 1 0 0 1 1 OP Output port to AC 0 1 1 0 0 0 0 1 1 1 SPB bit Set port bit 0 0 0 0 0 1 B1 B0 1 2 Branches to the location on the same page specified by P7 to P0 if CF is 1. Branches to the location on the same page specified by P7 to P0 if CF is 0. Branches to the location on the same page specified by P7 to P0 if ZF is 1. Branches to the location on the same page specified by P7 to P0 if ZF is 0. Branches to the location on the same page specified by P7 to P0 if the bit in the 16 flags specified by n3 n2 n1 n0 is 1. Branches to the location on the PC7 to 0 ← P7 P6 P5 P4 same page specified by P to P 7 0 P7 P6 P5 P4 if the bit in the 16 flags specified if Fn = 0 by n3 n2 n1 n0 iis 0. Inputs the contents of port ZF AC ← [P(DPL)] P(DPL) to AC. Outputs the contents of AC to P(DPL, B1 B0) ← (AC) port P(DP ). L Sets to 1 the bit in port P(DPL) specified by the immediate data P(DPL, B1 B0) ← 1 B1 B0. RPB bit Reset port bit 0 0 1 0 0 1 B1 B0 1 2 P(DPL, B1 B0) ← 1 SCTL bit Set control register bit (S) 0 0 1 0 1 1 0 0 2 2 CTL ← (CTL) ∨ B3 B2 B1 B0 RCTL bit Reset control register bit (S) 0 1 0 0 1 0 0 1 1 1 0 0 B3 B2 B1 B0 2 2 CTL ← (CTL) ∨ B3 B2 B1 B0 WTTM Write timer 1 1 1 1 1 0 1 1 1 1 TM ← (E), (AC) TMF ← 0 HALT Halt 1 1 1 1 0 1 1 0 1 1 Halt NOP No operation 0 0 0 0 0 0 0 0 1 1 No operation Other instructions I/O instructions Branch instructions Instruction group Number of bytes Continued from preceding page. Instruction code Mnemonic D7 D6 D5 D4 D3 D2 D1 D0 Modified Operation Description status Notes flags PC7 to 0 ← P7 P6 P5 P4 P7 P6 P5 P4 if TMF = 0 then TMF ← 0 PC7 to 0 ← P7 P6 P5 P4 P7 P6 P5 P4 if EXTF = 1 then EXTF ← 0 PC7 to 0 ← P7 P6 P5 P4 P7 P6 P5 P4 if EXTF = 0 then EXTF ← 0 PC7 to 0 ← P7 P6 P5 P4 P7 P6 P5 P4 if EXTF = 0 PC7 to 0 ← P7 P6 P5 P4 P7 P6 P5 P4 if CF = 0 PC7 to 0 ← P7 P6 P5 P4 P7 P6 P5 P4 if ZF = 1 PC7 to 0 ← P7 P6 P5 P4 P7 P6 P5 P4 if ZF = 0 PC7 to 0 ← P7 P6 P5 P4 P7 P6 P5 P4 if Fn = 1 Branches to the location on the same page specified by P7 to P0 TMF if TMF is 0. Also clears TMF. Branches to the location on the same page specified by P7 to P0 if EXTF is 1. Also clears EXTF. EXTF Branches to the location on the same page specified by P7 to P0 if EXTF is 0. Also clears EXTF. EXTF Clears to 0 the bit in port P(DPL) specified by the immediate data B1 B0. ZF Sets the bit (or bits) in the control register specified by B3 B2 B1 B0. Clears the bit (or bits) in the control register specified by B3 ZF B2 B1 B0. Loads the contents of E and AC into the timer. Also clears TMF. TMF Stops all operations. The mnemonics are BF0 to BF15, reflecting the value of n. The mnemonics are BFN0 to BFN15, reflecting the value of n. Executing this instruction destroys the contents of the E register. Executing this instruction destroys the contents of the E register. This instruction is disabled only when all bits in port PA are 0. Consumes one machine cycle while performing no operation. ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 1997. Specifications and information herein are subject to change without notice. No. 5190-35/35