Ordering number : EN*4247A CMOS LSI LC74730M On-Screen Display Controller LSI Preliminary Overview Package Dimensions The LC74730M is a CMOS LSI for on-screen display, a function that displays characters and patterns on a TV screen under microprocessor control. (The LC74730M supports the S-VCR format.) The characters displayed have an 8 × 8 dots structure and a dot interpolation function is provided. The LC74730M display 10 lines of 24 characters each. unit: mm 3073A-MFP30S [LC74730M] Features • Screen format: 10 lines × 24 characters (up to 240 characters) • Character format: 8 (horizontal) × 8 (vertical) (interpolation function provided) • Character sizes: Three horizontal sizes and 3 vertical sizes • Number of characters in font: 64 characters • Display start position — Horizontal: 64 positions — Vertical: 64 positions • Blinking: In character units • Types of blinking: Two types with approximately 1.0 sec. and 0.5 sec. • Background color: Four background colors (in internal synchronization mode) (For the PAL-M format: 1 color; blue background) • External control input: 8-bit serial data input format • Built-in sync separator circuit • Built-in synchronization recognition circuit: Recognizes whether or not external synchronizing signals are present • Video output: NTSC and PAL-M format composite outputs, Y-C output SANYO: MFP30S SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN D3095HA (OT) No. 4247-1/14 LC74730M Pin Assignment Specifications Absolute Maximum Ratings at Ta = 25°C Ratings Unit Maximum supply voltage Parameter VDD max Symbol VDD1, VDD2 VSS – 0.3 to VSS + 7.0 V Maximum input voltage VIN max All input pins VSS – 0.3 to VDD + 0.3 V CSYNOUT, SYNCJDG, SEPOUT VSS – 0.3 to VDD + 0.3 Maximum output voltage VOUT max Allowable power dissipation Conditions Pd max 300 V mW Operating temperature Topr –30 to +70 °C Storage temperature Tstg –40 to +125 °C max Unit Allowable Operating Ranges at Ta = –30 to +70°C Parameter Supply voltage Input high-level voltage Input low-level voltage Composite video input voltage Input voltage Oscillator frequency Symbol Conditions min typ VDD1 VDD1 4.5 5.0 5.5 V VDD2 VDD2 4.5 5.0 1.27 VDD1 V VIH1 RST, CS, SIN, SCLK 0.8 VDD1 VDD1 + 0.3 V VIH2 CTRL1 to CTRL3, SEPIN 0.7 VDD1 VDD1 + 0.3 V VIL1 RST, CS, SIN, SCLK VSS – 0.3 0.2 VDD1 V VIL2 CTRL1 to CTRL3, SEPIN VSS – 0.3 0.3 VDD1 V VIN1 CVIN 2 Vp-p VIN2 SYNIN 2 Vp-p VIN3 The XtalIN oscillator pin (in external clock input mode) Expected value (design target value) fOSC1 The XtalIN and XtalOUT oscillator pins (2fsc) fOSC2 The OSCIN and OSCOUT oscillator pins (LC oscillator) V 2.5 Vp-p 140 V mV 7.159 5 MHz 8 12 MHz Electrical Characteristics at Ta = –30 to +70°C, unless otherwise specified VDD1 = 5 V max Unit Output off leakage current Parameter Ileak1 COUT, YOUT, CVOUT 10 µA Input off leakage current Ileak2 CIN, YIN, CVIN 10 µA Output high-level voltage VOH1 CSYNOUT, SYNCJDG, SEPOUT; VDD1 = 4.5 V, IOH = 1.0 mA Output low-level voltage VOL1 CSYNOUT, SYNCJDG, SEPOUT; VDD1 = 4.5 V, IOL = 1.0 mA Input current Operating current drain Symbol Conditions IIH RST, CS, SIN, SCLK, CTRL1 to CTRL3, SEPIN; VIN = VDD1 IIL CTRL1 to CTRL3, OSCIN: VIN = VSS1 min typ 3.5 V 1.0 V 1 µA –1 µA IDD1 VDD1; all outputs open, crystal: 7.159 MHz, LC: 8 MHz 15 mA IDD2 VDD2; VDD2 = 5 V 20 mA No. 4247-2/14 LC74730M Timing Characteristics at Ta = –30 to +70°C, VDD1 = 5 ± 0.5 V Parameter Symbol tW (SCLK) Minimum input pulse width Data setup time Conditions min SCLK tW (CS) CS pin (during the period that CS is high) typ max Unit 200 ns 1 µs ns tSU (CS) CS 200 tSU (SIN) SIN 200 ns th (CS) CS 2 µs th (SIN) Data hold time One word write time SIN 200 ns tword The 8-bit data write time 4.2 µs twt The RAM data write time 1 µs Pin Functions Pin No. Symbol 1 VSS1 Ground Ground connection Crystal oscillator element connection Used to connect the external crystal and capacitors for the crystal oscillator that generates the internal synchronizing signal. Also used for an external clock input. (2fsc: 7.159 MHz) Crystal oscillator input switching Switches between the external 2fsc clock input mode and the crystal resonator driving mode. Low: crystal oscillator, high: external clock input Composite synchronizing signal output Outputs the composite synchronizing signal. Outputs the crystal oscillator clock on a reset due to a low level on the RST pin. Does not output any signal on a command reset. LC oscillator Connections for the coil and capacitor that form the oscillator that generates the character output dot clock. External synchronizing signal state judgment output Outputs the judgment as to whether or not an external synchronizing signal is present. Outputs a high level when a synchronizing signal is present. Outputs the dot clock (LC oscillator) on a reset due to a low level on the RST pin. Does not output any signal on a command reset. Enable input Enable input for serial data input. Serial data input is enabled by a low level. A pull-up resistor is built in. (This input has hysteresis characteristics.) 2 XtalIN 3 XtalOUT 4 CTRL1 5 CSYNOUT Function Description 6 OSCIN 7 OSCOUT 8 SYNCJDG 9 CS 10 SCLK Clock input Serial data input clock input. A pull-up resistor is built in. (This input has hysteresis characteristics.) 11 SIN Data input Serial data input. A pull-up resistor is built in. (This input has hysteresis characteristics.) 12 VDD2 Power supply Video signal level adjustment power supply. (Analog system power supply) 13 COUT Color signal output Color (C) signal output 14 NC 15 CIN 16 This pin must be level open or connected to ground. Color signal input Color (C) signal input CBIAS Chrominance bias output Chrominance signal bias level output 17 YOUT Luminance signal output Luminance signal (Y) output 18 NC 19 YIN This pin must be level open or connected to ground. Luminance signal input Luminance signal (Y) input 20 CTRL2 NTSC/PAL-M switching input Switches the synchronizing signal generator between NTSC and PAL-M formats. Low: NTSC, high: PAL-M 21 CVOUT Composite video signal output Outputs a composite video signal. 22 NC 23 CVIN 24 This pin must be level open or connected to ground. Composite video signal input Inputs a composite video signal. CTRL3 SEPIN input control Controls whether the VSYNC signal is input to the SEPIN input. Low: VSYNC is input, high: VSYNC is not input. 25 SYNIN Sync separator circuit input Video signal input to the built-in sync separator circuit. (Input either a horizontal or composite synchronizing signal to this pin if the built-in sync separator circuit is not used.) 26 SEPC Sync separator circuit adjustment Adjusts the built-in sync separator circuit. (Connect a capacitor to this pin.) (Leave this pin open if the built-in sync separator circuit is not used.) 27 SEPOUT Composite synchronizing signal output Outputs the built-in sync separator circuit composite synchronizing signal. (Outputs the SYNIN input signal if the built-in sync separator circuit is not used.) 28 SEPIN Vertical synchronizing signal input Integrates the SEPOUT output signal and inputs a vertical synchronizing signal. An integration circuit must be connected between this pin and the SEPOUT pin. This pin must be tied to VDD1 if it is not used. 29 RST Reset input The system reset input. A pull-up resistor is built in. (This input has hysteresis characteristics.) 30 VDD1 Power supply (+5 V) Power supply (+5 V: digital system power supply) No. 4247-3/14 LC74730M Block Diagram No. 4247-4/14 LC74730M Serial Data Input Timing Display Control Commands The display control commands have an 8-bit serial input format. Commands consist of a first byte, which includes the command identification code, and data in the second and following bytes. The LC74730M supports the following commands: ① COMMAND 0: Display memory (VRAM) write address setup command ② COMMAND 1: Display character data write command ③ COMMAND 2: Vertical display start position and vertical size setup command ④ COMMAND 3: Horizontal display start position and horizontal size setup command ⑤ COMMAND 4: Display control setup command ⑥ COMMAND 5: Synchronizing signal control setup command Display Control Command Table First byte Command Second byte Command identification code Data Data 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 COMMAND 0 Set write address 1 0 0 0 V3 V2 V1 V0 0 0 0 H4 H3 H2 H1 H0 COMMAND 1 Write character 1 0 0 1 0 0 0 0 at 0 c5 c4 c3 c2 c1 c0 1 0 1 0 VS 21 VS 20 VS 11 VS 10 0 0 VP 5 VP 4 VP 3 VP 2 VP 1 VP 0 1 0 1 1 HS 21 HS 20 HS 11 HS 10 0 0 HP 5 HP 4 HP 3 HP 2 HP 1 HP 0 COMMAND 4 Display control 1 1 0 0 TST MOD CB OSC STP SYS RST 0 0 NON EG BK 1 BK 0 RV DSP ON COMMAND 5 Synchronizing signal control 1 1 0 1 PH 1 PH 0 BCL INT 0 0 0 0 SN 3 SN 2 SN 1 SN 0 COMMAND 2 Set vertical display start position and vertical character size COMMAND 3 Set horizontal display start position and horizontal character size The command identification code in a first byte is retained until the next first byte is written. However, if a display character data write command (COMMAND 1) is written, the LC74730M locks in display character data write mode, and the first byte cannot be overwritten. The command state is reset to the COMMAND 0 state (display memory address setup mode) when the CS pin is set high. No. 4247-5/14 LC74730M ① COMMAND 0 (Display memory write address setup command) First byte Register content DA0 to DA7 Register name State 7 — 1 6 — 0 5 — 0 4 — 3 2 1 0 V3 V2 V1 V0 Function Note Command 0 identification code Set the display memory write address. 0 0 1 0 1 0 Display memory line address (0 to 9 hexadecimal) 1 0 1 Second byte Register content DA0 to DA7 Register name State 7 — 0 6 — 0 5 — 0 4 H4 3 H3 2 H2 1 H1 0 H0 Function Note Second byte identification bit 0 1 0 1 0 1 Display memory character address (0 to 17 hexadecimal) 0 1 0 1 Note: All these registers are set to 0 by a reset due to the RST pin. ② COMMAND 1 (Display character data write setup command) First byte Register content DA0 to DA7 Register name State 7 — 1 6 — 0 5 — 0 4 — 1 3 — 0 2 — 0 1 — 0 0 — 0 Function Command 1 identification code Sets up a display character data write operation Note When this command is issued, the LC74730M is locked in display character data write mode until the CS pin goes high. No. 4247-6/14 LC74730M Second byte Register content DA0 to DA7 Register name 7 at 6 — 5 c5 4 c4 3 c3 2 c2 1 c1 0 c0 State Note Function 0 Character attributes off 1 Character attributes on 0 0 1 0 1 0 1 0 Character code (00 to 3F hexadecimal) 1 0 1 0 1 Note: All these registers are set to 0 by a reset due to the RST pin. ③ COMMAND 2 (Vertical display start position and vertical size setup command) First byte Register content DA0 to DA7 Register name State 7 — 1 6 — 0 5 — 1 4 — 0 3 VS21 2 VS20 1 VS11 0 VS10 Command 2 identification code Sets up the vertical display position and the character size in the vertical direction. 0 1 Note Function VS20 VS21 0 1 0 0 1 H per dot 2 H per dot 1 1 3 H per dot 1 H per dot 0 1 VS10 VS11 0 Vertical character size for the second line 1 0 0 1 H per dot 2 H per dot 1 1 3 H per dot 1 H per dot Vertical character size for the first line No. 4247-7/14 LC74730M Second byte Register content DA0 to DA7 Register name State Note Function 7 — 0 6 — 0 VP5 (MSB) 0 If VS is the vertical display start position then: 5 1 VS = H × (2Σ 2nVPn) 4 VP4 3 VP3 2 VP2 1 VP1 0 VP0 (LSB) Second byte identification bit 5 n=0 0 1 Where H is horizontal period pulse period. 0 The vertical display start position is specified by the 6 bits VP0 to VP5. 1 0 The weight of the low-order bit is 2 H. 1 0 1 0 1 Note: All these registers are set to 0 by a reset due to the RST pin. ④ COMMAND 3 (Horizontal display start position and horizontal size setup command) First byte Register content DA0 to DA7 Register name State 7 — 1 6 — 0 5 — 1 4 — 1 3 HS21 2 HS20 1 HS11 0 HS10 Command 3 identification code Sets up the horizontal display position and the character size in the horizontal direction. 0 1 Note Function HS20 HS21 0 1 0 0 1 Tc per dot 2 Tc per dot 1 1 3 Tc per dot 1 Tc per dot 0 1 HS10 HS11 0 Horizontal character size for the second line 1 0 0 1 Tc per dot 2 Tc per dot 1 1 3 Tc per dot 1 Tc per dot Horizontal character size for the first line Second byte Register content DA0 to DA7 Register name State Function 7 — 0 6 — 0 HP5 (MSB) 0 If HS is the horizontal start position then: 5 1 HS = Tc × (2Σ 2nHPn) 4 HP4 3 HP3 2 HP2 1 HP1 0 HP0 (LSB) 0 1 0 Note Second byte identification bit 5 n=0 Where Tc is a single period of the LC oscillator connected the OSCIN and OSCOUT pins. 1 0 The horizontal display start position is specified by the 6 bits HP0 to HP5. The weight of the low-order bit is 2 Tc. 1 0 1 0 1 Note: All these registers are set to 0 by a reset due to the RST pin. No. 4247-8/14 LC74730M ⑤ COMMAND 4 (Display control setup command) First byte Register content DA0 to DA7 Register name State 7 — 1 6 — 1 5 — 0 4 — 3 TSTMOD 2 CB 1 OSCSTP 0 SYSRST Note Function Command 4 identification code Sets up the display control state. 0 0 Normal operating mode 1 Test mode Must be set to 0. 0 Output the color burst signal. 1 Stop color burst signal output. Valid only when BCL is high. 0 Does not stop the crystal and LC oscillators. 1 Stops the crystal and LC oscillators. Valid in external synchronization mode when character display is off. Resets all registers and turns off display. Reset occurs when the CS pin is low, and the reset is cleared when CS goes high. 0 1 Second byte Register content DA0 to DA7 Register name State 7 — 0 6 — 0 5 NON 4 EG 3 BK1 2 BK0 1 0 RV DSPON Function Note Second byte identification code 0 Interlace (262.5 H per field) 1 Non-interlaced (263 H per field) 0 Border off 1 Border on 0 Blinking period: about 0.5 s 1 Blinking period: about 1 s 0 Blinking off 1 Blinking on 0 Reverse video character display off 1 Reverse video character display on 0 Character display off 1 Character display on Switches between interlaced and non-interlaced display Switches the blinking period Blinking during reversed video character display switches the character display between normal display and reversed video display. Note: All these registers are set to 0 by a reset due to the RST pin. No. 4247-9/14 LC74730M ⑥ COMMAND 5 (Synchronizing signal control setup command) First byte Register content DA0 to DA7 Register name State 7 — 1 6 — 1 5 — 0 4 — 1 3 PH1 Note Function Command 5 identification code Sets up control of the synchronizing signals 0 PHASE1 PHASE0 1 0 2 PH0 Background color (phase) 0 0 π/2 0 1 π 1 0 3π/2 1 1 In phase Sets the background color (one of 4 colors). There is only one background color (blue) in PAL-M mode. 1 1 BCL 0 INT 0 Background color displayed. 1 No background color (only the background level is set). 0 External synchronization 1 Internal synchronization Valid only in internal synchronization mode Switches between internal and external synchronization. Second byte Register content DA0 to DA7 Register name State 7 — 0 6 — 0 5 — 0 4 — 0 3 SN3 2 1 0 SN2 SN1 SN0 Note Function Second byte identification bit 0 1 SN3 SN2 SN1 SN0 Number of times HSYNC detected 0 0 0 0 0 Not detected 1 0 0 0 1 16 times 0 0 0 1 0 32 times 1 0 1 0 0 64 times 0 1 0 0 0 128 times External synchronizing signal detection control 1 Note: All these registers are set to 0 by a reset due to the RST pin. Display Screen Organization The display screen consists of 10 lines of 24 characters each. Thus the maximum number of characters that can be displayed is 240 characters. However, the maximum number of characters that can be displayed may be fewer than 240 when characters are enlarged. The display memory address consists of a line address (with values from 0 to 9 decimal), and a column (character position) address (with values from 0 to 23 decimal). No. 4247-10/14 LC74730M Display Screen Organization (Display memory address) No. 4247-11/14 LC74730M Composite Video Signal Output Levels (internally generated levels) Output level (IRE) Output voltage (VDC) 100 3.000 90 2.857 46 2.228 20 1.857 10 1.714 8 1.685 0 1.571 –20 1.285 –40 1.000 Note: VDD2 = 5.000 VDC No. 4247-12/14 LC74730M Video Signal Output Levels (Y (luminance) signal: internally generated levels) Output level (IRE) Output voltage (VDC) 100 3.000 90 2.857 28 1.971 20 1.857 8 1.685 0 1.571 –40 1.000 Note: VDD2 = 5.000 VDC No. 4247-13/14 LC74730M Video Signal Output Levels (chrominance signal: internally generated levels) Output level (IRE) Output voltage (VDC) 40 3.071 20 2.786 0 2.500 –20 2.214 –40 1.928 Note: VDD2 = 5.000 VDC ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. No. 4247-14/14