Ordering number : EN5159B CMOS LSI LC74772V Camcorder On-Screen Display LSI Overview The LC74772V is a CMOS LSI that implements on-screen display for camcorders. It displays characters and patterns in a camcorder viewfinder under microprocessor control. The LC74772V displays a 12 × 18 dot font with 256 characters. • Outputs: R, G, B plus 2 output systems Or: 4 output systems (character data and blanking data: 4 outputs each) • External control input: 8-bit serial data input format. Package Dimensions unit: mm Features 3175A-SSOP24 24 1.0 [LC74772V] 0.5 7.6 5.6 13 12 1.6max 1 8.0 0.15 0.1 • Screen format: 12 lines × 24 characters (up to 288 characters) • Number of characters displayed: Up to 288 characters • Character format: 12 (horizontal) × 18 (vertical) dots • Number of characters in font: 256 characters • Character sizes: Normal and double, specified in line units • Display start position — Horizontal: 64 positions — Vertical: 64 positions • Character reverse video function: Individual characters can be displayed in reverse video. • Types of blinking: Two types with periods of 1.0 and 0.5 seconds, specifiable on a per character basis. (Blinking has a 60% display on duty.) (Four divisors: 1/25, 1/30, 1/50, 1/60) 0.22 0.65 0.43 SANYO: SSOP24 Specifications Absolute Maximum Ratings Parameter Symbol Conditions Ratings Unit Supply voltage VDD VDD VSS – 0.3 to VSS + 7.0 V Input voltage VIN All input pins VSS – 0.3 to VDD + 0.3 V CKOUT, CHA4, BLK4, CHA3, BLK3, B, G, R, BLANK VSS – 0.3 to VDD + 0.3 Output voltage VOUT Allowable power dissipation Pd max Ta = 25°C 300 V mW Operating temperature Topr –30 to +70 °C Storage temperature Tstg –40 to +125 °C Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 23099HA(OT)/O3096HA(OT)/D3095HA (OT) No. 5159-1/17 LC74772V Allowable Operating Ranges at Ta = –30 to +70°C Parameter Supply voltage Symbol Conditions VDD VDD Input high-level voltage VIH CTRL1, TESTIN, CS, SCLK, SIN, OUTMOD, HSYNC, VSYNC, RST Input low-level voltage VIL CTRL1, TESTIN, CS, SCLK, SIN, OUTMOD, HSYNC, VSYNC, RST Oscillator frequency FOSC Ratings min typ 2.7 5.5 V 0.8 VDD VDD + 0.3 V VSS – 0.3 0.2 VDD V OSCIN, OSCOUT (LC oscillator) 6 5.0 Unit max (8) 10 MHz Electrical Characteristics at Ta = –30 to +70°C, unless otherwise specified VDD = 5 V Parameter Symbol Conditions Output high-level voltage VOH CKOUT, CHA4, BLK4, CHA3, BLK3, B, G, R, BLANK: VDD = 5.5 to 4.5 V (VDD = 4.4 to 2.7 V), IOH = –1.0 mA (–0.5 mA) Output low-level voltage VOL CKOUT, CHA4, BLK4, CHA3, BLK3, B, G, R, BLANK: VDD = 5.5 to 4.5 V (VDD = 4.4 to 2.7 V), IOL = 1.0 mA (0.5 mA) IIH CTRL1, TESTIN, CS, SCLK, SIN, OUTMOD, HSYNC, VSYNC: VIN = VDD IIL CTRL1, TESTIN, HSYNC, VSYNC: VIN = VSS IDD VDD pin; all outputs open, LC oscillator: 8 MHz Input current Operating current drain Ratings min typ Unit max 0.9 VDD V 0.1 VDD V 1 µA 10 mA –1 µA Timing Characteristics at Ta = –30 to +70°C, VDD = 5 ± 0.5 V Parameter Minimum input pulse width Data setup time Data hold time One-word write time Symbol tW (SCLK) Conditions SCLK tW (CS) CS (the period that CS is high) tSU (CS) Ratings min typ 200 max Unit ns 1 µs CS 200 ns tSU (SIN) SIN 200 ns th (CS) CS 2 µs th (SIN) SIN 200 ns The time to write 8 bits of data 4.2 µs 1 µs tword twt The RAM data write time No. 5159-2/17 LC74772V Serial Data Input Timing Pin Assignment The signal names in parentheses indicate the output pin functions when 4-system output mode is used. No. 5159-3/17 LC74772V Pin Functions PinNo. Symbol 1 VSS Function Description Ground Ground connection LC oscillator Connections for the coil and capacitor that form the oscillator that generates the character output horizontal dot clock. Control input that switches between LC oscillator mode and clock input mode Low: LC oscillator mode, high: clock input mode 2 OSCIN 3 OSCOUT 4 CTRL1 Clock input control 5 TESTIN Test control input Test mode control input (The IC operates in test mode when this input is high.) Enable input Serial data input enable input Low: active (This input has hysteresis characteristics.) 6 CS 7 SCLK Clock input Serial data input clock input (This input has hysteresis characteristics.) 8 SIN Data input Serial data input (This input has hysteresis characteristics.) 9 CKOUT Clock output LC oscillator clock monitor output This signal is output when RST is low. 10 BLK4 Blanking signal output Blanking signal output (system 2) Functions as the system 4 blanking data signal output in 4-system mode. 11 CHA4 Character data output Character data signal output (system 2) Functions as the system 4 character data signal output in 4-system mode. 12 NC Unused Must be left open or tied to ground in normal operation. 13 NC Unused Must be left open or tied to ground in normal operation. 14 BLK3 Blanking signal output Blanking signal output (system 1) Functions as the system 3 blanking data signal output in 4-system mode. 15 CHA3 Character data output Character data signal output (system 1) Functions as the system 3 character data signal output in 4-system mode. 16 BLANK Blanking signal output Blanking signal output (blanking signal for RGB output) Functions as the system 2 blanking data signal output in 4-system mode. 17 R Character data output Character data (R) signal output Functions as the system 2 character data signal output in 4-system mode. 18 G Character data output Character data (G) signal output Functions as the system 1 blanking data signal output in 4-system mode. 19 B Character data output Character data (B) signal output Functions as the system 1 character data signal output in 4-system mode. 20 OUTMOD Output control input Control input that switches between RGB output and 4-system output Low: RGB output, high 4-system output 21 VSYNC Vertical synchronizing signal input Vertical synchronizing signal input (This input has hysteresis characteristics.) 22 HSYNC Horizontal synchronizing Horizontal synchronizing signal input (This input has hysteresis characteristics.) signal input 23 RST Reset input System reset signal input (This input has hysteresis characteristics.) 24 VDD Power supply Power supply connection (+5 V) Note: 1. Built-in pull-up resistors can be specified for inclusion in the CS (pin 6), SCLK (pin 7), SIN (pin 8), and RST (pin 23) pins as mask options. 2. In clock input mode (when CTRL1 is high), the function that holds the OSCIN (pin 2) pin high during an oscillator reset is stopped. No. 5159-4/17 LC74772V Block Diagram No. 5159-5/17 LC74772V Display Control Commands The display control commands have an 8-bit serial input format. Data is input LSB first. Display Control Command Table First byte Command Second byte Command code D7 D6 D5 Data Data D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 RST SYS RAM CLR OSC STP TST MOD — — — — — — — — COMMAND 0 System setup 1 0 0 0 0 COMMAND 1 System setup 2 0 0 0 1 CSYN CLK CLK CLK MOD POLT MOD1 MOD0 — — — — — — — — COMMAND 2 Input control setup 0 0 1 0 VSYN HSYN DATA ART POLT POLT FMT FMT — — — — — — — — COMMAND 3 General-purpose port control 0 0 1 1 PORT OUT SET P11 COMMAND 4 Display operation control: reverse video and blinking 0 1 0 0 RVS ON COMMAND 5 Display control: on/off settings for each output 0 1 0 1 DSP 4 COMMAND 6 Output control: systems 3 and 4 0 1 1 0 COMMAND 8 Display control: border 1 0 0 0 COMMAND 9 Display start position 1 0 0 COMMAND 10 Display line control 1 0 COMMAND 11 RAM write address 1 COMMAND 14 Display RAM setup data 1 OUT P10 OUT P9 — — — — — — — — BLK ON BLK 1 BLK 0 — — — — — — — — DSP 3 DSP 2 DSP 1 — — — — — — — — DSPF DSP SL34 RSG DSP GSG DSP BSG — — — — — — — — 0 BKC R BKC G BKC BKO4 BKO4 BKO3 BKO3 BKO2 BKO2 BKO1 BKO1 B F1 F0 F1 F0 F1 F0 F1 F0 1 VP5 VP4 VP3 VP2 VP1 VP0 HP5 HP4 HP3 HP2 HP1 HP0 1 0 LNF SZ LNF OT4 LNF OT3 LN SEL 0 0 LIN 126 LIN 115 LIN 104 LIN 93 LIN 82 LIN 71 0 1 1 0 0 0 1 1 BLK C7 C6 C5 VADR VADR VADR VADR 3 2 1 0 RV R G B ① HADR HADR HADR HADR HADR 4 3 2 1 0 C4 C3 C2 C1 C0 ② ① Command code: (These 4 bits in the first byte identify the command.) Command 14 is recognized by the upper 3 bits. ② Command data: (These bits specify the data for each command.) • For commands 0 through 7, 8 bits of data are read in. • For commands 8 through 14, 16 bits of data are read in. • If the command 2 data-1 bit (DATAFMT) was set to 1, after the first byte of a command 14 is read in, the system goes to continuous transfer mode for reading in a series of following bytes. Note: 1. If the CS pin is set high, the command state is set to the command 0 (system control setup) state. 2. If a system reset is executed from the RST pin or by a command reset, the command register is set tot 0. No. 5159-6/17 LC74772V ① COMMAND 0 (System control setup 1) First byte Register content DA0 to DA7 Register name State Function Note 7 — 0 6 — 0 5 — 0 4 — 0 3 RST SYS 0 Normal operation 1 System reset RAM CLR 0 2 1 The VRAM clear operation is not executed when the oscillator Normal operation VRAM clear (All data is set to FE (hexadecimal)) is stopped. 0 The LC oscillator operating state is maintained. 1 The LC oscillator is stopped. 1 0 OSC STP TST MOD Command 0 identification code If CS is low, the reset is executed, but if CS is high this command will be excluded. Normal operation 0 Normal operation 1 Test mode Valid when the display is off. VRAM write is not possible when the oscillator is stopped. Illegal setting. This bit must always be set to 0. Note: This register is set to 0 on a reset (either by the RST pin or by a command reset). Notes on command settings 1. RSTSYS: A command reset is executed immediately after the data is read. The reset is cleared by returning the CS pin to high to reset this register. The reset is also cleared if this command is executed consecutively or if this register is set to 0. 2. RAMCLR: The RAM can only be erased when display is off. This operation is not executed during display. This operation cannot be executed if the LC oscillator is stopped. Only use this command when the LC oscillator is operating. • This command bit is automatically cleared when the RAM erase operation completes. • Once the RAM erase command has been read in, the following time is required to complete the operation. — Tclear = 5 [µs] + 4/fOSC (LC-oscillator) × 288 3. OSCSTP: The LC oscillator stop command stops the LC oscillator connected to pins 2 and 3 (OSCIN and OSCOUT). The oscillator stop command is only executed when display is off. It is not executed if display is in progress. • In external clock input mode, this command stops the acquisition of that clock signal. 4. TSTMOD: The test mode command is executed if the TESTIN pin (pin 5) is high. This command should not be used by applications in normal operation. No. 5159-7/17 LC74772V ② COMMAND 1 (System control setup 2) First byte Register content DA0 to DA7 Register name State 7 — 0 6 — 0 5 — 0 4 — 1 3 CSYN MOD 2 1 0 CLK POLT CLK MOD1 CLK MOD0 Note Function Command 1 identification code 0 HSYNC (pin 22) functions as the horizontal synchronizing signal input 1 HSYNC (pin 22) functions as the composite synchronizing signal input 0 The system clock has a positive polarity. 1 The system clock has a negative polarity. 0 1 0 1 MOD1 MOD0 0 0 LC oscillator mode 0 1 Clock input (1 dot) 1 0 Clock input (NTSC) 1 1 Clock input (PAL) The VSYNC pin (pin 21) must be tied to ground or VDD in composite synchronizing signal input mode. This sets the clock polarity for system operation when pin 2 is used as a clock input. Operation Valid when the CTRL1 pin (pin 4) is high. The input clock frequency in clock input mode is either 4fsc or the dot clock frequency. ③ COMMAND 2 (Input control) First byte Register content DA0 to DA7 Register name State 7 — 0 6 — 0 5 — 1 Function Command 2 identification code 4 — 0 3 VSYN POLT 0 The vertical synchronizing signal input polarity is low active. 1 The vertical synchronizing signal input polarity is high active. 2 HSYN POLT 0 The horizontal synchronizing signal input polarity is low active. 1 The horizontal synchronizing signal input polarity is high active. DATA FMT 0 Data is transferred in 16-bit units. 1 1 Continuous transfers with the upper 8 bits input first and then the lower 8 bits 0 RV specifies the reverse video display function. 1 RV specifies system 3 output control. 0 ATR FMT Note Sets the pin 21 (VSYNC) signal input polarity. Sets the pin 22 (HSYNC) signal input polarity. Sets the COMMAND 14 data transfer format. COMMAND-14 Data 11: Valid in RV RGB output mode. Note: This register is set to 0 on a reset (either by the RST pin or by a command reset). No. 5159-8/17 LC74772V ④ COMMAND 3 (General-purpose port control) First byte Register content DA0 to DA7 Register name State Note Function 7 — 6 — 0 0 5 — 1 4 — 1 3 PORT SET 0 System 4 functions as a normal character and border outputs. 1 System 4 functions as general-purpose ports. 2 OUT P11 0 The pin 11 output is set to low. 1 The pin 11 output is set to high. 1 OUT P10 0 The pin 10 output is set to low. 1 The pin 10 output is set to high. 0 OUT P9 0 The pin 9 output is set to low. 1 The pin 9 output is set to high. Command 3 identification code Controls the pin 10 (BLK4) and pin 11 (CHA4) outputs. Sets the output when PORTSET is set to 1. Sets the output when PORTSET is set to 1. Sets the output for pin 9 during normal operation (other than during a reset). ⑤ COMMAND 4 (Display control: reverse video and blinking) First byte Register content DA0 to DA7 Register name State 7 — 0 6 — 1 5 — 0 4 — 0 3 RVS ON 2 BLK ON Note Function Command 4 identification code 0 — 1 Characters for which the attribute is specified are displayed in reverse video. 0 — 1 Characters for which the attribute is specified are displayed blinking. 0 1 BLK1 1 0 0 BLK0 1 BLK1 BLK0 0 0 V × 25 (PAL: 0.5 s) Operation 0 1 V × 30 (NTSC: 0.5 s) 1 0 V × 50 (PAL: 1.0 s) 1 1 V × 60 (NTSC: 1.0 s) The blinking period setting The duty is 60% for all types. Character display on: 60% Character display off: 40% V: Vertical period Note: This register is set to 0 on a reset (either by the RST pin or by a command reset). No. 5159-9/17 LC74772V ⑥ COMMAND 5 (Display control: on/off settings for each output system) First byte Register content DA0 to DA7 Register name State 7 — 0 6 — 1 5 — 0 4 — 1 3 DSP4 2 DSP3 1 0 Note Function Command 5 identification code 0 System 4 output off 1 System 4 output on Pin 10 (BLK4) and pin 11 (CHA4) output control 0 System 3 output off 1 System 3 output on 0 System 2 output off Pin 16 (BLK2) and pin 17 (CHA2) output control 1 System 2 output on Invalid in RGB output mode. 0 System 1 (RGB) output off Pin 18 (BLK1) and pin 19 (CHA1) output control 1 System 1 (RGB) output on Functions as the RGB output control in RGB output mode. Pin 14 (BLK3) and pin 15 (CHA3) output control DSP2 DSP1 ⑦ COMMAND 6 (Output control: systems 3 and 4 output control settings) First byte Register content DA0 to DA7 Register name State 7 — 0 6 — 1 5 — 1 4 — 0 3 DSPF SL34 2 DSP RSG DSP GSG Sets the system 3 output conditions according to the command described below. 1 Sets the system 4 output conditions according to the command described below. 0 0 1 0 DSP BSG Command 6 identification code 0 1 1 Note Function 0 1 DSPRSG DSPGSG DSPBSG Only system 4 is valid in 4-system output mode. System 4 cannot be set when the general-purpose output port usage is specified. Output selection 0 0 0 Signals other than R, G, B are output. 0 0 1 B is output. 0 1 0 G is output. 0 1 1 G and B are output. 1 0 0 R is output. 1 0 1 R and B are output. 1 1 0 R and G are output. 1 1 1 All of R, G, B are output. Note: The following registers are set to 1 during a reset. DSPRSG DSPGSG DSPBSG As a result, the “All of R, G, B are output” state is selected during a reset. Note: This register is set to 0 on a reset (either by the RST pin or by a command reset). No. 5159-10/17 LC74772V ⑧ COMMAND 8 (Output control: background color setting: RGB output mode) First byte Register content DA0 to DA7 Register name State 7 — 1 6 — 0 5 — 0 4 — 0 3 0 0 2 BKCR 1 0 1 BKCG 1 0 0 BKCB 1 Note Function Command 8 identification code — BKCR BKCG BKCB 0 0 0 Black Background color 0 0 1 Blue 0 1 0 Green 0 1 1 Cyan 1 0 0 Red 1 0 1 Magenta 1 1 0 Yellow 1 1 1 White Background color setting in RGB output mode This command is invalid in 4-system output mode. • Invalid when pin 20 (OUTMOD) is high. • Valid when pin 20 (OUTMOD) is low. Second byte Register content DA0 to DA7 Register name 7 BKO4 F1 State BKO4 F0 Note 0 BKO4F1 BKO4F0 1 6 Function 0 Operation function 0 0 No background or border 0 1 Font size (black characters) 1 0 Border 1 1 Areas other than the font (all filled) The system 4 output border setting 1 5 BKO3 F1 0 BKO3F1 BKO3F0 1 4 BKO3 F0 0 Operation function 0 0 No background or border 0 1 Font size (black characters) 1 0 Border 1 1 Areas other than the font (all filled) The system 3 output border setting 1 3 BKO2 F1 0 BKO2F1 BKO2F0 1 2 BKO2 F0 0 Operation function 0 0 No background or border 0 1 Font size (black characters) 1 0 Border 1 1 Areas other than the font (all filled) The system 2 output border setting This command is invalid in RGB output mode. • Invalid when pin 20 (OUTMOD) is low. • Valid when pin 20 (OUTMOD) is high. 1 1 BKO1 F1 0 BKO1F1 BKO1F0 1 0 BKO1 F0 0 Operation function 0 0 No background or border 0 1 Font size 1 0 Border 1 1 Areas other than the font (all filled) The system 1 or RGB output border setting 1 Note: This register is set to 0 on a reset (either by the RST pin or by a command reset). No. 5159-11/17 LC74772V ⑨ COMMAND 9 (Display start position setting) First byte Register content DA0 to DA7 Register name State 7 — 1 6 — 0 5 — 0 4 — 1 0 3 VP5 Function Note Command 9 identification code If VS is the vertical display start position then: 5 VS = H × (Σ 2nVPn) + 16H n=0 1 Where H is horizontal period pulse period. 0 2 VP4 1 0 1 VP3 1 0 0 VP2 1 Second byte Register content DA0 to DA7 Register name 7 VP1 6 VP0 5 HP5 4 HP4 3 HP3 2 HP2 1 HP1 0 HP0 State Function Note 0 1 0 1 0 1 0 If VS is the horizontal display start position then: 1 HS = Tc × (Σ 2nHPn) + 12Tc 0 1 0 1 0 1 5 n=0 Where Tc is a single period of the LC oscillator connected to pins 2 and 3 (OSCIN and OSCOUT), or: Tc is the period of the input clock (4fsc input) if CTRL1 (pin 4) is high. NTSC mode: 7.159 MHz = 4fsc × 1/2 PAL mode: 7.094 MHz = 4fsc × 2/5 0 1 Note: This register is set to 0 on a reset (either by the RST pin or by a command reset). No. 5159-12/17 LC74772V ⑩ COMMAND 10 (Display line control) First byte Register content DA0 to DA7 Register name State Function 7 — 1 6 — 0 5 — 1 4 — 0 LNF SZ 0 1 Sets the character size. 2 LNF OT4 0 — 1 Sets the system 4 display line. 1 LNF OT3 0 — 1 Sets the system 3 display line. 0 LNF SEL 0 The line specified by the next 6 bits is one of lines 1 to 6. 1 The line specified by the next 6 bits is one of lines 7 to 12. 3 Note Command 10 identification code — Invalid in general-purpose port mode. Invalid in system 4 output setup mode. Controls the line switching specified by the six bits in the second byte. Second byte Register content DA0 to DA7 Register name State Function 7 — 0 — 6 — 0 — 5 LIN 126 0 Clears the line 6 (12) setting. 1 Sets line 6 (12). LIN 115 0 Clears the line 5 (11) setting. 1 Sets line 5 (11). 3 LIN 104 0 Clears the line 4 (10) setting. 1 Sets line 4 (10). 2 LIN 93 4 0 Clears the line 3 (9) setting. 1 Sets line 3 (9). Clears the line 2 (8) setting. 1 LIN 82 0 1 Sets line 2 (8). 0 LIN 71 0 Clears the line 1 (7) setting. 1 Sets line 1 (7). Note The character size or display line setting 0: Character size specification = normal Display line specification = off 1: Character size specification = double size Display line specification = on Note: This register is set to 0 on a reset (either by the RST pin or by a command reset). No. 5159-13/17 LC74772V 11 COMMAND 11 (Display RAM write address setting) First byte Register content DA0 to DA7 Register name State 7 — 1 6 — 0 5 — 1 4 — 1 3 VADR 3 0 2 VADR 2 0 1 VADR 1 0 0 VADR 0 0 Function Note Command 11 identification code 1 1 The range of the display RAM vertical address (line address) setting is from 0 to B (hexadecimal) (12 lines). Values of C (hexadecimal) or larger are not allowed. 1 1 Second byte Register content DA0 to DA7 Register name State Function 7 — 0 — 6 — 0 — 5 — 0 — 4 HADR 4 0 3 HADR 3 0 2 HADR 2 0 1 HADR 1 0 0 HADR 0 0 Note 1 1 1 The range of the display RAM horizontal address (character address) setting is from 00 to 17 (hexadecimal) (24 characters). Values of 18 (hexadecimal) or larger are not allowed. 1 1 Note: This register is set to 0 on a reset (either by the RST pin or by a command reset). No. 5159-14/17 LC74772V 12 COMMAND 14 (Display RAM setup data) First byte Register content DA0 to DA7 Register name State 7 — 1 6 — 1 5 — 1 4 BLK 3 2 1 0 RV R G B 0 Function Note Command 14 identification code — 1 Blinking character specification 0 — 1 Reverse video character specification 0 — 1 R output specification (system 3 output in 4-system output mode) 0 — 1 G output specification (system 2 output in 4-system output mode) 0 — 1 B output specification (system 1 output in 4-system output mode) Second byte Register content DA0 to DA7 Register name 7 C7 6 C6 5 C5 4 C4 3 C3 2 C2 1 C1 0 C0 State Function Note 0 1 0 1 0 1 0 1 0 1 0 1 Character code setting There are 256 characters (00 to FF hexadecimal). FE hexadecimal is handled as blank data. Nothing is displayed, whatever the other conditions are set to. FF hexadecimal functions as the transfer termination code for character-code-only continuous transfers. Continuous transfer mode is set up by setting the data 0 bit (DATAFMT) in COMMAND 2 to 1. 0 1 0 1 Note: This register is set to 0 on a reset (either by the RST pin or by a command reset). No. 5159-15/17 LC74772V Display Screen Organization The display screen consists of 12 lines of 24 characters each. Thus the maximum number of characters that can be displayed is 288 characters. The display memory address consists of a line address (VADR0, VADR1, VADR2, and VADR3 representing values from 0 to B (hexadecimal)), and a column (character position) address (HADR0, HADR1, HADR2, HADR3, and HADR4 representing values from 0 to 17 (hexadecimal)). Display Screen Organization (Display memory address) No. 5159-16/17 LC74772V Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1999. Specifications and information herein are subject to change without notice. PS No. 5159-17/17