Ordering number : EN5213A CMOS LSI LC74725, 74725M On-Screen Display Controller LSI Overview Package Dimensions The LC74725 and LC74725M are built-in EDS on-screen display controller CMOS LSI products that display characters and patterns on a TV screen under microprocessor control. The characters displayed have an 8 × 8 dot format, and a dot interpolation function is provided. These LSIs can display ten lines of 24 characters each. unit: mm 3067-DIP24S [LC7425] Features • Display format: 24 characters by 10 lines (up to 240 characters) • Character format: 8 (horizontal) × 8 (vertical) dots (interpolation function provided) • Character sizes: Two horizontal and two vertical sizes • Characters in font: 64 characters • Initial display positions: 64 horizontal positions and 64 vertical positions • Blinking: Specifiable on a per-character basis • Blinking types: Two periods, 1.0 second and 0.5 second • Blue background screen display: Available in internal synchronization mode • External control input: 8-bit serial input format • Built-in sync separator circuit • EDS support • Video outputs: Composite video signal output in either NTSC or PAL-M • Package: 24-pin plastic DIP (300 mil) 24-pin plastic MFP (375 mil) SANYO: DIP24S 3045B-MFP24 [LC7425M] SANYO: MFP24 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 41096HA (OT)/O3195HA (OT) No. 5213-1/16 LC74725, 74725M Pin Assignment Pin Functions Pin No. Symbol 1 VSS1 2 XtalIN 3 XtalOUT 4 CTRL1 5 LN21 6 OSCIN 7 OSCOUT Function Description Ground Ground connection (digital system ground) Crystal oscillator Connections for the external crystal and capacitors used to form a crystal oscillator for internal synchronizing signal generation. Alternatively, these pins can be used for external clock input (2fsc or 4fsc). Crystal oscillator input switching Switches between external clock input mode and crystal oscillator mode. Low: crystal oscillator mode, high: external clock input mode. Data output Line 21H pulse output (MOD0 = low: even field, MOD0 = high: both fields output) LC oscillator Connections for the external coil and capacitor used to form the character output dot clock generation oscillator. External synchronizing signal judgment output Outputs the judgment as to where there are or are not external synchronizing signals present. Outputs a high level when there are synchronizing signals. SEL0 = high: Outputs field discrimination pulses (O/E pulses) Outputs the dot clock (LC oscillator) when the CS1 pin is high and the RST pin is low. A command is provided that turns this output off. Outputs the crystal oscillator clock when the CS1 pin is low and the RST pin is low. A command is provided that turns this output off. Enable input Enable input for OSD serial data input. Serial data input is enabled when this pin is low. A pullup resistor is built in (hysteresis input). 8 SYNCJDG 9 CS1 10 SCLK Clock input Serial data input clock input. A pull-up resistor is built in (hysteresis input). Data input Serial data input. A pull-up resistor is built in (hysteresis input). 11 SIN 12 VDD2 13 CVOUT Power supply Composite video signal level adjustment power supply (analog system power supply) Video signal output Composite video signal output pin 14 NC 15 CVIN Video signal input Must be either connected to ground or left open. 16 VDD1 Power supply Power supply (+5 V: digital system power supply) 17 SYNIN Sync separator circuit input Video signal input to the built-in sync separator circuit 18 VSS1 Ground Ground (digital system ground) Composite synchronizing signal output Video signal output from the built-in sync separator circuit Vertical synchronizing signal input Inputs the vertical synchronizing signal generated by integrating the SEPOUT pin output signal. An integrating circuit must be inserted between the SEPOUT pin and this pin. This pin must be tied to VDD1 if unused. Composite video signal input pin 19 SEPOUT 20 SEPIN 21 CS2 Enable input Enable input for EDS data output. EDS data output is enabled when this input is low. A pull-up resistor is built in (hysteresis input). 22 CPDT Data output EDS data output (either an n-channel open-drain or a CMOS output circuit) 23 RST Reset input System reset input. A pull-up resistor is built in (hysteresis input). 24 VDD1 Power supply (+5 V) Power supply (+5 V: digital system power supply) Note: Both VDD1 pins must be connected to the power supply. No. 5213-2/16 LC74725, 74725M Specifications Absolute Maximum Ratings at Ta = 25°C Ratings Unit Maximum supply voltage Parameter VDD max Symbol VDD1, VDD2 VSS – 0.3 to VSS + 7.0 V Maximum input voltage VIN max All input pins VSS – 0.3 to VDD + 0.3 V LN21, CPDT, SEPOUT, SYNCJDG VSS – 0.3 to VDD + 0.3 Maximum output voltage VOUT max Allowable power dissipation Pd max Conditions Ta = 25°C 350 V mW Operating temperature Topr –30 to +70 °C Storage temperature Tstg –40 to +125 °C max Unit Allowable Operating Ranges at Ta = –30 to +70°C Parameter Supply voltage Input high level voltage Input low level voltage Pull-up resistance Composite video input voltage Input voltage Oscillator frequency Symbol Conditions min typ VDD1 VDD1 4.5 5.0 5.5 V VDD2 VDD2 4.5 5.0 1.27 VDD1 V VIH1 RST, CS1, CS2, SIN, SCLK 0.8 VDD1 VDD1 + 0.3 V VIH2 CTRL1, SEPIN 0.7 VDD1 VDD1 + 0.3 V VIL1 RST, CS1, CS2, SIN, SCLK VSS – 0.3 0.2 VDD1 V VIL2 CTRL1, SEPIN VSS – 0.3 0.3 VDD1 V RPU Applies to RST, CS1, CS2, SIN, SCLK, and the pins specified as options. 25 50 90 kΩ VIN1 CVIN: VDD1 = 5 V VIN2 SYNIN: VDD1 = 5 V 1.5 VIN3 XtalIN (when external clock input is used), fIN = 2fsc or 4fsc: VDD1 = 5 V 0.1 fOSC1 XtalIN, XtalOUT oscillator pins (2fsc: NTSC) 7.159 MHz fOSC1 XtalIN, XtalOUT oscillator pins (4fsc: NTSC) 14.318 MHz fOSC1 XtalIN, XtalOUT oscillator pins (2fsc: PAL-M) 7.151 MHz fOSC1 XtalIN, XtalOUT oscillator pins (4fsc: PAL-M) 14.302 fOSC2 OSCIN, OSCOUT oscillator pins (LC oscillator) 2.0 Vp-p 2.0 2.5 Vp-p 5.0 Vp-p MHz 5 12 MHz Note: Extreme care must be used to prevent noise when the XtalIN pin is used in clock input mode. Electrical Characteristics at Ta = –30 to +70°C, and unless otherwise specified, with VDD1 = 5 V max Unit Input off leakage current Parameter Ileak1 CVIN 1 µA Output off leakage current Ileak2 CVOUT 1 µA Output high level voltage VOH1 LN21, SYNCJDG, CPDT, SEPOUT: VDD1 = 4.5 V, IOH = –1.0 mA Output low level voltage VOL1 LN21, SYNCJDG, CPDT, SEPOUT: VDD1 = 4.5 V, IOL = 1.0 mA Input current Operating current drain Sync level Pedestal level Color burst low level Color burst high level Background color low level Background color high level Symbol Conditions IIH RST, CS1, CS2, SIN, SCLK, CTRL1, SEPIN: VIN = VDD1 IIL CTRL1, OSCIN: VIN = VSS1 min typ 3.5 V 1.0 1 –1 V µA µA IDD1 VDD1: All outputs open, crystal: 7.159 MHz, LC: 8 MHz 30 mA IDD2 VDD2: VDD2 = 5 V 20 mA VSN VPD VCBL VCBH VRSL VRSH When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V 0.69 0.81 0.98 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V 0.89 1.01 1.13 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V 1.28 1.40 1.52 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V 1.47 1.59 1.71 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V 0.97 1.09 1.21 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V 1.16 1.28 1.40 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V 1.60 1.72 1.84 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V 1.79 1.91 2.03 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V 1.44 1.56 1.68 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V 1.63 1.75 1.87 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V 1.96 2.08 2.20 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V 2.16 2.28 2.40 V Continued on next page. No. 5213-3/16 LC74725, 74725M Continued from preceding page. Parameter Border level 0 Border level 1 Character level Symbol VBK0 VBK1 VCHA Conditions min typ When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V 1.43 1.55 1.67 max Unit V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V 1.61 1.73 1.85 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V 2.01 2.13 2.25 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V 2.18 2.30 2.42 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V 2.57 2.69 2.81 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V 2.76 2.88 3.00 V min typ Timing Characteristics at Ta = –30 to +70°C, VDD1 = 5 V ± 0.5 V Parameter Symbol Conditions max Unit OSD write (See Figure 1.) Minimum input pulse width Data setup time Data hold time One-word write time tW (SCLK) SCLK tW (CS1) CS1 (the period when CS1 is high) tSU (CS1) 200 ns 1 µs CS1 200 ns tSU (SIN) SIN 200 ns th (CS1) CS1 2 µs th (SIN) SIN 200 ns The time to write 8 bits of data 4.2 µs 1 µs tword twt The RAM data write time ESD read (See Figure 2 for the n-channel open-drain circuit.) tCKCY SCLK 2 ns tCKL SCLK 1 µs tCKH SCLK 1 µs Data setup time tICK SCLK 10 Output delay time tCKO CPDT Minimum input pulse width µs 0.5 µs Note: Follows the OSD timing for the CMOS output circuit type. Figure 1 OSD Serial Data Input Timing No. 5213-4/16 LC74725, 74725M Note: CPDT goes to the high-impedance state when CS2 is high. Figure 2 EDS Serial Output Test Conditions (N-Channel Open-Drain Circuit) Note: The O/E signal is output from the SYNCJDG pin when SEL0 is high. LN21 outputs the even field when MOD0 is low, and both fields when MOD0 is high. Figure 3 O/E and LN21 Output Timing No. 5213-5/16 LC74725, 74725M Note: When closed caption character data is extracted in NTSC-TV mode (MOD0 is high), the control microprocessor can determine whether the current field is an odd field or an even field by checking the signal level output by the SYNCJDG pin (when SEL0 is high) at the point it detects the rise of the LN21 signal. Figure 4 LC74725/M to Decoder LSI (or Microprocessor) Caption Data Transfer Technique 1 (This is the basic usage mode for these LSIs.) Caption data transfer to the data output buffer is synchronized with the falling edge of the pulse output from LN21. Therefore, the following software processing is required if the decoder LSI (or microprocessor) does not detect the fall of LN21. When MOD0 is low, since the data is output to the data buffer once (during the even field) in a single frame, the decoder LSI (or microprocessor) must perform the transfer control operation at least twice per frame (about 32 ms). When the transfer control operation is performed twice in the same frame, the second CPDT 16 bits of output data are all zeros. Therefore, the microprocessor must determine that the data for the next frame had not been transferred to the output buffer in this case. Note: The LC74725 hardware will not transfer data to the output buffer while CS2 is low. Therefore the decoder LSI (or microprocessor) must restore CS2 from the low level to the high level after completing a data transfer control cycle. This transfer technique (technique 2) cannot be used in NTSC-TV mode, i.e., when MOD0 is high. Figure 5 LC74725/M to Decoder LSI (or Microprocessor) Caption Data Transfer Technique 2 (When a port to detect the fall of LN21 cannot be allocated in the decoder LSI (or Microprocessor).) No. 5213-6/16 LC74725, 74725M System Block Diagram No. 5213-7/16 LC74725, 74725M Display Control Commands Display control commands have an 8-bit format and are transferred using the serial input function. Commands consist of a command identification code in the first byte and command data in the following bytes. The following commands are supported. ① ② ③ ④ ⑤ ⑥ COMMAND0: Display memory (VRAM) write address setup command COMMAND1: Display character data write command COMMAND2: Vertical display start position and vertical character size setup command COMMAND3: Horizontal display start position and horizontal character size setup command COMMAND4: Display control setup command COMMAND5: Display control setup command Display Control Command Table First byte Command Second byte Command identification code Data Data 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 COMMAND0 Set write address 1 0 0 0 V3 V2 V1 V0 0 0 0 H4 H3 H2 H1 H0 COMMAND1 Write character 1 0 0 1 0 0 0 0 at 0 c5 c4 c3 c2 c1 c0 1 0 1 0 0 VS 20 0 VS 10 0 FS VP 5 VP 4 VP 3 VP 2 VP 1 VP 0 1 0 1 1 EGP HS 20 0 HS 10 0 LC HP 5 HP 4 HP 3 HP 2 HP 1 HP 0 COMMAND4 Display control 1 1 0 0 TST MOD RAM ERS OSC STP SYS RST 0 EGL NON EG BK 1 BK 0 RV DSP ON COMMAND5 Synchronizing signal control 1 1 0 1 BCL PH RSN INT 0 0 0 MUT MOD 0 CTL 3 CTL 2 SEL 0 COMMAND2 Set vertical display start position and vertical character size COMMAND3 Set horizontal display start position and horizontal character size Once written, the command identification code in the first byte is stored until the next first byte is written. However, when the display character data write command (COMMAND1) is written, the LC74725/M locks into the display character data write mode, and another first byte cannot be written. When a high level is input to the CS pin, the LC74725/M is set to COMMAND0 (display memory write address setup mode). ① COMMAND0 (Display memory write address setup command) First byte Register content DA0 to DA7 Register name State 7 — 1 6 — 0 5 — 0 4 — 3 2 1 0 V3 V2 V1 V0 Function Note Command 0 identification code Set the display memory write address. 0 0 1 0 1 0 Display memory row address (0 to 9 hexadecimal) 1 0 1 No. 5213-8/16 LC74725, 74725M Second byte Register content DA0 to DA7 Register name State 7 — 0 6 — 0 5 — 0 4 H4 3 H3 2 H2 1 H1 0 H0 Function Note Second byte identification bit 0 1 0 1 0 1 Display memory column address (0 to 17 hexadecimal) 0 1 0 1 ② COMMAND1 (Display character data write setup command) First byte Register content DA0 to DA7 Register name State 7 — 1 6 — 0 5 — 0 4 — 1 3 — 0 2 — 0 1 — 0 0 — 0 Function Command 1 identification code Set up display character data write. Note When this command is input, the LC74725/M locks into the display character data write mode until the CS1 pin goes high. Second byte Register content DA0 to DA7 Register name 7 at 6 — 5 c5 4 c4 3 c3 2 c2 1 c1 0 c0 State Function 0 Character attribute off 1 Character attribute on Note 0 0 1 0 1 0 1 0 Character code (00 to 3F hexadecimal) 1 0 1 0 1 No. 5213-9/16 LC74725, 74725M ③ COMMAND2 (Vertical display start position and vertical character size setup command) First byte Register content DA0 to DA7 Register name State 7 — 1 6 — 0 5 — 1 4 — 0 3 — 0 2 VS20 1 — 0 VS10 Note Function Command 2 identification code Set the vertical display start position and vertical character size. 0 1H per dot 1 2H per dot Second line vertical character size 0 0 1H per dot 1 2H per dot First line vertical character size Second byte Register content DA0 to DA7 Register name 7 — 6 FS 5 VP5 (MSB) 4 VP4 3 VP3 2 VP2 1 VP1 0 VP0 (LSB) State Note Function 0 Second byte identification bit 0 Crystal oscillator frequency: 2fsc 1 Crystal oscillator frequency: 4fsc 0 If VS is the vertical display start position then: 1 VS = H × (2Σ 2nVPn) 0 H: the horizontal synchronization pulse period 5 n=0 1 0 The vertical display start position is set by the 6 bits VP0 to VP5. The weight of bit 1 is 2H. 1 0 1 0 1 0 1 ④ COMMAND3 (Horizontal display start position and horizontal character size setup command) First byte Register content DA0 to DA7 Register name State 7 — 1 6 — 0 5 — 1 4 — 1 3 EGP 2 HS20 1 — 0 HS10 Function Note Command 3 identification code Set the horizontal display start position and horizontal character size. 0 Correction: off 1 Correction: on 0 1 Tc per dot 1 2 Tc per dot Border specification when the horizontal double character size is used Second line horizontal character size 0 0 1 Tc per dot 1 2 Tc per dot First line horizontal character size No. 5213-10/16 LC74725, 74725M Second byte Register content DA0 to DA7 Register name 7 — 6 LC 5 HP5 (MSB) 4 HP4 3 HP3 2 HP2 1 HP1 0 HP0 (LSB) State 0 Function Note Second byte identification bit 0 An LC oscillator is used for the dot clock. 1 A crystal oscillator is used for the dot clock. Selects the dot clock used in horizontal character display. 0 1 0 1 0 1 0 1 If HS is the horizontal start position then: 5 HS = Tc × (2Σ 2nHPn) n=0 Tc: Period of the oscillator connected to OSCIN/OSCOUT in operating mode. The horizontal display start position is set by the 6 bits HP0 to HP5. The weight of bit 1 is 2Tc. 0 1 0 1 ⑤ COMMAND4 (Display control setup command) First byte Register content DA0 to DA7 Register name State 7 — 1 6 — 1 5 — 0 4 — 3 TSTMOD 2 RAMERS 1 OSCSTP 0 SYSRST Function Note Command 4 identification code Display control setup 0 0 Normal operating mode 1 Test mode This bit must be zero. 0 1 Erase display RAM (set to 3F hexadecimal) The RAM erase operation requires about 500 µs (It is executed in the DSPOFF state.) 0 Do not stop the crystal oscillator and LC oscillator circuits. 1 Stop the crystal oscillator and LC oscillator circuits. Valid when character display is off in external synchronization mode. Reset all registers and turn the display off. Reset occurs when the CS1 pin is low, and the reset is cleared when CS1 goes high. 0 1 Second byte Register content DA0 to DA7 Register name 7 — 6 EGL 5 NON 4 EG 3 BK1 2 BK0 1 0 RV DSPON State Function 0 Second byte identification bit 0 Border level 0 (VBK0) 1 Border level 1 (VBK1) 0 Interlaced (262.5H per field) 1 Noninterlaced (263H per field) 0 Border off 1 Border on 0 Blinking period: about 0.5 s 1 Blinking period: about 1.0 s 0 Blinking off 1 Blinking on 0 Reverse (character reversing) off 1 Reverse (character reversing) on 0 Character display off 1 Character display on Note Switches the border level Switches between interlaced and noninterlaced Switches the blinking period. When blinking is specified for reversed characters, the blinking will be between normal character and reversed character display. No. 5213-11/16 LC74725, 74725M ⑥ COMMAND5 (Display control setup command) First byte Register content DA0 to DA7 Register name State 7 — 1 6 — 1 5 — 0 4 — 1 3 BCL 2 1 0 Command 5 identification code Synchronizing signal control settings 0 Background color present 1 No background color (only the background level is set) 0 Green background 1 Blue background 0 External synchronizing signal detection control: Off 1 External synchronizing signal detection control: On Only valid in internal synchronization mode Background color switching (Only valid in NTSC mode) (In PAL-M mode, only blue is available as the background color.) PH RSN INT Note Function 0 External synchronization 1 Internal synchronization External synchronizing signal detection control. Determines when the signal goes from detected to undetected, and from undetected to detected. Switches between external and internal synchronization Second byte Register content DA0 to DA7 Register name State 7 — 0 6 — 0 5 — 0 4 MUT 3 MOD0 2 CTL3 1 CTL2 0 SEL0 Note Function Second byte identification bit 0 Normal output 1 CVIN is cut and CVOUT is fixed at the pedestal level. 0 Even field line 21 data extraction (VCR) 1 Both even and odd field line 21 data extraction (NTSC-TV) 0 Internal V separation used. 1 Internal V separation not used. 0 NTSC 1 PAL-M 0 External synchronizing signal detection output signal 1 O/E signal Switches CVOUT. Switches line 21 data extraction operation. Switches V separation usage. Switches between generation of NTSC and PAL-M signals. Switches SYNCJDG (pin 21) output. Note: The register states are all set to zero when the LC74725/M is reset with the RST pin. No. 5213-12/16 LC74725, 74725M Display Screen Structure The display consists of 10 lines of 24 characters each and thus up to 240 characters can be displayed. Enlarging the size of the characters reduces the number of characters that can be displayed to under 240 characters. Display memory addresses are specified as row (0 to 9 decimal) and column (0 to 23 decimal) addresses. Display Screen Structure (display memory addresses) No. 5213-13/16 LC74725, 74725M Composite Video Signal Output Level (internally generated level) CVOUT Output Level Waveform (VDD2 = 5.00 V) Output voltage ➀ [V] Output voltage ➁ [V] VCHA: Character 2.69 2.88 VRSH: Background color high 2.08 2.28 VCBH: Color burst high 1.72 1.91 VRSL: Background color low 1.56 1.75 VBK1: Border 2.13 2.30 VBK0: Border 1.55 1.73 VPD: Pedestal 1.40 1.59 VCBL: Color burst low 1.09 1.28 VSN: 0.81 1.01 Output level Sync VDD2 = 5.00 V No. 5213-14/16 LC74725, 74725M Application Circuit Examples (Connected to a Y/C1 chip) 1. External system clock input Note: Values listed are reference values. No. 5213-15/16 LC74725, 74725M 2. Crystal oscillator clock generation Note: Values listed are reference values. ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. No. 5213-16/16