SANYO LC74770

Ordering number : EN4248A
CMOS LSI
LC74770M
On-Screen Display Controller LSI
Overview
Package Dimensions
The LC74770M is a CMOS LSI that implements onscreen display, a function that displays characters and
patterns on display screens such as camcorder viewfinder
screens under microprocessor control. This LSI displays
12-dot by 18-dot characters.
unit: mm
3112-MFP24S
[LC74770M]
Features
• Display format: 24 characters by 12 rows (up to
288 characters)
• Characters displayed: Up to 288 characters
• Character format: 12 (horizontal) × 18 (vertical)
• Characters in font: 128
• Character sizes: Normal and double
• Initial display positions: 64 horizontal positions and
64 vertical positions
• Reverse video function: Characters can be displayed in
reverse video specified in units of individual characters.
• Blinking types: In character units in one of two periods,
1.0 second and 0.5 second, with a 50% duty.
• Outputs: Character and blanking data, with two output
systems for each
• External control input: 8-bit serial input format
• General-purpose output port: 4 bits (controlled from the
serial input data)
SANYO: MFP24S
Pin Assignment
Top view
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
31596HA (OT) No. 4248-1/11
LC74770M
Specifications
Absolute Maximum Ratings at Ta = 25°C
Ratings
Unit
Maximum supply voltage
Parameter
VDD max
Symbol
VDD
VSS – 0.3 to VSS + 7.0
V
Maximum input voltage
VIN max
All input pins
VSS – 0.3 to VDD + 0.3
V
BLK1, BLK2, CHA1, CHA2, P0 to P3, CKOUT
VSS – 0.3 to VDD + 0.3
Maximum output voltage
VOUT max
Allowable power dissipation
Conditions
Pd max
300
V
mW
Operating temperature
Topr
–30 to +70
°C
Storage temperature
Tstg
–40 to +125
°C
max
Unit
Allowable Operating Ranges at Ta = –30 to +70°C
Parameter
Symbol
Conditions
min
typ
Supply voltage
VDD
VDD
Input high-level voltage
VIH
RST, CS, SIN, SCLK, HSYNC, VSYNC
0.8 VDD
VIL
RST, CS, SIN, SCLK, HSYNC, VSYNC
VSS – 0.3
Input low-level voltage
Oscillator frequency
fOSC
4.5
OSCIN and OSCOUT oscillator pins
5
5.0
5.5
V
VDD + 0.3
V
0.2 VDD
7
10
V
MHz
Electrical Characteristics at Ta = –30 to +70°C, VDD = 5 V unless otherwise specified.
Parameter
Symbol
Conditions
Output high-level voltage
VOH
BLK1, BLK2, CHA1, CHA2, P0 to P3: VDD = 5.0 V,
IOH = –1.0 mA
Output low-level voltage
VOL
BLK1, BLK2, CHA1, CHA2, P0 to P3: VDD = 5.0 V,
IOL = 1.0 mA
IIH
RST, CS, SIN, SCLK, HSYNC, VSYNC: VIN = VDD
IIL
HSYNC, VSYNC: VIN = VSS
IDD
VDD: all outputs open, LC = 7 MHz
Input current
Operating current drain
min
typ
max
4.5
Unit
V
0.5
V
1
µA
10
mA
max
Unit
–1
µA
Timing Characteristics at Ta = –30 to +70°C, VDD = 5 ± 0.5 V
Parameter
Minimum input pulse width
Data setup time
Data hold time
Single word write time
Symbol
tW (SCLK)
Conditions
SCLK
tW (CS)
CS (the period that CS is high)
min
typ
200
ns
1
µs
ns
tSU (CS)
CS
200
tSU (SIN)
SIN
200
ns
th (CS)
CS
2
µs
th (SIN)
SIN
200
ns
The time to write 8 bits of data
4.2
µs
1
µs
tword
twt
The time to write RAM data
No. 4248-2/11
LC74770M
Serial Data Input Timing
Pin Functions
No.
Symbol
1
VSS
Pin
Function
Ground pin
Ground connection
LC oscillator pin
Connections for the coil and capacitor that form the oscillator that generates the character output
dot clock.
Clock output/test
output pin
Provides the OSCOUT output (when RST is low) and the test mode output.
2
OSCIN
3
OSCOUT
4
CKOUT/TEST
5
P0
General-purpose port 0
output pin
General-purpose port (PORT0) output
6
P1
General-purpose port 1
output pin
General-purpose port (PORT1) output
7
CS
Enable input pin
Enable input for the serial data input function. Serial data input is enabled when this pin is low.
A pull-up resistor is built in, i.e., this is a hysteresis input.
8
SCLK
Clock input pin
Clock input for the serial data input function. A pull-up resistor is built in,
i.e., this is a hysteresis input.
9
SIN
Data input pin
Serial data input. A pull-up resistor is built in, i.e., this is a hysteresis input.
10
VSS
Ground pin
Ground connection
11
NC
No connection
12
NC
No connection
13
NC
No connection
Unused pins.
These pins must be left open or connected to ground.
14
NC
15
CHA1
Character 1 output pin
No connection
16
BLK1
Blank 1 output pin
System 1 blank data output
17
CHA2
Character 2 output pin
System 2 character data output
18
BLK2
System 1 character data output
Blank 2 output pin
System 2 blank data output
General-purpose port (PORT3) output
19
P3
General-purpose port 3
output pin
20
P2
General-purpose port 2
output pin
General-purpose port (PORT2) output
21
VSYNC
Vertical synchronizing
signal input pin
Input for the vertical synchronizing signal (active low)
22
HSYNC
Horizontal synchronizing
signal input pin
Input for the horizontal synchronizing signal (active low)
23
RST
Reset input pin
System reset input (active low) A pull-up resistor is built in, i.e., this is a hysteresis input.
24
VDD
Power supply pin (+5 V)
Power supply (+5 V)
No. 4248-3/11
LC74770M
Block Diagram
Display Control Commands
Display control commands have an 8-bit format and are transferred using the serial input function. Commands consist of
a command identification code in the first byte and command data in the following bytes. The following commands are
supported.
1 COMMAND 0: Display memory (VRAM) write address setup command
2 COMMAND 1: Display character data write command
3 COMMAND 2: Vertical display start position and vertical character size setup command
4 COMMAND 3: Horizontal display start position and horizontal character size setup command
5 COMMAND 4: Display control setup command
6 COMMAND 5: System 2 (BLK2 and CHA2) output control (lines 1 to 6) and line size setting command
7 COMMAND 6: System 2 (BLK2 and CHA2) output control (lines 7 to 12) and general-purpose port setting command
No. 4248-4/11
LC74770M
Display Control Command Table
First byte
Command
Second byte
Command identification code
Data
Data
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
COMMAND 0
Write address
1
0
0
0
V3
V2
V1
V0
0
0
0
H4
H3
H2
H1
H0
COMMAND 1
Character write
1
0
0
1
0
0
0
0
at
c6
c5
c4
c3
c2
c1
c0
1
0
1
0
0
0
0
0
0
0
VP
5
VP
4
VP
3
VP
2
VP
1
VP
0
1
0
1
1
0
0
0
0
0
0
HP
5
HP
4
HP
3
HP
2
HP
1
HP
0
1
1
0
0
TST
RCL
OSC
RST
0
MD1
MD0
EG
BK
1
BK
0
RV
DSP
1
1
0
1
0
0
0
LS
0
0
LN
6
LN
5
LN
4
LN
3
LN
2
LN
1
1
1
1
0
P3
P2
P1
P0
0
0
LN
12
LN
11
LN
10
LN
9
LN
8
LN
7
COMMAND 2
Vertical display position
start position
COMMAND 3
Horizontal display position
start position
COMMAND 4
Display control
COMMAND 5
BLK2 and CHA2 output control:
lines 1 to 6, and line size control
COMMAND 6
BLK2 and CHA2 output control:
lines 7 to 12, and general-purpose
port control
Once written, the command identification code in the first byte is stored until the next first byte is written. However,
when the display character data write command (COMMAND1) is written, the LC74770M locks into the display
character data write mode, and another first byte cannot be written.
When a high level is input to the CS pin, the LC74770M is set to COMMAND0 (display memory write address setup
mode).
1
COMMAND 0 (Display memory write address setup command)
First byte
Register content
DA0 to DA7
Register name
State
7
—
1
6
—
0
5
—
0
4
—
3
2
1
0
V3
V2
V1
V0
Function
Note
Command 0 identification code
Sets the display memory write address.
0
0
1
0
1
0
Display memory address (0 to B hexadecimal)
1
0
1
No. 4248-5/11
LC74770M
Second byte
Register content
DA0 to DA7
Register name
State
7
—
0
6
—
0
5
—
0
4
H4
3
H3
2
H2
1
H1
0
H0
Function
Note
Second byte identification bit
0
1
0
1
0
1
Display memory address (0 to 17 hexadecimal)
0
1
0
1
Note: All registers are set to 0 when the LC74770M is reset by the RST pin.
2
COMMAND 1 (Display character data write setup command)
First byte
Register content
DA0 to DA7
Register name
State
7
—
1
6
—
0
5
—
0
4
—
1
3
—
0
2
—
0
1
—
0
0
—
0
Function
Command 1 identification code
Sets up display character data write.
Note
When this command is input, the
LC74770M locks into the display
character data write mode until the CS
pin goes high.
Second byte
Register content
DA0 to DA7
Register name
7
at
6
c6
5
c5
4
c4
3
c3
2
c2
1
c1
0
c0
State
Function
0
Character attribute off
1
Character attribute on
Note
0
1
0
1
0
1
0
1
Character code (00 to 7F hexadecimal)
0
1
0
1
0
1
Note: All registers are set to 0 when the LC74770M is reset by the RST pin.
No. 4248-6/11
LC74770M
3
COMMAND 2 (Vertical display start position setup command)
First byte
Register content
DA0 to DA7
Register name
State
7
—
1
6
—
0
5
—
1
4
—
0
3
—
0
2
—
0
1
—
0
0
—
0
Function
Note
Command 2 identification code
Sets the vertical display start position.
Second byte
Register content
DA0 to DA7
Register name
State
Function
7
—
0
6
—
0
VP5
(MSB)
0
If VS is the vertical display start position then:
5
1
VS = H × (Σ 2nVPn)
4
VP4
3
VP3
2
VP2
1
VP1
0
VP0
(LSB)
0
1
Note
Second byte identification bit
5
n=0
H: the horizontal synchronization pulse period
0
The vertical display start position is set
by the 6 bits VP0 to VP5.
1
0
The weight of bit 1 is 1H.
1
0
1
0
1
Note: All registers are set to 0 when the LC74770M is reset by the RST pin.
4
COMMAND 3 (Horizontal display start position setup command)
First byte
Register content
DA0 to DA7
Register name
State
7
—
1
6
—
0
5
—
1
4
—
1
3
—
0
2
—
0
1
—
0
0
—
0
Function
Note
Command 3 identification code
Sets the horizontal display start position.
No. 4248-7/11
LC74770M
Second byte
Register content
DA0 to DA7
Register name
State
7
—
0
6
—
0
5
HP5
(MSB)
0
4
HP4
3
HP3
2
HP2
1
HP1
0
HP0
(LSB)
Function
Note
Second byte identification bit
1
0
1
0
1
0
1
If HS is the horizontal start position then:
5
HS = Tc × (Σ 2nHPn)
The horizontal display start position is
set by the 6 bits HP0 to HP5.
Tc: Period of the oscillator connected to OSCIN/OSCOUT in
operating mode.
The weight of bit 1 is 1Tc.
n=0
0
1
0
1
Note: All registers are set to 0 when the LC74770M is reset by the RST pin.
5
COMMAND 4 (Display control setup command)
First byte
Register content
DA0 to DA7
Register name
State
7
—
1
6
—
1
5
—
0
Function
Command 4 identification code
Sets up display control.
4
—
0
3
TST
(TSTMOD)
0
Normal operating mode
1
Test mode
2
RCL
(RAMCLR)
0
1
Erase display RAM (Data is set to 7F hexadecimal.)
1
OSC
(OSCSTP)
0
Do not stop the LC oscillator circuit.
1
Stop the LC oscillator circuit.
RST
(SYSRST)
0
0
1
Note
Reset all registers and turn the display off.
This bit must be zero.
Valid when display is off.
This bit must be zero.
The LSI is reset when the CS pin is low,
and the reset is cleared when that pin
goes high.
No. 4248-8/11
LC74770M
Second byte
Register content
DA0 to DA7
Register name
7
—
6
MD1
5
MD0
4
EG
3
BK1
2
BK0
1
RV
0
DSP
(DSPON)
State
Function
0
Second byte identification bit
0
The blank output also outputs character data.
1
The blank output only outputs blank data.
0
The system 1 output outputs all lines.
1
The system 1 output only outputs lines not output by system 2.
0
Border off
1
Border on
0
Blinking period set to about 0.5 second.
1
Blinking period set to about 1 second.
0
Blinking off
1
Blinking on
0
Reverse video off
1
Reverse video on
0
Character display off
1
Character display on
Note
Blank output control
Output system 1 control
Blinking period switching
Blinking of reverse video characters
consists of alternation between normal
and reverse video.
Note: All registers are set to 0 when the LC74770M is reset by the RST pin.
6
COMMAND 5 (System 2 output control and line size setting command)
First byte
Register content
DA0 to DA7
Register name
State
7
—
1
6
—
1
5
—
0
4
—
1
3
—
0
2
—
0
1
—
0
LS
Function
Note
Command 5 identification code
Controls output system 2 and sets the line size.
(Output control for CHA2 and BLK2)
(Line size control)
0
0
Output line selection
1
Character size selection (line units)
The line is selected in the second byte.
Second byte
Register content
DA0 to DA7
Register name
State
7
—
0
6
—
0
5
LN6
4
3
LN5
LN4
2
LN3
1
LN2
0
LN1
Function
Note
Second byte identification bit
0
The sixth line of data is not output to CHA2 and BLK2.
1
The sixth line of data is output to CHA2 and BLK2.
0
The fifth line of data is not output to CHA2 and BLK2.
1
The fifth line of data is output to CHA2 and BLK2.
0
The fourth line of data is not output to CHA2 and BLK2.
1
The fourth line of data is output to CHA2 and BLK2.
0
The third line of data is not output to CHA2 and BLK2.
1
The third line of data is output to CHA2 and BLK2.
0
The second line of data is not output to CHA2 and BLK2.
1
The second line of data is output to CHA2 and BLK2.
0
The first line of data is not output to CHA2 and BLK2.
1
The first line of data is output to CHA2 and BLK2.
Used for the line output setting when LS
is low.
Used for the line size setting when LS is
high.
Note:
LS = 1: Set the line size.
LS = 0: Specifies line output.
Note: All registers are set to 0 when the LC74770M is reset by the RST pin.
No. 4248-9/11
LC74770M
7
COMMAND 6 (System 2 output control and general-purpose port setting command)
First byte
Register content
DA0 to DA7
Register name
State
7
—
1
6
—
1
5
—
1
4
—
0
3
P3
2
1
0
P2
P1
P0
0
Function
Note
Command 6 identification code
Controls output system 2 output.
(Output control for CHA2 and BLK2)
(General-purpose port output control)
Sets the general-purpose port output (P3) to low.
1
Sets the general-purpose port output (P3) to high.
0
Sets the general-purpose port output (P2) to low.
1
Sets the general-purpose port output (P2) to high.
0
Sets the general-purpose port output (P1) to low.
1
Sets the general-purpose port output (P1) to high.
0
Sets the general-purpose port output (P0) to low.
1
Sets the general-purpose port output (P0) to high.
Second byte
Register content
DA0 to DA7
Register name
State
7
—
0
6
—
0
5
LN12
4
3
LN11
LN10
2
LN9
1
LN8
0
LN7
Function
Note
Second byte identification bit
0
The twelfth line of data is not output to CHA2 and BLK2.
1
The twelfth line of data is output to CHA2 and BLK2.
0
The eleventh line of data is not output to CHA2 and BLK2.
1
The eleventh line of data is output to CHA2 and BLK2.
0
The tenth line of data is not output to CHA2 and BLK2.
1
The tenth line of data is output to CHA2 and BLK2.
0
The ninth line of data is not output to CHA2 and BLK2.
1
The ninth line of data is output to CHA2 and BLK2.
0
The eighth line of data is not output to CHA2 and BLK2.
1
The eighth line of data is output to CHA2 and BLK2.
0
The seventh line of data is not output to CHA2 and BLK2.
1
The seventh line of data is output to CHA2 and BLK2.
Used for the line output setting when LS
is low.
Used for the line size setting when LS is
high.
Note:
LS = 1: Set the line size.
LS = 0: Specifies line output.
Note: All registers are set to 0 when the LC74770M is reset by the RST pin.
No. 4248-10/11
LC74770M
Display Screen Structure
The display consists of 12 lines of 24 characters each and thus up to 288 characters can be displayed.
Display memory addresses are specified as row (0 to B hexadecimal) and column (0 to 17 hexadecimal) addresses.
Display Screen Structure (display memory addresses)
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of March, 1996. Specifications and information herein are subject to
change without notice.
PS No. 4248-11/11