FUJITSU MB90092_01

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-28824-3E
ASSP for Screen Display Control
CMOS
ON-Screen Display Controller
MB90092
■ DESCRIPTION
The MB90092 is the display controller for displaying text and graphics on the TV screen.
The MB90092 incorporates display memory (VRAM), a font memory interface, and a video signal generator,
allowing text and graphics to be displayed in conjunction with a small number of external components.
The MB90092 can provide two screens, called the main screen and the sub-screen, either independently or
overlayed one on top of the other.
The main screen consists of 24 characters by 12 lines and allows data to be set for each character. The subscreen consists of 32 characters by 12 lines or up to 32 characters by 16 lines. Data can be set either for each
line in the former configuration or collectively for the entire screen in the latter configuration.
For output of video signals, the MB90092 has the composite video signal, Y/C-separated video signal, and RGB
digital output pins. The MB90092 also has video signal input pins, allowing superimpose display over either
composite video signals and Y/C-separated video signals.
■ PACKAGE
80-pin Plastic QFP
(FPT-80P-M06)
MB90092
■ FEATURES
• Main Screen Display
• Screen display capacity:24 characters × 12 lines (up to 288 characters)
• Character dot configuration:24 × 32 dots (per character)
• Character types: 16384 different characters (when using a 16 M bit external clock)
• Character sizes: Standard, double width, double height, double width × double height,
quadruple width × double height (Setting possible for each line)
• Display position control :Horizontal display position
:Set in 1/3-character units
Vertical display position
:Set in raster units
Line spacing control
:Set in raster units (0 to 15 rasters)
• Display priority control:Capable of controlling display priority over the sub-screen (for each line)
• Sub-Screen Display
Screen display position: Settable horizontally and vertically in 2-dot units
• Normal screen mode:Screen capacity:32 characters × 12 lines (up to 384 characters)
256 horizontal dots × 384 vertical dots (graphics characters only) (The
actual display screen depends on the television system and dot clock
frequency.) Normal character/graphic character display selectable for
each line (Header display character code is specified for each line.)
Character string length:Selectable from among 1, 2, 4, 8, 16, 24, and 32 digits
• Full-screen mode
Screen capacity: 32 characters × 16 lines (up to 512 characters)
256 horizontal dots × 512 vertical dots
(The actual display screen depends on the television
system and dot clock frequency.)
Virtual screen capacity:Mode A:32 characters × 16 lines (× 32 screens)
256 horizontal dots × 512 vertical dots
Mode B:512 characters × 32 lines
4096 horizontal dots × 1024 vertical dots
Screen Background Display
Screen background color: 8 colors (set for the entire screen)
Analog Inputs
• Composite video signal input
• Y/C-separated inputs
Analog Outputs
• Composite video signal output
• Y/C-separated outputs
Digital Outputs
• G (Green), R (Red), and B (Blue) output
• VOC (character) output, VOB (character + background) output
• Characters, character background, line background, and screen background each capable of being displayed
in eight colors
Internal Synchronization Control (Video Signal Generator)
• Internal video signal generator supporting the NTSC and PAL systems
• Interlaced/noninterlaced display selectable
(Continued)
2
MB90092
(Continued)
External Synchronization Control
• Separated sync signal input/composite sync signal input selectable
External Interface
• 8-bit serial inputs (3 signal input pins)
Chip select: CS
Serial clock: SCLK
Serial data: SIN
Package
• QFP-80
Miscellaneous
• Internal power-on reset circuit
3
MB90092
■ PIN ASSIGNMENT
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
XD
EXD
TEST
TSC
VCC
ADR20
ADR19
ADR18
ADR17
ADR16
ADR15
ADR14
ADR13
ADR12
ADR11
VSS
(TOP VIEW)
TESTI
VOC
VOB
VSS
B
R
G
CS
SCLK
SIN
VCC
EXHSYN
EXVSYN
HSYNC
VSYNC
VBLNK
EXS
XS
TEST1
FSCO
CBCK
PDS
VSS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
TEST2
TEST3
TEST4
TEST5
AVSS
AVSS
YOUT
YIN
AVCC2
COUT
CIN
AVSS
VOUT
VKIN
VKOUT
VIN
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
AVSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(FPT-80P-M06)
4
ADR10
ADR9
VCC
ADR8
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
VSS
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
READ
VCC
AVCC1
MB90092
■ PIN DESCRIPTION
Pin no.
Pin name
I/O
Circuit
type
Function
1
TESTI
I
B
Test signal input pin. Input High level signal during normal operation.
This pin also can be used as a reset signal input pin by Low-level input
to the TEST pin. That is effective only after release of power-on reset.
This pin is a hysteresis input with an internal pull-up resistor.
2
VOC
O
C
Character interval signal output pin.
The output signal represents the character dot output interval.
3
VOB
O
C
Character/background internal signal output pin.
During internal synchronization control operation, the output signal represents the character, character background, line background, or screen
background output interval.
5
6
7
B
R
G
O
C
Color signal output pins.
These pins output the character, character background, line background, and screen background color signals.
8
CS
I
B
Chip select pin.
For serial transfer, set this pin to the Low level.
This pin is also used to release a power-on reset.
The pin is a hysteresis input with an internal pull-up resistor.
9
SCLK
I
B
Shift clock input pin for serial transfer.
This pin is a hysteresis input with an internal pull-up resistor.
10
SIN
I
B
Serial data input pin.
The pin is a hysteresis input with an internal pull-up resistor.
B
External horizontal sync signal input pin.
Input negative logic signal.
This pin can also serve as a composite sync signal input pin depending
on the internal register setting.
The pin is a hysteresis input with an internal pull-up resistor.
B
External vertical sync signal input pin.
Input negative logic signal.
Input to this pin is disabled when composite sync signal input has been
selected by setting the internal register. The pin is a hysteresis input with
an internal pull-up resistor.
C
Horizontal sync signal output pin.
This pin can also output composite sync signals depending on the internal register setting.
The pin outputs the signal (FSC) resulting from dividing the 4FSC clock
frequency by setting the TEST pin to the Low level.
12
13
14
EXHSYN
EXVSYN
HSYNC
I
I
O
15
VSYNC
O
C
Vertical sync signal output pin.
This pin is fixed at the High level when composite sync signal output has
been selected by setting the internal register.
The pin outputs the dot clock oscillator signal when the TEST pin goes
into Low.
16
VBLNK
O
C
Vertical blanking interval signal output pin.
This pin outputs the Low-level signal in the vertical blanking interval.
(Continued)
5
MB90092
Circuit
type
Function
I
O
H
External circuit pins for color burst clock generator.
Connect an external crystal oscillator (14.31818 MHz for NTSC or
17.734475 MHz for PAL) and load capacitance (C) to these pins to form
a crystal oscillator circuit.
FSCO
O
C
Internal color burst clock output pin.
This pin controls internal color burst clock output depending on the FO
bit of command 7.
21
CBCK
I
G
External color burst clock input pin
22
PDS
O
D
Pin for output of the result of color burst clock phase comparison
31
YOUT
O
F
Luminance signal output pin.
This pin outputs a signal of 2 VP-P (pedestal level 1.57 V, sync tip level 1
V).
32
YIN
I
E
Luminance signal input pin for superimpose display.
This pin inputs a DC-reproduced (DC-clamped) signal of 2 VP-P (pedestal
level 1.57 V, sync tip level 1 V).
34
COUT
O
F
Saturation signal output pin.
This pin outputs a signal at 1.57 VDC and a color burst signal amplitude
of 0.57 VP-P.
35
CIN
I
E
Saturation signal input pin for superimpose display.
This pin inputs a signal at 1.57 VDC and a color burst signal amplitude
of 0.57 VP-P.
37
VOUT
O
F
Composite video signal output pin.
This pin outputs a signal of 2 VP-P (pedestal level 1.57 V, sync tip level
1 V).
E
Background level control input pin for halftone background display of external input composite video signals (input to the VIN pin and output
from the VOUT pin).
Halftone background display is controlled by setting the KID bit of command 5 to “1”.
Pin no.
Pin name
I/O
17
18
EXS
XS
20
38
VKIN
I
39
VKOUT
O
F
Background level control output pin for halftone background display of
external input composite video signals (input to the VIN pin and output
from the VOUT pin).
Halftone background display is controlled by setting the KID bit of command 5 to “1”.
40
VIN
I
E
Composite video signal input pin for superimpose display.
This pin inputs a DC-reproduced (DC-clamped) signal of 2 VP-P (pedestal
level 1.57 V, sync tip level 1 V).
D
External font memory read control pin.
This pin outputs the Low-level signal in the font memory read period.
The pin enters the high impedance state when the TSC pin inputs a
Low-level signal.
43
READ
O
(Continued)
6
MB90092
Pin no.
44
45
46
47
48
49
50
51
53
54
55
56
57
58
59
60
61
63
64
66
67
68
69
70
71
72
73
74
75
Pin name
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
ADR0
ADR1
ADR2
ADR3
ADR4
ADR5
ADR6
ADR7
ADR8
ADR9
ADR10
ADR11
ADR12
ADR13
ADR14
ADR15
ADR16
ADR17
ADR18
ADR19
ADR20
I/O
Circuit
type
I
A
External font memory data input pins.
These pins are inputs with an internal pull-up resistor.
D
External font memory address output pins.
These pins enter the high impedance state when the TSC pin inputs a
Low-level signal.
ADR0
ADR1
ADR2
Raster address
ADR3
ADR4
∗1
∗2
ADR5
M0, SM0
ADR6
M1, SM1
ADR7
M2, SM2
ADR8
M3, SM3
Character code (Lower bits)
ADR9
M4, SM4
ADR10
M5, SM5
ADR11
M6, SM6
ADR12
Data distinction bits
ADR13
(12,13 = 00: Left, 10: Center, 01: Right)
ADR14
M7, SM7
ADR15
M8, SM8
ADR16
M9, SM9
ADR17
MA, SMA
Character code (Higher bits)
ADR18
MB, SMB
ADR19
MC, SMC
ADR20
MD, SMD
*1: M0 to MD are control bits for main screen character
control data setting (the commands 1-1 and 2-1)
*2: SM0 to SMD are control bits for sub-screen character
control data setting (the commands 1-2 and 2-2)
O
Function
77
TSC
I
B
Tristate control input pin for external font memory control bus.
When this pin inputs a Low-level signal, the ADR0 to ADR20 pins and
the READ pin enter the high impedance state.
The pin is a hysteresis input with an internal pull-up resistor.
78
TEST
I
B
Test signal input pin.
This pin usually inputs a High-level (fixed) signal.
79
80
EXD
XD
I
O
I
External circuit pins for display dot clock generator.
Connect these pins to external “L” and “C” to form an LC oscillator circuit.
(Continued)
7
MB90092
(Continued)
Pin name
I/O
Circuit
type
19
25
26
27
28
TEST1
TEST2
TEST3
TEST4
TEST5
O
—
Leave these pins unconnected.
11
42
62
76
VCC
—
—
Power-supply pins (+5 V)
4
23
52
65
VSS
—
—
Ground pins
41
AVCC1
—
—
Analog power pin for composite video signals (VIN-VOUT)
33
AVCC2
—
—
Analog power pin for luminance (YIN-YOUT) and chroma (CIN-COUT)
signals
24
29
30
36
AVSS
—
—
Analog circuit ground pins.
Set these pins to the same level as the VSS pin.
Pin no.
8
Function
MB90092
■ I / O CIRCUIT TYPE
Type
Circuit
Remarks
A
CMOS level input
With pull-up resistor: approximately 50 kΩ
B
CMOS level, hysteresis input
With pull-up resistor: approximately 50 kΩ
C
CMOS output
D
CMOS three state output
(Continued)
9
MB90092
(Continued)
Control signal
E
Analog input
Analog input
CMOS analog SW
Control signal
F
Analog output
Analog output
CMOS analog SW
Control signal
G
CMOS level, hysteresis input
XS
H
Crystal oscillation circuit
EXS
Control signal
XD
EXD
I
LC oscillation circuit
Control signal
10
Inside
clock signal
MB90092
■ BLOCK DIAGRAM
SIN
SCLK
CS
TEST
Serial input
control
Each control and data
VIN
YIN
CIN
Analog
SW
VKOUT
VKIN
EXHSYN
EXVSYN
HSYNC
VSYNC
VBLNK
VOUT
YOUT
COUT
H/V separation
circuit
NTSC/PAL
signal
generator
Video signal
generator
B
R
G
VOB
VOC
Display memory
control
Output
control
Display memory
(VRAM)
Font
memory
control
ADR0 ~ ADR20
READ
DA0 ~ DA7
TSC
Phase
comparator
(color burst)
CBCK
PDS
FSCO
XS
EXS
4FSC clock
oscillator
Each block
XD
EXD
Dot clock
oscillator
Each block
11
MB90092
■ DISPLAY CONTROL COMMANDS
Command
no.
Function
First byte
Second byte
Command code/data
Data
76543
2
1
0
7
6
5
4
3
0
VRAM address setting
10000 VSL RA8 RA7
0
RA6 RA5 CA4 CA3
1-1
Main screen
character control
data setting 1*
10001
MA
MB
AT
0
CG
CR
CB
MC
2-1
Main screen
character control
data setting 2
10010
M9
M8
M7
0
M6
M5
M4
M3
1-2
Sub-screen line
control data setting
1
10001 SMA SMB
0
0
2-2
Sub-screen line
control data setting
2
10010 SM9 SM8 SM7
0
1-3
Main screen line
control data setting
1
10001 OF1 OF0
0
0
0
0
0
2-3
Main screen line
control data setting
2
10010
G2
G1
G0
0
SOC
VD
3
VRAM write
control
10011
FIL
0
0
0
0
4
Screen control 1
10100
IE
IN
EB
0
EO
5
Screen control 2
10101 KID APC GYZ
6
Main screen line
control
10110
G2
G1
7
Main screen vertical
display position
control
10111
EC
8
Main screen horizontal
display position control
11000
9
Main screen
display mode
control
10
2
1
0
CA2
CA1
CA0
BG
BR
BB
(GR)* (BS)* (MD)*
M1
M0
SCG SCR SCB SMC SGR
SDC
SMD
SM6 SM5 SM4 SM3
SM2
SM1
SM0
PC
PG
PR
PB
DG
KC
KG
KR
KB
0
0
0
0
0
0
CM
ZM
NP
P2
P0
DC
0
BH2 BH1 BH0
W3
W2
W1
W0
G0
0
SOC
VD
DG
N3
N2
N1
N0
LP
FO
0
0
Y5
Y4
Y3
Y2
Y1
Y0
SC
0
FC
0
0
X5
X4
X3
X2
X1
X0
11001
0
0
GRM
0
RP1 RP0 S16
SF1
Color control
11010
0
0
RB
0
BK
UC
11
Sub-screen
control
11011 SG2 SG1 SG0
0
0
12
Sub-screen vertical
display position
control
11100 SGA
13
Sub-screen horizontal
display position control
11101
14
(Reserved)
15
(Reserved)
CC
BC
M2
DW4 RM1
UG
SCC SBC SGC SBG
RM0
UR
UB
SBR
SBB
0
SY7
0
SY6 SY5 SY4 SY3
SY2
SY1
SY0
0
SX8
SX7
0
SX6 SX5 SX4 SX3
SX2
SX1
SX0
11110
—
—
—
0
—
—
—
—
—
—
—
11111
—
—
—
0
—
—
—
—
—
—
—
*: Parenthesized bit names are used for extended graphics mode.
Note: DC bit of screen control 1 (command 4) is initialized at “0” and display is off by reset. All command data and
all VRAM are needed to set after release of power-on reset.
12
MB90092
■ COMMAND
1. VRAM Address Setting (Command 0)
MSB
First byte
LSB
1
0
0
0
0
VSL
RA8
RA7
LSB
MSB
Second byte
0
RA6
RA5
CA4
CA3
CA2
CA1
CA0
VSL
: VRAM write control
RA8 to RA5 : VRAM row address setting (0H to BH)
CA4 to CA0 : VRAM column address setting (00H to 17H)
2. VRAM Data Settings 1 and 2 (Commands 1 and 2)
(1) Writing main screen character control data (when command 0: VSL = 0)
• Command 1-1 (Main screen character control data setting 1)
MSB
First byte
LSB
1
0
0
0
1
MA
MB
LSB
MSB
Second byte
AT
0
CG
CR
CB
MC
BG
(GR)
BR
(BS)
BB
(MD)
*
*: Parenthesized bit names are used for extended graphics mode.
• Command 2-1 (Main screen character control data setting 2)
MSB
First byte
LSB
1
0
0
1
0
M9
M8
M7
LSB
MSB
Second byte
0
M6
(MD), MC to M0
AT
CG, CR, CB
BG, BR, BB
(GR)
(BS)
M5
M4
M3
M2
M1
M0
: Character code
: Specify character attribute display.
: Character colors
: Character background colors
: Specify normal character/graphic character display.
: Specify shaded background display.
13
MB90092
(2) Writing sub-screen line control data (when command 0: VSL = 1, CA0 = 0)
• Command 1-2 (Sub-screen line control data setting 1)
MSB
First byte
LSB
1
0
0
0
1
SMA
SMB
LSB
MSB
Second byte
0
0
SCG
SCR
SCB
SMC
SGR
SDC
SMD
• Command 2-2 (Sub-screen line control data setting 2)
MSB
First byte
LSB
1
0
0
1
0
SM9
SM8
LSB
MSB
Second byte
0
SM6
SMD to SM0
SDC
SGR
SCG to SCB
SCG
SCR, SCB
14
SM7
SM5
SM4
SM3
SM2
SM1
SM0
: Sub-screen line first character code
: Sub-screen line output control
: Sub-screen line character display control
: Sub-screen line character colors (when SGR = 0)
: Sub-screen line graphic color transparency control (when SGR = 1)
: Sub-screen line graphic color phase control (when SGR = 1)
MB90092
(3) Writing main screen control data (when command 0: VSL = 1, CA0 = 1)
• Command 1-3 (Main screen line control data setting 1)
MSB
First byte
LSB
1
0
0
0
1
OF1
OF0
0
LSB
MSB
Second byte
0
0
0
0
PC
PG
PR
PB
• Command 2-3 (Main screen line control data setting 2)
MSB
First byte
LSB
1
0
0
1
0
G2
G1
G0
LSB
MSB
Second byte
0
SOC
OF1, OF0
PC
PG, PR, PB
G2, G1, G0
SOC
VD
DG
KC
KG, KR, KB
VD
DG
KC
KG
KR
KB
: Character color phase control
: Shaded pattern background color/monochrome control
: Shaded pattern background color
: Character size control
: Output priority control
: Video signal output control
: Digital signal output control
: Line background color/monochrome control
: Line background color
3. VRAM Write Control (Command 3)
MSB
First byte
LSB
1
0
0
1
1
FIL
0
0
LSB
MSB
Second byte
0
0
0
0
0
0
0
0
FIL: VRAM fill control
15
MB90092
4. Screen Control 1 (Command 4)
MSB
First byte
LSB
1
0
1
0
0
IE
IN
LSB
MSB
Second byte
EB
0
IE
IN
EB
EO
CM
ZM
NP
P2, P0
DC
EO
CM
ZM
NP
P2
P0
DC
: Internal/external synchronization control
: Interlaced/noninterlaced display control
: Screen background display control
: Field control
: Color/monochrome display control
: Zoom-in control
: NTSC/PAL control
: Pattern background control
: Display control
5. Screen Control 2 (Command 5)
MSB
First byte
LSB
1
0
1
0
1
KID
APC
GYZ
LSB
MSB
Second byte
0
BH2
KID
APC
GYZ
BH2 to BH0
W3 to W0
BH1
BH0
W2
W1
: Halftone control
: Reserve*
: Main screen line enlargement control
: Reserve*
: Main screen line spacing control
*: Reserve must be set at “ 0 ”.
16
W3
W0
MB90092
6. Main Screen Line Control (Command 6)
MSB
First byte
LSB
1
0
1
1
0
G2
G1
G0
LSB
MSB
Second byte
0
SOC
G2 to G0
SOC
VD
DG
N3 to N0
VD
DG
N3
N2
N1
N0
: Character size control
: Output priority control
: Video signal output control
: Digital signal output control
: Line specification
7. Main Screen Vertical Display Position Control (Command 7)
MSB
First byte
LSB
1
0
1
1
1
EC
LP
FO
LSB
MSB
Second byte
0
0
EC
LP
FO
Y5 to Y0
Y5
Y4
Y3
Y2
Y1
Y0
: Sync signal output control
: Simple NTSC/PAL control
: Color phase signal output control
: Main screen vertical display position control
8. Main Screen Horizontal Display Position Control (Command 8)
MSB
First byte
LSB
1
1
0
0
0
SC
0
FC
LSB
MSB
Second byte
0
SC
FC
X5 to X0
0
X5
X4
X3
X2
X1
X0
: Sync signal input control
: Sync signal input 3 µs filter control
: Main screen horizontal display position control
17
MB90092
9. Main Screen Display Mode Control (Command 9)
MSB
First byte
LSB
1
1
0
0
1
0
0
LSB
MSB
Second byte
GRM
0
RP1
RP0
S16
SF1
DW4
RM1
RM0
GRM: Main screen display mode control
RP1, RPO : Reserve 4*
S16
: Reserve 3*
SF1
: Reserve 2*
DW4
: Reserve 1*
RM1, RM0 : Reserve 0*
*: Reserve 0 to reserve 4 must be set at “0”.
10. Color Control (Command 10)
MSB
First byte
LSB
1
1
0
1
0
0
0
RB
LSB
MSB
Second byte
0
RB
BK
CC
BC
BK
CC
BC
UC
UG
UR
UB
: Main screen solid-fill background display control
: Main screen blink display control
: Main screen character color/monochrome control
: Main screen character background color/monochrome control
(Main screen graphic color/monochrome control)
UC
: Screen background color/monochrome control
UG, UR, UB : Screen background color
18
MB90092
11. Sub-Screen Control (Command 11)
MSB
First byte
LSB
1
1
0
1
1
SG2
SG1
LSB
MSB
Second byte
SG0
0
0
SCC
SG2 to SG0
SCC
SBC
SGC
SBG, SBR, SBB
SBC
SGC
SBG
SBR
SBB
: Sub-screen configuration control
: Sub-screen character color/monochrome control
: Sub-screen character background color/monochrome control
: Sub-screen graphic color/monochrome control
: Sub-screen pattern background color
12. Sub-Screen Vertical Display Position Control (Command 12)
MSB
First byte
LSB
1
1
1
0
0
SGA
0
LSB
MSB
Second byte
SY7
0
SY6
SY5
SY4
SY3
SY2
SY1
SY0
SGA
: Sub-screen full-screen mode control
SY7 to SY0 : Sub-screen vertical display position
13. Sub-Screen Horizontal Display Position Control (Command 13)
MSB
First byte
LSB
1
1
1
0
1
0
SX8
LSB
MSB
Second byte
SX7
0
SX6
SX5
SX4
SX3
SX2
SX1
SX0
SX8 to SX0 : Sub-screen horizontal display position
19
MB90092
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Symbol
Unit
Remarks
Min.
Max.
VCC
VSS – 0.3
VSS + 7.0
V
*1
AVCC1
VSS – 0.3
VSS + 7.0
V
*1
AVCC2
VSS – 0.3
VSS + 7.0
V
*1
VIN
VSS – 0.3
VSS + 7.0
V
*2
VOUT
VSS – 0.3
VSS + 7.0
V
*2
Power consumption
Pd
—
600
mW
Operating temperature
Ta
–40
+85
°C
Tstg
–55
+150
°C
Supply voltage
Input voltage
Output voltage
Storage temperature
*1: AVSS and VSS must have equal potential.
*2: Neither VIN nor VOUT must exceed “VCC + 0.3 V.”
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
(VSS = AVSS = 0 V)
Parameter
Supply voltage
“H” level input voltage
“L” level input voltage
Operating temperature
Analog input voltage
Value
Symbol
Unit
Remarks
Min.
Max.
VCC
4.5
5.5
V
Specification guarantee
range
AVCC1
4.5
5.5
V
*1, *2
AVCC2
4.5
5.5
V
*1, *3
VIHS1
2.2
VCC + 0.3
V
DA0 to DA7
VIHS2
0.8 × VCC
VCC + 0.3
V
Except DA0 to DA7
VILS1
–0.3
+ 0.8
V
DA0 to DA7
VILS2
–0.3
0.2 × VCC
V
Except DA0 to DA7
Ta
–40
+85
°C
AVIN
0
VCC
V
*1: AVSS and VSS must have equal potential.
*2: “AVCC1 = AVSS” is allowed if composite video signals (VIN-VOUT pins) are not used.
*3: “AVCC2 = AVSS” is allowed if Y/C-separated video signals (YIN-YOUT and CIN-COUT pins) are not used.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
20
MB90092
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(Ta = –40°C to +85°C, VSS = AVSS = 0 V)
Parameter
Symbol
Pin
Conditions
Value
Unit
Min.
Typ.
Max.
VCC = 4.5 V
IOH = –2 mA
4.0
—
—
V
VCC = 4.5 V
IOL = 4.0 mA
—
—
0.4
V
IIL
TESTI, CS,
SCLK, SIN,
EXHSYN,
EXVSYN,
CBCK,
DA0 to DA7,
TSC, TEST
VCC = 5.5 V
VIL = 0.0 V
–200
—
–50
µA
ICC
VCC, AVCC1,
AVCC2
VCC = AVCC1 = AVCC2 = 5.5 V
4fsc = 17.734475 MHz
fDC = 16.0 MHz
No load
—
—
50
mA
IA
AVCC1, AVCC2
VCC = AVCC1 = AVCC2 = 5.5 V
4fsc = fDC = 0 MHz
AVIN = 1.65 V
No load
—
—
30
mA
ON
resistance
RON
VIN-VOUT,
YIN-YOUT,
CIN-COUT,
VIN-VKOUT,
VKIN-VOUT
VCC = AVCC1 = AVCC2 = 4.5 V
IOL = 100 µA
—
100
320
Ω
Off
leakage
current
IOFF
VIN, YIN, CIN,
VKIN
VCC = AVCC1 = AVCC2 = 5.5 V
AVIN = 5.5 V
—
0.1
10
µA
Output
resistance
ROUT
VOUT, YOUT,
COUT, VKOUT
VCC = AVCC1 = AVCC2 = 4.5 V
IOL = 100 µA
100
—
1800
Ω
“H” level
output
voltage
VOH
“L” level
output
voltage
VOL
Input
current
Supply
current
Analog
supply
current
VOC, VOB, B,
R, G, HSYNC,
VSYNC,
VBLNK, FSCO,
READ,
ADR0 to ADR20
Remarks
(Continued)
21
MB90092
(Ta = –40°C to +85°C, VSS = AVSS = 0 V)
Parameter
Symbol
Pin
Conditions
Value
Min.
Typ.
Max.
Unit
Yellow
High level
VYELH
2.89
3.00
3.11
V
Yellow
Low level
VYELL
2.03
2.14
2.25
V
Cyan
High level
VCYAH
2.89
3.00
3.11
V
Cyan
Low level
VCYAL
1.63
1.74
1.85
V
Green
High level
VGREH
2.66
2.77
2.88
V
Green
Low level
VGREL
1.63
1.74
1.85
V
Magenta
High level
VMAGH
2.49
2.60
2.71
V
Magenta
Low level
VMAGL
1.46
1.57
1.68
V
Red
High level
VREDH
2.49
2.60
2.71
V
Red
Low level
VREDL
1.23
1.34
1.45
V
Blue
High level
VBLUH
2.15
2.26
2.37
V
Blue
Low level
VBLUL
1.23
1.34
1.45
V
Color burst
High level
VBSTH
1.80
1.91
2.02
V
Color burst
Low level
VBSTL
1.12
1.23
1.34
V
VOUT
VCC = AVCC1 = AVCC2 = 5.0 V
Remarks
See Figure
“VOUT output”
(Continued)
22
MB90092
(Ta = –40°C to +85°C, VSS = AVSS = 0 V)
Parameter
Symbol
White level 3
φ = – 270°
Pin
Conditions
Values
Unit
Min.
Typ.
Max.
VWHT3
YWHT3
2.83
2.94
3.05
V
White level 2
φ = – 180°
VWHT2
YWHT2
2.72
2.83
2.94
V
White level 1
φ = – 90°
VWHT1
YWHT1
2.60
2.71
2.82
V
White level 0
φ = 0°
VWHT0
YWHT0
2.49
2.60
2.71
V
Gray
level 6
VGRY6
YGRY6
2.43
2.54
2.65
V
Gray
level 5
VGRY5
YGRY5
2.26
2.37
2.48
V
Gray
level 4
VGRY4
YGRY4
2.15
2.26
2.37
V
Gray
level 3
VGRY3
YGRY3
1.98
2.09
2.20
V
Gray
level 2
VGRY2
YGRY2
1.86
1.97
2.08
V
Gray
level 1
VGRY1
YGRY1
1.69
1.80
1.91
V
Black
level 3
φ = – 270°
VBLK3
YBLK3
1.92
2.03
2.14
V
Black
level 2
φ = – 180°
VBLK2
YBLK2
1.80
1.91
2.02
V
Black
level 1
φ = – 90°
VBLK1
YBLK1
1.69
1.80
1.91
V
Black
level 0
φ = 0°
VBLK0
YBLK0
1.57
1.68
1.79
V
Pedestal
level
VPDS
YPDS
1.46
1.57
1.68
V
SYNC level
VTIP
YTIP
0.84
1.00
1.16
V
VOUT,
YOUT
VCC = AVCC1 = AVCC2 = 5.0 V
Remarks
See
Figures
“VOUT
Output” and
“YOUT
Output”.
(Continued)
23
MB90092
(Continued)
24
(Ta = –40°C to +85°C, VSS = AVSS = 0 V)
Value
Unit
Remarks
Min.
Typ.
Max.
Parameter
Symbol
Yellow
High level
CYELH
1.92
2.03
2.14
V
Yellow
Low level
CYELL
1.00
1.11
1.22
V
Cyan
High level
CCYAH
2.09
2.20
2.31
V
Cyan
Low level
CCYAL
0.89
1.00
1.11
V
Green
High level
CGREH
1.98
2.09
2.20
V
Green
Low level
CGREL
0.95
1.06
1.17
V
Magenta
High level
CMAGH
1.98
2.09
2.20
V
Magenta
Low level
CMAGL
Red
High level
Pin
COUT
Conditions
VCC = AVCC1 = AVCC2 = 5.0 V
0.95
1.06
1.17
V
CREDH
2.09
2.20
2.31
V
Red
Low level
CREDL
0.89
1.00
1.11
V
Blue
High level
CBLUH
1.92
2.03
2.14
V
Blue
Low level
CBLUL
1.00
1.11
1.22
V
Color burst
High level
CBSTH
1.80
1.91
2.02
V
Color burst
Low level
CBSTL
1.12
1.23
1.34
V
Pedestal
level
CPDSC
1.46
1.57
1.68
V
See
Figure
“COUT
Output”
MB90092
• VOUT Output
VYELH
VCYAH
VGREH
VWHT0 − 3
VMAGH
VGRY6
VREDH
VGRY5
VBLUH
VGRY4
VGRY3
VYELL
VGRY2
VGRY1
VBLK0 − 3
VPDS
VCYAL
VBSTH
VPDS
VGREL
VMAGL
VBSTL
VREDL
VBLUL
VTIP
• YOUT Output
YWHT0 − 3
YGRY6
YGRY5
YGRY4
YGRY3
YGRY2
YGRY1
YBLK0 − 3
YPDS
YPDS
YTIP
• COUT Output
CCYAH
CGREH
CMAGH
CREDH
CBLUH
CYELH
CBSTH
CPDS
CBSTL
CBLUL
CYELL
CCYAL
CGREL
CMAGL
CREDL
25
MB90092
2. AC Characteristics
(Ta = –40°C to +85°C, VCC = 5.0 V±10%, VSS = 0 V)
Parameter
Shift clock cycle time
Shift clock pulse width
Shift clock signal rise/fall time
Symbol
Pin
Value
Min. Max.
Unit
tCYC SCLK
1000
—
ns
tWCH
450
—
ns
450
—
ns
—
200
ns
—
200
ns
tWCL
tCR
tCF
SCLK
SCLK
Shift clock start time
tSS
SCLK
200
—
ns
Data setup time
tSU
SIN
200
—
ns
Data hold time
tH
SIN
100
—
ns
Chip select end time
tEC
CS
500
—
ns
—
200
ns
—
200
ns
Chip select signal rise/fall time
tCRC
tCFC
CS
Remarks
See Figure “Serial Input
Timings”.
Horizontal sync signal rise time
tHR
EXHSYN
—
200
ns
Horizontal sync signal fall time
tHF
EXHSYN
—
200
ns
Vertical sync signal rise time
tVR
EXVSYN
—
200
Vertical sync signal fall time
tVF
EXVSYN
—
200
Horizontal sync signal pulse width*1
tWH
EXHSYN
4.0
8.0
ns See Figure
“Vertical and Horizontal Sync
ns Signal Input Timings”.
µs
Vertical sync signal pulse width *1
tWV
EXVSYN
1
5
Horizontal sync detection pulse width *2 tWCSH EXHSYN
4.0
8.0
tWCSV EXHSYN
13
28
µs See Figure “Composite Sync
µs Signal input Timings”.
Vertical sync detection pulse width*2
H
Reset input pulse width
tWR
TESTI
(TEST = Low)*3
10
—
µs
ROM read cycle *4
trcyc
—
250
500
ns
Address valid delay
tab
ADR0 to ADR20
—
60
ns
READ active delay
tra
READ
—
38
ns
Read data setup time
tds
DA0 to DA7
30
—
ns
Read data hold time
tdh
DA0 to DA7
30
—
ns
Address invalid delay
tai
ADR0 to ADR20
0
—
ns
READ inactive delay
tri
READ
0
—
ns
Tristate address delay
ttad
ADR0 to ADR20
—
100
Tristate READ delay
ttrd
READ
—
100
See Figure “Reset Signal Input Timing”.
See Figure “Address Data
Hold Timings”.
ns See Figure “Address and
READ Signal Delays at TSC
ns Signal Input”
*1: The values assume H/V-separated sync signal input.
*2: The values assume composite sync signal input.
*3: When the TEST pin is a Low-level input, the TESTI pin serves as a reset pin input. (The TESTI and TEST pins
can be Low level at the same time.)
*4: Depends on the dot clock oscillation frequency. (trcyc = 4/fDC)
26
MB90092
• Serial Input Timings
CS
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tCRC
tSS
tCYC
tEC
tCFC
0.8 VCC
SCLK
0.2 VCC
tWCH
tCR
tWCL
tCF
tH
tSU
0.8 VCC
SIN
0.2 VCC
• Vertical and Horizontal Sync Signal Input Timings
0.8 VCC
EXHSYN
0.8 VCC
0.2 VCC
tHF
tWH
0.8 VCC
EXVSYN
tHR
0.8 VCC
0.2 VCC
tVF
0.2 VCC
tWV
0.2 VCC
tVR
27
MB90092
• Composite Sync Signal Input Timings
0.8 V CC
EXHSYN
0.8 V CC
0.2 V CC
0.2 V CC
tWCSH
tHF
tHR
0.8 V CC
EXHSYN
0.8 V CC
0.2 V CC
0.2 V CC
tWCSV
H
H
EXHSYN
tWCSV
Vertical sync signal interval
(3H)
• Reset Signal Input Timing
TESTI
0.2 VCC
tWR
28
0.2 VCC
MB90092
• Address Data Hold Timings
trcyc
4
1
2
3
4
1
2
3
4
1
0.8 VCC
0.2 VCC
EXD
ADR0
to
ADR20
Main screen data address *
0.8 VCC
0.2 VCC
Sub-screen data address *
tab
tai
0.8 VCC
0.2 VCC
READ
tra
DA0
to
DA7
tri
Sub-screen data *
Main screen data *
tds
0.8 VCC
0.2 VCC
tdh
*: The main screen and sub-screen have the same address data timings.
• Address and READ Signal Delays at TSC Signal Input
0.8 VCC
ADR0 to ADR20
0.2 VCC
0.8 VCC
READ
TSC
0.2 VCC
0.2 VCC
ttrd
ttad
29
MB90092
3. Clock Timing Specifications
Parameter
Display dot clock*
Color burst clock (NTSC)*
Color burst clock (PAL)*
Symbol
Pin
fDC
EXD, XD
4 fSC
EXS, XS
Value
Unit
Min.
Typ.
Max.
8
—
16
MHz
—
14.318185
—
MHz
—
17.734475
—
MHz
Remarks
* : Input the signal with a duty cycle of 50%.
4. Power-on Reset Specifications
(Ta = –40°C to +85°C)
Parameter
Power-supply rise time
Symbol
Pin
tr
Value
Min.
0.05
Max.
50
Unit
ms
Conditions which activate
the power-on reset circuit
(See Figure “Power ON/
OFF Timing”).
Conditions in which the circuit repeatedly operate
normally (See Figure
“Power ON/OFF Timing”).
VCC
Power-supply off time
toff
1
—
ms
Time after power-supply rise
tWIT
450
—
ns
450
—
450
—
Reset cancel pulse width
30
tWRH
tWRL
CS
Remarks
ns
Power-on reset cancel timing (See Figure “Power-on
Reset Cancel Timing”).
MB90092
• Power ON/OFF Timing
4.5 V
0.2 V
0.2 V
0.2 V
VCC
tr
toff
Note: The power supply must be activated smoothly.
• Power-on Reset Cancel Timing
4.5 V
VCC
Internal reset
CS
tWIT
0.8 V CC
CS
0.2 V CC
tWRL
tWRH
tCRC*
tCFC*
*: See Section 2, “AC Characteristics”.
31
MB90092
5. Recommended Input Timings
(1) Composite sync signal input timing
Parameter
NTSC
PAL
Unit
525
625
Lines
Field frequency
60 (59.94)
50
Hz
*1
Line frequency
15750 (15734.264)
15625
Hz
*1
19 to 21
25
H
*2
First equalizing pulse interval
3
2.5
H
*2
Vertical sync pulse interval
3
2.5
H
*2
Second equalizing pulse interval
3
2.5
H
*2
Equalizing pulse width
2.29 to 2.54
2.34 to 2.36
µs
Equalizing pulse cycle
0.5
0.5
H
Cut-in pulse width
3.81 to 5.34
4.5 to 4.9
µs
Cut-in pulse cycle
0.5
0.5
H
63.492 (63.5555)
64
µs
4.19 to 5.71 (4.7±0.1)
4.5 to 4.9
µs
*1
11.7 to 12.3
µs
*1
NTSC
PAL
Unit
60 (59.94)
50
Hz
*1
1 to 5
1 to 4
H
*2
63.492 (63.5555)
64
µs
*1
4.19 to 5.71 (4.7±0.1)
4.5 to 4.9
µs
*1
Number of frame scan lines
Vertical retrace blanking interval
Horizontal sync signal cycle
Horizontal sync signal pulse width
Horizontal retrace blanking interval 10.2 to 11.4 (10.5 to 11.4)
Remarks
*2
*2
*1: Parenthesized values are specifications for color information display.
*2: 1 H is assumed to be one horizontal sync signal period.
(2) H/V-separated sync signal input timing
Parameter
Vertical sync signal frequency
Vertical sync signal pulse width
Horizontal sync signal cycle
Horizontal sync signal pulse width
*1: Parenthesized values are specifications for color information display.
*2: 1 H is assumed to be one horizontal sync signal period.
32
Remarks
MB90092
6. Output Timings
(1) Horizontal timing
Symbol
NTSC
PAL
Remarks
HPS
0
0
EQP1E
34
42
HPE
68
84
BSTS
76
100
BSTE
112
140
HBLKE
143
186
SEP1S
388
484
EQP2S
455
568
EQP2E
489
610
SEP2S
842
1050
HBLKS
888
1106
IHCLR
910
1135
(1137)*
See Figure “NTSC/PAL Horizontal Timings”.
*: Parenthesized values assume the last raster in each V cycle (field).
Note: The values in the above list are 4fSC count values.
(2) Vertical timing
Symbol
NTSC
PAL
Interlaced
Noninterlaced
Interlaced
Noninterlaced
VPS
0
0
0
0
VPE
6
6
5
5
EQPE
12
12
10
10
VBLKE
36
36
45
45
VBLKS
519
519
620
620
VPS
525
526
625
624
Remarks
See Figures
“NTSC Vertical
Timings” and
“PAL Vertical
Timings”.
Note: The values in the above list are 1/2H count values.
33
MB90092
• NTSC/PAL Horizontal Timings
Video signal
Horizontal sync signal
Horizontal retrace
blanking interval
Burst flag
Equalizing pulse
Cut-in pulse
EQP2E
EQP2S
SEP1S
HBLKE
BSTE
BSTS
HPE
EQP1E
HPS
HBLKS
34
IHCLR
HBLKS
SEP2S
Equalizing pulse interval
Vertical retrace blanking interval
Vertical sync interval
Horizontal scanning line No.
Composite video signal
Odd-numbered field
Equalizing pulse interval
Vertical retrace blanking interval
Vertical sync interval
Horizontal scanning line No.
Composite video signal
Even-numbered field
VBLKS
259 260 261
VBLKS
521 522 523
262
524
1
VPS
263 264
VPS
525
265
2
VPE
4
5
267 268
VPE
266
3
7
EQPE
269 270
EQPE
6
~
~
19
280
20
VBLKE
281 282
VBLKE
18
~
~
521
258
523 524
VBLKS
260 261
VBLKS
522
259
1
VPS
263
VPS
525
262
MB90092
• NTSC Vertical Timings
35
36
624
VBLKS
311
311
VBLKS
312
312
624
BSTE, VBLKS
309 310
BSTE
621 622 623
BSTE
309 310
BSTE VBLKS
621 622 623
Note1
VPS
313
314
1
VPS
625
VPS
313
314
1
VPS
625
VPE
3
VPE
3
VPE
315 316
2
VPE
315 316
2
317
4
6
7
318 319
6
EQPE
320
7
BSTS
318 319
EQPE, BSTS
5
320
EQPE BSTS
5
EQPE BSTS
317
4
Note 2
~
~
~
~
VBLKE
23
VBLKE
23
VBLKE
335 336
22
VBLKE
335 336
22
Notes 1: indicates the HSYNC positions in the equalizing pulse intervals.
2: The arrows marks indicate the phase of color subcarrier. (↑: +135°, ↓: –135°)
Color burst phase
Composite video signal
Horizontal scanning line No.
Vertical sync interval
Vertical retrace blanking interval
Burst blanking interval
Equalizing pulse interval
Forth field
Color burst phase
Composite video signal
Horizontal scanning line No.
Vertical sync interval
Vertical retrace blanking interval
Burst blanking interval
Equalizing pulse interval
Third field
Color burst phase
Composite video signal
Horizontal scanning line No.
Vertical sync interval
Vertical retrace blanking interval
Burst blanking interval
Equalizing pulse interval
Second field
Color burst phase
Composite video signal
Horizontal scanning line No.
Vertical sync interval
Vertical retrace blanking interval
Burst blanking interval
Equalizing pulse interval
First field
337
24
337
24
~
~
~
~
623 624
1
VPS
313
1
VPS
313
VPS
625
312
VPS
625
312
BSTS, VBLKS
310 311
VBLKS
623 624
BSTE VBLKS
621 622
309
BSTE
308
310 311
BSTE VBLKS
309
621 622
308
MB90092
• PAL Vertical Timings
MB90092
■ SAMPLE CIRCUIT
This is a standard example of the circuit to synthesize the character to input video signal or input internal
generation video signal from the outside. Note that composition is different according to the system and parts
used.
MB90092
Composite
IN
Composite OUT
Video amplifer &
clamp circuit
VIN
VOUT
Video amplifer &
clamp circuit
YIN
YOUT
COUT
Buffer circuit
Y/C IN
Y/C OUT
CIN
Sync separation
circuit
Buffer circuit
EXHSYN
D0
D0
∼
∼
∼
D7
D7
ADR0
A0
CS
Control
microcontroller
SCLK
∼
+5 V
∼
∼
SIN
ADR20
A20
READ
OE
CE
(16M − ROM)
AVCC1
AVCC2
+
+5 V
AVSS
VCC
+
EXS
VSS
XS
XD
EXD
3.3 µH
20 pF
(Approx. 14 MHz)
20 pF
NTSC : 14.31818 MHz
PAL : 17.734475 MHz
37
MB90092
■ ORDERING INFORMATION
38
Part number
Package
MB90092PF
80-pin, plastic QFP
(QFP-80P-M06)
Remarks
MB90092
■ PACKAGE DIMENSION
80-pin plastic QFP
(FPT-80P-M06)
Note : Pins width and pins thickness include plating thickness.
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
64
41
65
40
0.10(.004)
17.90±0.40
(.705±.016)
14.00±0.20
(.551±.008)
INDEX
Details of "A" part
80
25
0.25(.010)
+0.30
3.05 –0.20
+.012
.120 –.008
(Mounting height)
1
24
0.80(.031)
"A"
C
2001 FUJITSU LIMITED F80010S-c-4-4
0.37±0.05
(.015±.002)
0.20(.008)
0~8°
M
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
+0.10
0.30 –0.25
+.004
.012 –.010
(Stand off)
Dimensions in mm (inches).
39
MB90092
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0108
 FUJITSU LIMITED Printed in Japan