Ordering number : EN5731A CMOS IC LC74788, 74788M, 74788JM On-Screen Display Controller Overview Package Dimensions The LC74788, LC74788M, and LC74788JM are onscreen display controller CMOS ICs that display characters and patterns on the TV screen under microprocessor control. These ICs support 12 × 18 dot characters and can display 12 lines by 24 characters of text. unit: mm 3067-DIP24S [LC74788] Features • Display format: 24 characters by 12 rows (Up to 288 characters) • Character format: 12 (horizontal) × 18 (vertical) dots • Character sizes: Three sizes each in the horizontal and vertical directions • Characters in font: 128 (128 characters, one spacing character, and one transparent spacing character) • Initial display positions: 64 horizontal positions and 64 vertical positions • Blinking: Specifiable in character units • Blinking types: Two periods supported: About 1.0 second and about 0.5 second • Blanking: Over the whole font (12 × 18 dots) • Background color: 8 colors (internal synchronization mode): 2fSC and 4fSC • Line background color — Can be set for 3 lines — Line background color: 8 colors (internal synchronization mode): 2fSC and 4fSC • External control input: 8-bit serial input format • On-chip sync separator circuit • Video outputs - NTSC, PAL, PAL-N, PAL-M, NTSC 4.43, and PAL60 format composite video outputs • Package — 24-pin plastic DIP-24S (300 mil) — 24-pin plastic MFP-24 (375 mil) — 24-pin plastic MFP-24S (300 mil) SANYO: DIP24S unit: mm 3045B-MFP24 [LC74788M] SANYO: MFP24 unit: mm 3112-MFP24S [LC74788JM] SANYO: MFP24S SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 30698HA (OT) No. 5731-1/23 LC74788, 74788M, 74788JM Pin Assignment LC74788 LC74788M LC74788JM A08688 Pin Functions Pin no. Pin Function 1 VSS1 Ground 2 XtalIN 3 XtalOUT (MUTE) Notes Ground connection (digital system ground) Crystal oscillator (MUTE input) These pins are used either to connect the crystal and capacitors used to form an external crystal oscillator circuit to generate the internal synchronizing signals, or to input an external clock signal (2fsc or 4fsc). As a mask option, the XtalOUT pin can be set to function as the MUTE input pin. When this pin is set low, the video output is held at the pedestal level. (A pullup resistor is built in and the input has hysteresis characteristics.) 4 CTRL1 (CHABLK) Crystal oscillator input switching (CHABLK output) Switches the mode between external clock input and crystal oscillator operation. A low level selects crystal oscillator operation and a high level selects external clock input. As a mask option, the CTRL1 input pin can be set to function as the CHABLK (character · frame) output. This is a 3-value output. 5 HFTONOUT Background line output 6 OSCIN 7 OSCOUT Outputs the range signal specified by LNA*, LNB*, and LNC*. Outputs the crystal oscillator clock when RST is low. (This signal is not output after a reset command is executed.) Connections for the inductor and capacitor that form the character output dot clock generation LC oscillator oscillator. Outputs the state of the external synchronizing signal presence/absence judgment. Outputs a high level when synchronizing signals are present. Outputs the dot clock (LC oscillator) when RST is low. (This signal is not output on command resets.) 8 SYNCJDG External synchronizing signal judgment output 9 CS Enable input 10 SCLK Clock input Serial data input circuit clock input. A pull-up resistor is built in. (This input has hysteresis characteristics.) 11 SIN Data input Serial data input. A pull-up resistor is built in. (This input has hysteresis characteristics.) 12 VDD2 Power supply Serial data input circuit enable pin. Serial data input is enabled when a low level is input. A pull-up resistor is built in. (This input has hysteresis characteristics.) Composite video signal level adjustment power supply (analog system power supply) Continued on next page. No. 5731-2/23 LC74788, 74788M, 74788JM Continued from preceding page. Pin no. Pin Function 13 CVOUT Video signal output 14 VSS2 Ground 15 CVIN Video signal input 16 CVCR Video signal input 17 VDD1 Power supply 18 SYNIN Sync separator circuit input Video signal input to the internal sync separator circuit (Used as either the horizontal synchronizing signal or the composite synchronizing signal input when the internal sync separator circuit is not used.) 19 SEPC Sync separator circuit bias voltage Internal sync separator circuit bias voltage monitor 20 SEPOUT Composite synchronizing signal output Internal sync separator circuit composite synchronizing signal output. Can be switched to function as a signal (high, low, or ST. pulse) output by the SEL0 and MOD0 setting. 21 SEPIN Vertical synchronizing signal input 22 CDLR Background color phase adjustment 23 RST Reset input 24 VDD1 Power supply (+5 V) Notes Composite video signal output Ground connection (analog system ground) Composite video signal input SECAM chrominance signal input Power supply (+5 V: digital system power supply) Inputs the vertical synchronizing signal created by integrating the SEPOUT pin output signal. An integration circuit must be connected to the SEPOUT pin. This pin must be tied to VDD1 if unused. This pin can be switched to function as the frame signal input mode by setting SEL1 high. This is valid when CTL3 is set high. This input has hysteresis characteristics. Background color phase adjustment. Connect a resistor between this pin and ground. System reset input A pull-up resistor is built in and the input has hysteresis characteristics. Power supply (+5 V: digital system power supply) Note: Both VDD1 pins must be connected to the power supply. No. 5731-3/23 LC74788, 74788M, 74788JM Specifications Absolute Maximum Ratings Ratings Unit Maximum supply voltage Parameter VDD max VDD1 and VDD2 VSS–0.3 to VSS+6.5 V Maximum input voltage VIN max All input pins VSS–0.3 to VDD+0.3 V HFTONOUT, SYNCJDG, and SEPOUT VSS–0.3 to VDD+0.3 Maximum output voltage Allowable power dissipation Symbol VOUT max Pd max Conditions Ta = 25°C 350 V mW Operating temperature Topr –30 to +70 °C Storage temperature Tstg –40 to +125 °C Allowable Operating Ranges Parameter Supply voltage Input high-level voltage Input low-level voltage Pull-up resistance Composite video signal input voltage Input voltage Oscillator frequencies Symbol Ratings Conditions min typ max Unit VDD1 VDD1 4.5 5.0 5.5 V VDD2 VDD2 4.5 5.0 1.27VDD1 V VIH1 RST, CS, SIN, SCLK, SEPIN, and MUTE 0.8VDD1 VDD1+0.3 V VIH2 CTRL1 0.7VDD1 VDD1+0.3 V VIL1 RST, CS, SIN, SCLK, SEPIN, and MUTE VSS–0.3 0.2VDD1 V VIL2 CTRL1 VSS–0.3 0.3VDD1 V RPU RST, CS, SIN, SCLK, and MUTE Applies to pins set up by options. VIN1 CVIN: VDD1 = 5 V 2.0 VIN2 SYNIN: VDD1 = 5 V 2.0 VIN3 CVCR: VDD1 = 5 V 2.0 VIN4 XtalIN (when used for external clock input) fIN = 2fsc or 4fsc ; VDD1 = 5 V FOSC1 FOSC2 25 50 0.10 90 kΩ Vp-p 2.5 Vp-p Vp-p 5.0 Vp-p XtalIN and XtalOUT oscillator pins (2fsc: NTSC) 7.159 MHz XtalIN and XtalOUT oscillator pins (4fsc: NTSC) 14.318 MHz XtalIN and XtalOUT oscillator pins (2fsc: PAL) 8.867 MHz XtalIN and XtalOUT oscillator pins (4fsc: PAL) 17.734 MHz XtalIN and XtalOUT oscillator pins (2fsc: PAL-M) 7.151 MHz XtalIN and XtalOUT oscillator pins (4fsc: PAL-M) 14.302 MHz XtalIN and XtalOUT oscillator pins (2fsc: PAL-N) 7.164 MHz XtalIN and XtalOUT oscillator pins (4fsc: PAL-N) 14.328 OSCIN and OSCOUT oscillator pins (LC oscillator) 5 MHz 10 MHz Note: Applications must be especially cautious about noise when using the XtalIN input pin in clock input mode. No. 5731-4/23 LC74788, 74788M, 74788JM Electrical Characteristics at Ta = –30 to +70°C. VDD1 = 5 V unless otherwise specified. Parameter Symbol Pin Ratings Conditions min typ Unit max Input off leakage current Ileak1 CVIN and CVCR 1 µA Output off leakage current Ileak2 CVOUT 1 µA Output high-level voltage VOH1 HFTONOUT, SYNCJDG, and SEPOUT VDD1 = 4.5 V, IOH = –1.0 mA Output low-level voltage VOL1 HFTONOUT, SYNCJDG, and SEPOUT VDD1 = 4.5 V, IOL = –1.0 mA VO CHABLK VDD1 = 5.0 V IIH RST, CS, SIN, SCLK, CTRL1, SEPIN, and MUTE VIN = VDD1 IIL CTRL1 and OSCIN VIN = VSS1 IDD1 VDD1 All outputs: open Xtal:7.159 MHz LC:8 MHz IDD2 VDD2 VDD2 = 5 V Three-value output voltage Input current Operating mode current drain SYNC level Pedestal level Color burst low level Color burst high level Background color low level (other than blue) Background color high level (other than blue) Blue background 1 low level Blue background 2 low level Blue background 1 and 2 high level Frame level 0 Frame level 1 Character level VSN VPD VCBL VCBH VRSL1 VRSL2 VRSH1, 2 VBK0 VBK1 VCHA V 1.0 H 3.3 5.0 V 1.8 2.3 V L 0 0.8 V 1 µA –1 µA 15 mA 20 mA (1) 0.70 0.82 0.94 (2) 0.89 1.01 1.13 (3) 1.18 1.30 1.42 (1) 1.32 1.44 1.56 (2) 1.52 1.64 1.76 (3) 1.81 1.93 2.05 (1) 0.98 1.10 1.22 (2) 1.17 1.29 1.41 (3) 1.46 1.58 1.70 (1) 1.63 1.75 1.87 (2) 1.83 1.95 2.07 (3) 2.11 2.23 2.35 (1) 1.17 1.29 1.41 1.36 1.48 1.60 (3) 1.65 1.77 1.89 (1) 2.33 2.45 2.57 (2) 2.52 2.64 2.76 (1): When the sync level = 0.8 V VDD1 = 5.0 V (3) 2.81 2.93 3.05 (2): When the sync level = 1.0 V VDD2 = 5.0 V (1) 1.08 1.20 1.32 (3): When the sync level = 1.3 V (2) 1.27 1.39 1.51 (3) 1.56 1.68 1.80 (1) 1.49 1.61 1.83 (2) 1.68 1.80 1.92 (3) 1.97 2.09 2.21 (1) 1.97 2.09 2.21 (2) 2.17 2.29 2.41 (3) 2.46 2.58 2.70 (1) 1.40 1.52 1.64 (2) 1.60 1.72 1.84 (3) 1.89 2.01 2.13 CVOUT V M (2) VRSL0 VRSH0 3.5 (1) 1.97 2.09 2.21 (2) 2.17 2.29 2.41 (3) 2.46 2.58 2.70 (1) 2.55 2.67 2.79 (2) 2.75 2.87 2.99 (3) 3.04 3.16 3.28 V V V V V V V V V V V V Note: Blue background 1 or 2 are option settings. No. 5731-5/23 LC74788, 74788M, 74788JM Timing Characteristics at Ta = –30 to +70°C, VDD1 = 5 ±0.5 V Parameter Minimum input pulse width Data setup time Data hold time One word write time Symbol tW(SCLK) Ratings Conditions min SCLK tW(CS) CS (The period when CS is high) typ max Unit 200 ns 1 µs ns tSU(CS) CS 200 tSU(SIN) SIN 200 ns th(CS) CS 2 µs th(SIN) SIN 200 ns tword The time to write 8 bits of data 4.2 µs 1 µs twt The RAM data write time Serial Data Input Timing First byte Second byte A08689 No. 5731-6/23 Sync separator Character output dot clock generator Serial to parallel converter Composite sync signal separation control Synchronization determination 8-bit latch + command decode Vertical size counter Horizontal size counter Timing generator Vertical character size register Horizontal character size register Sync signal generator Line control counter Vertical display position detector Horizontal display position detector Character control counter Vertical dot counter Vertical display position register Horizontal dot counter Horizontal display position register Display control register Character output control Background control Video output control Blinking and reverse control circuit Blinking and reverse control register Font ROM Decoder A08690 Display RAM Shift register Decoder RAM write address counter LC74788, 74788M, 74788JM System Block Diagram No. 5731-7/23 LC74788, 74788M, 74788JM Display Control Commands Display control commands have an 8-bit format and are transferred using the serial input function. Commands consist of a command identification code in the first byte and command data in the following bytes. The following commands are supported. 1 2 3 4 5 6 7 8 9 10 11 COMMAND0: COMMAND1: COMMAND2: COMMAND3: COMMAND4: COMMAND5: COMMAND6: COMMAND7: COMMAND8: COMMAND9: COMMAND10: Display memory (VRAM) write address setup command Display character data write command Vertical display start position and vertical character size setup command Horizontal display start position and horizontal character size setup command Display control setup command Display control setup command Synchronizing signal detection setup command Display control setup command Display control setup command Display control setup command Display control setup command Display Control Command Table First byte Command Command identification code Second byte Data Data 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 V3 V2 V1 V0 0 0 0 H4 H3 H2 H1 H0 1 0 0 1 0 0 0 at c7 c6 c5 c4 c3 c2 c1 c0 COMMAND2 Vertical character size and vertical display start position 1 0 1 0 VS 21 VS 20 VS 11 VS 10 0 FS VP 5 VP 4 VP 3 VP 2 VP 1 VP 0 COMMAND3 Horizontal character size and horizontal display start position 1 0 1 1 HS 21 HS 20 HS 11 HS 10 0 LC HP 5 HP 4 HP 3 HP 2 HP 1 HP 0 COMMAND4 1 1 0 0 0 BLK BLK BLK BK BK RV DSP 2 1 0 1 0 NP HLF BCL CB PH PH 2 INT 2 1 0 RN SN SN SN COMMAND0 Write address setup COMMAND1 Character write Display control COMMAND5 1 1 0 1 Display control COMMAND6 RAM OSC SYS ERS STP RST NP NP NON INT 1 0 SEL MOD 1 1 1 0 0 0 LIN 1 1 1 1 0 0 SEL 1 3 1 1 1 1 0 1 VSY HSY SEL SEL MOD Synchronizing signal detection COMMAND7 TST MOD Display control COMMAND8 Display control COMMAND9 Display control RN 2 1 0 3 2 1 0 CTL 0 CIN CIN VNP VSP MSK MSK EGL SEL CTL SEL SEL ERS SEL 0 LNA LNA LNA LNA LPA LPA 3 2 1 0 2 1 0 0 LNB LNB LNB LNB LPB LPB LPB 3 2 1 0 2 1 0 0 LNC LNC LNC LNC LPC LPC LPC 3 2 1 0 2 1 0 1 1 1 0 LNB SEL 2 1 1 1 1 1 1 LNC MOD SEL 3 SN PH 0 1 RN ON MUT 1 Display control COMMAND10 DIS 0 LPA Once written, a first byte command identification code is stored until the next first byte is written. However, when the display character data write command (COMMAND1) is written, the LC74788/M/JM locks into the display character data write mode, and another first byte cannot be written. When the CS pin is set high, the LC74788/M/JM is set to the COMMAND0 (display memory write address setup mode) state. No. 5731-8/23 LC74788, 74788M, 74788JM COMMAND0 (Display memory write address setup command) • First byte DA 0 to 7 Contents Register State Function 7 — 1 6 — 0 Command 0 identification code 5 — 0 Sets the display memory write address. 4 — 0 3 V3 2 V2 1 V1 0 V0 Notes 0 1 0 1 Display memory line address (0 to B hexadecimal) 0 1 0 1 • Second byte DA 0 to 7 Contents Register State 7 — 1 6 — 0 5 — 0 4 H4 3 H3 2 H2 1 H1 0 H0 Function Notes Second byte identification code 0 1 0 1 0 Display memory column address (0 to 17 hexadecimal) 1 0 1 0 1 Note: All registers are set to 0 when the LC74788/M/JM is reset by the RST pin. No. 5731-9/23 LC74788, 74788M, 74788JM COMMAND1 (Display character data write setup command) • First byte DA 0 to 7 Contents Register State Function 7 — 1 6 — 0 Command 1 identification code. 5 — 0 Sets up display character data write mode. 4 — 1 3 — 0 2 — 0 1 — 0 0 at 0 Character attribute off 1 Character attribute on Notes When this command is input, the LC74788/M/JM locks in the display character data write mode until the CS pin goes high • Second byte DA 0 to 7 Contents Register 7 c7 6 c6 5 c5 4 c4 3 c3 2 c2 1 c1 0 c0 State Function Notes 0 1 0 1 0 1 Character code (00 to 7F hexadecimal) 0 1 (FE (hex): spacing character) 0 (FF (hex): transparent spacing character) 1 0 1 0 1 0 1 Note: All registers are set to 0 when the LC74788/M/JM is reset by the RST pin. No. 5731-10/23 LC74788, 74788M, 74788JM COMMAND2: Vertical display start position and vertical character size setup command • First byte DA 0 to 7 Contents Register State Notes Function 7 — 1 6 — 0 Command 2 identification code 5 — 1 Sets the vertical display start position and the vertical character size 4 — 0 3 VS21 2 VS20 1 VS11 0 VS10 0 VS20 0 1 0 0 1H/dot 2H/dot 1 1 3H/dot 1H/dot 0 1 1 VS21 0 1 VS10 VS11 0 0 1H/dot 2H/dot 1 1 3H/dot 1H/dot Second line vertical character size First line vertical character size • Second byte DA 0 to 7 7 6 5 4 Contents Register — FS Function 0 Second byte identification bit 0 Crystal oscillator frequency: 2fsc 1 Crystal oscillator frequency: 4fsc VP5 0 If VS is the vertical display start position then: (MSB) 1 VS = α + H × (2Σ 2n VPn) 0 H: the horizontal synchronization pulse period 1 α = 20 H (in 525-line systems) 0 = 25 H (in 625-line systems) VP4 3 VP3 2 VP2 1 VP1 0 State Notes 5 n=0 The vertical display start position is set by the 6 bits VP0 to VP5. 1 0 The weight of bit 1 is 2H. 1 0 1 VP0 0 (LSB) 1 Character display area Note: All registers are set to 0 when the LC74788/M/JM is reset by the RST pin. No. 5731-11/23 LC74788, 74788M, 74788JM COMMAND3 (Horizontal display start position and horizontal size setup command) • First byte DA 0 to 7 Contents Register State Notes Function 7 — 1 6 — 0 Command 3 identification code 5 — 1 Sets the horizontal display start position and the horizontal character size. 4 — 3 HS21 2 HS20 1 HS11 0 HS10 1 0 HS20 0 1 0 0 1 Tc/dot 2 Tc/dot 1 1 3 Tc/dot 1 Tc/dot 0 1 1 HS21 0 1 HS10 HS11 0 0 1 Tc/dot 2 Tc/dot 1 1 3 Tc/dot 1 Tc/dot Second line horizontal character size First line horizontal character size • Second byte DA 0 to 7 7 6 5 Contents Register — State Function 0 Second byte identification bit 0 Use the LC oscillator for the dot clock 1 Use the crystal oscillator for the dot clock HP5 0 If HS is the horizontal start position then: (MSB) 1 HS =Tc × (2Σ 2n HPn) LC Notes Selects the dot clock used for character display in the horizontal direction. 5 n=0 4 HP4 3 HP3 2 HP2 1 HP1 0 0 Tc: Period of the oscillator connected to OSCIN/OSCOUT in operating 1 mode. 0 1 0 The horizontal display start position is set by the 6 bits HP0 to HP5. The weight of bit 1 is 2Tc. 1 0 1 HP0 0 (LSB) 1 Note: All registers are set to 0 when the LC74788/M/JM is reset by the RST pin. No. 5731-12/23 LC74788, 74788M, 74788JM COMMAND4 (Display control setup command) • First byte DA 0 to 7 Contents Register State Notes Function 7 — 1 6 — 1 Command 4 identification code. 5 — 0 Display character data write setup. 4 — 0 3 TSTMOD 2 RAMERS 1 OSCSTP 0 SYSRST 0 Normal operating mode 1 Test mode This bit must be set to 0. 0 Erasing RAM takes about 500 µs. (This operation must be executed in the DSPOFF state.) 1 Erase display RAM. (The RAM data is set to FF hexadecimal.) 0 Do not stop the crystal and LC oscillators. 1 Stop the crystal and LC oscillators. Valid in external synchronization mode when character display is off. Reset all registers and turn display off. The registers are reset when the CS pin is low, and the reset state is cleared when CS is set high. 0 1 • Second byte DA 0 to 7 7 Contents Register — 6 BLK2 5 BLK1 4 BLK0 3 BK1 2 BK0 1 RV 0 DSPON State 0 Second byte identification bit 0 Character display area 1 Video display area 0 1 Notes Function BLK0 0 1 0 Blanking off Character size 1 Frame size Complete fill in BLK1 0 1 0 Blinking period: About 0.5 s 1 Blinking period: About 1.0 s 0 Blinking off 1 Blinking on Specifies the size for complete fill in 0 Reverse video off 1 Reverse video on 0 Character display off 1 Character display on Changes the blanking size Switches the blinking period Blinking in reverse video mode switches the display between normal character display and reverse video display. Note: All registers are set to 0 when the LC74788/M/JM is reset by the RST pin. No. 5731-13/23 LC74788, 74788M, 74788JM COMMAND5 (Display control setup command) • First byte DA 0 to 7 Contents Register State 7 — 1 6 — 1 Command 5 identification code 5 — 0 Display control setup 4 — 1 3 NP1 0 1 0 2 NP0 1 1 NON 0 INT Notes Function NP2 NP1 NP0 0 0 0 Format NTSC 0 0 1 PAL-M 0 1 0 PAL 0 1 1 PAL-N 1 0 0 NTSC4.43 1 0 1 PAL60 0 Interlaced 1 Noninterlaced 0 External synchronization 1 Internal synchronization Switches between the NTSC, PAL, PAL-N, PAL-M, NTSC 4.43, and PAL60 formats. Switches between interlaced and noninterlaced video. Switches between external and internal synchronization • Second byte DA 0 to 7 7 Contents Register — 6 NP2 5 HLFINT 4 BCL 3 CB 2 PH2 State 0 0 Normal mode 1 Half internal synchronization mode 0 Background color on 1 No background color (Only the background level is set) 0 Color burst signal output. 1 Color burst signal output stopped. 0 PH1 1 0 PH0 Set with NP0 and NP1. 1 1 0 Second byte identification bit 0 0 1 Notes Function 1 Only valid in internal synchronization mode. Only valid when BCL is high. PH2 PH1 PH0 0 0 0 Background color (phase) Cyan 0 0 1 Yellow 0 1 0 Red 0 1 1 Blue 1 0 0 Cyan blue 1 0 1 Green 1 1 0 Orange 1 1 1 Magenta Background color specification Note: All registers are set to 0 when the LC74786/M/JM is reset by the RST pin. No. 5731-14/23 LC74788, 74788M, 74788JM COMMAND6 (Synchronizing signal detection setup command) • First byte DA 0 to 7 Contents Register State Notes Function 7 — 1 6 — 1 Command 6 identification code. 5 — 1 Sets up synchronizing signal control. 4 — 0 3 SEL0 0 SEL0 MOD SEPOUT output 0 0 Sync separator signal 0 1 Low-level output 1 0 High-level output 1 1 ST pulse signal 1 0 2 MOD0 Switches the SEPOUT (pin 19) output 1 1 DISLIN 0 MUT 0 12 lines 1 10 lines 0 Normal output 1 CVIN is cut and CVOUT is held at the pedestal level. Switches the number of lines displayed CVOUT switching • Second byte DA 0 to 7 7 6 5 Contents Register — RN2 RN1 4 RN0 3 SN3 2 SN2 1 0 SN1 SN0 State 0 Notes Function Second byte identification bit 0 1 RN2 RN1 RN0 Number of times HSYNC detected 0 0 0 0 times Signal absent → signal present transition detection 0 0 1 4 times 0 1 0 8 times 1 0 0 16 times Sets the sampling period in which SYNC can be detected continuously in the horizontal synchronizing signal period (1H). 0 1 0 External synchronizing signal detection control. 1 0 1 SN3 SN2 SN1 SN0 Number of times HSYNC detected 0 0 0 0 0 Not detected 1 0 0 0 1 32 times 0 0 0 1 0 64 times 1 0 1 0 0 128 times 0 1 0 0 0 256 times External synchronizing signal detection control. Signal present → signal absent transition detection Sets the sampling period in which SYNC cannot be detected continuously in the horizontal synchronizing signal period (1H). 1 Note: All registers are set to 0 when the LC74788/M/JM is reset by the RST pin. No. 5731-15/23 LC74788, 74788M, 74788JM COMMAND7 (Display control setup command) • First byte DA 0 to 7 Contents Register State Notes Function 7 — 1 6 — 0 Command 7 identification code. 5 — 0 Display control setup. 4 — 1 3 — 0 2 — 0 1 SEL1 0 CTL3 Extended command 0 identification code 0 Vertical synchronizing signal (external V separation) input Switches the SEPIN (pin 20) input. 1 Frame signal input Only valid when CTL3 is high. 0 Use internal V separation 1 Do not use internal V separation Switches V separation. • Second byte DA 0 to 7 7 Contents Register — 6 CINSEL 5 CINCTL 4 VNPSEL 3 VSPSEL 2 MSKERS 1 MSKSEL 0 EGL State Notes Function 0 Second byte identification bit 0 Blanking area (The logical OR of the character and frame signals) 1 Video signal display area 0 CVCR: off 1 CVCR: on CVCR on signal switching CVCR on/off setting 0 V falling edge detection Switches the V acquisition polarity in external mode 1 V rising edge detection when internal V separation is used. 0 VSEP: about 8.9 µs (for NTSC) 1 VSEP: about 17.8 µs (for NTSC) 0 Mask valid 1 Mask invalid 0 3H (for NTSC) 1 20H (for NTSC) 0 Frame level 0 only (VBK0) Switches the internal V separation period. Clears the HSYNC and VSYNC masks. Switches the VSYNC mask. Switches the frame level. Note: All registers are set to 0 when the LC74786/M/JM is reset by the RST pin. No. 5731-16/23 LC74788, 74788M, 74788JM COMMAND8 (Display control setup command) • First byte DA 0 to 7 Contents Register State 7 — 1 6 — 1 Command 8 identification code. 5 — 1 Display control setup. 4 — 1 3 — 0 2 — 1 1 VSYSEL 0 0 Notes Function Extended command 1 identification code Negative polarity SEPIN input polarity switching. Only valid when CTL3 is high. 1 Positive polarity 0 Negative polarity 1 Positive polarity SYNIN (only valid when the sync separator circuit is not used) and SEPOUT input and output polarity switching HSYSEL • Second byte DA 0 to 7 Contents Register 7 — 6 LNA3 State 0 0 1 0 5 LNA2 1 0 4 LNA1 1 0 3 LNA0 1 Notes Function Second byte identification bit LNA3 LNA2 LNA1 LNA0 Specified line 0 0 0 0 Do not change the line background 0 0 0 1 Line 1 0 0 1 0 Line 2 0 0 1 1 Line 3 0 1 0 0 Line 4 0 1 0 1 Line 5 0 1 1 0 Line 6 0 1 1 1 Line 7 1 0 0 0 Line 8 1 0 0 1 Line 9 1 0 1 0 Line 10 1 0 1 1 Line 11 1 1 — — Line 12 Specifies the line whose background is to be changed. (If the same line is specified to have different background colors with LNA*, LNB*, and LNC*, then the setting specified by the last command issued will be valid. The previously specified registers (LN* and LP*) will all be reset to 0.) 0 2 LPA2 1 0 1 LPA1 1 0 0 LPA0 LPA2 LPA1 0 0 LPA0 Line background color (phase) 0 Cyan 0 0 1 Yellow 0 1 0 Red 0 1 1 Blue 1 0 0 Cyan blue 1 0 1 Green 1 1 0 Orange 1 1 1 Magenta Specifies the background color 1 Note: All registers are set to 0 when the LC74788/M/JM is reset by the RST pin. No. 5731-17/23 LC74788, 74788M, 74788JM COMMAND9 (Display control setup command) • First byte DA 0 to 7 Contents Register State Notes Function 7 — 1 6 — 1 Command 9 identification code. 5 — 1 Display control setup. 4 — 1 3 — 1 2 — 0 1 LNBSEL 0 MOD2 Extended command 2 identification code 0 Normal line background color operation 1 RV characters have the background color specified by PH* or the RV character background color is white. 0 The LNBSEL: 1 setting specifications 1 RV characters have the background color specified by PH*, characters are white. Switches the RV mode background color for the line specified by LNB* for characters specified for RV display. Valid when LNBSEL is high • Second byte DA 0 to 7 Contents Register 7 — 6 LNB3 State 0 0 1 0 5 LNB2 1 0 4 LNB1 1 0 3 LNB0 1 Notes Function Second byte identification bit LNB3 LNB2 LNB1 LNB0 Specified line 0 0 0 0 Do not change the line background 0 0 0 1 Line 1 0 0 1 0 Line 2 0 0 1 1 Line 3 0 1 0 0 Line 4 0 1 0 1 Line 5 0 1 1 0 Line 6 0 1 1 1 Line 7 1 0 0 0 Line 8 1 0 0 1 Line 9 1 0 1 0 Line 10 1 0 1 1 Line 11 1 1 — — Line 12 Specifies the line whose background is to be changed. (If the same line is specified to have different background colors with LNA*, LNB*, and LNC*, then the setting specified by the last command issued will be valid. The previously specified registers (LN* and LP*) will all be reset to 0.) 0 2 LPB2 1 0 1 LPB1 1 0 0 LPB0 LPB2 LPB1 LPB0 0 0 0 Line background color (phase) Cyan 0 0 1 Yellow 0 1 0 Red 0 1 1 Blue 1 0 0 Cyan blue 1 0 1 Green 1 1 0 Orange 1 1 1 Magenta Specifies the background color 1 Note: All registers are set to 0 when the LC74788/M/JM is reset by the RST pin. No. 5731-18/23 LC74788, 74788M, 74788JM COMMAND10 (Display control setup command) • First byte DA 0 to 7 Contents Register State Notes Function 7 — 1 6 — 1 Command 10 identification code. 5 — 1 Display control setup. 4 — 1 3 — 1 2 — 1 1 LNCSEL 0 MOD3 Extended command 3 identification code 0 Normal line background color operation 1 RV characters have the background color specified by PH* or the RV character background color is white. 0 The LNCSEL: 1 setting specifications 1 RV characters have the background color specified by PH*, characters are white. Switches the RV mode background color for the line specified by LNC* for characters specified for RV display. Valid when LNCSEL is high • Second byte DA 0 to 7 Contents Register 7 — 6 LNC3 State 0 0 1 0 5 LNC2 1 0 4 LNC1 1 0 3 LNC0 1 Notes Function Second byte identification bit LNC3 LNC2 LNC1 LNC0 Specified line 0 0 0 0 Do not change the line background 0 0 0 1 Line 1 0 0 1 0 Line 2 0 0 1 1 Line 3 0 1 0 0 Line 4 0 1 0 1 Line 5 0 1 1 0 Line 6 0 1 1 1 Line 7 1 0 0 0 Line 8 1 0 0 1 Line 9 1 0 1 0 Line 10 1 0 1 1 Line 11 1 1 — — Line 12 Specifies the line whose background is to be changed. (If the same line is specified to have different background colors with LNA*, LNB*, and LNC*, then the setting specified by the last command issued will be valid. The previously specified registers (LN* and LP*) will all be reset to 0.) 0 2 LPC2 1 0 1 LPC1 1 0 0 LPC0 LPC2 LPC1 0 0 LPC0 Line background color (phase) 0 Cyan 0 0 1 Yellow 0 1 0 Red 0 1 1 Blue 1 0 0 Cyan blue 1 0 1 Green 1 1 0 Orange 1 1 1 Magenta Specifies the background color. 1 Note: All registers are set to 0 when the LC74788/M/JM is reset by the RST pin. No. 5731-19/23 LC74788, 74788M, 74788JM Display Screen Structure The display consists of 12 lines of 24 characters. Up to 288 characters can be displayed. The number of characters that can be displayed is reduced when enlarged characters are displayed. Display memory addresses are specified as row (0 to 11 decimal) and column (0 to 23 decimal) addresses. Display Screen Structure (display memory addresses) 24 Characters 12 Rows A08691 No. 5731-20/23 LC74788, 74788M, 74788JM Composite Video Signal Output Levels (internally generated levels) CVOUT output level waveform (VDD2 = 5.0 V) Output voltage (1) [V] Output voltage (2) [V] Output voltage (3) [V] VCHA : Character Output level 2.67 2.87 3.16 VRH0 : Background color (other than blue) high 2.45 2.64 2.93 VRSH1, 2 : Blue background color 1 and 2 high 2.09 2.29 2.58 VBk1 : Frame 1 2.09 2.29 2.58 VCBH : Color burst high 1.75 1.95 2.23 VRSL2 : Blue background color 2 low 1.61 1.80 2.09 VBK0 : Frame 0 1.52 1.72 2.01 VPD : Pedestal 1.44 1.64 1.93 VRSL0 : Background color (other than blue) low 1.29 1.48 1.77 VRSL1 : Blue background color 1 low 1.20 1.39 1.68 VCBL : Color burst low 1.10 1.29 1.58 VSN : Sync 0.82 1.01 1.30 No. 5731-21/23 LC74788, 74788M, 74788JM Sample Application Circuits (When the LC74788/M/JM is used in conjunction with a single-chip Y/C circuit.) • Circuit Using an External System Clock Input Microcontroller A08693 • Circuit Using a Crystal Oscillator Microcontroller A08694 No. 5731-22/23 LC74788, 74788M, 74788JM • Circuit Using an External System Clock Input (when the pin 3 and 4 functions are modified by mask options) Microcontroller A08695 Note: When a sync tip level of 1.3 V DC (CVIN input signal: sync tip = 1.3 V) is selected for the internal generated video signals by option settings, the electrolytic capacitor connected to SYNIN must be connected with the correct polarity. ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of March, 1998. Specifications and information herein are subject to change without notice. PS No. 5731-23/23