FUJITSU MB90050

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-28829-2E
ASSP For Screen Display Control
CMOS
On-Screen Display Controller
MB90050
■ DESCRIPTION
The MB90050 is an on-screen display controller for displaying text and graphics on the TV screen.
The MB90050 controls a display area of 35 characters by 16 lines, and provides each character composed of 24
× 32 dots at most. The display functions include a wealth of characters with qualifying functions such as character
background shading (shadow casting) , sprite character functions and graphic character functions, contributing
to the use of control GUI displays. The MB90050 incorporates display memory (VRAM) , character font ROM,
and sync signal generation circuit and video signal generation circuit supporting the NTSC and PAL systems,
allowing text and graphics to be displayed in conjunction with a small number of external components.
■ FEATURES
• Main screen display capacity
35 characters × 16 lines (maximum 560 characters)
• Character configuration
Normal characters : 24 × 32 dots
Graphic characters : 12 × 16 dots* (colorable per 1 dot)
(Continued)
■ PACKAGE
48-pin plastic QFP
(FPT-48P-M15)
MB90050
• Font display configuration
Three horizontal width settings (selectable setting L/M/S for each character) per character.
L size : 24 dots
M size : 18 dots
S size : 12 dots
Two vertical height settings (selectable A/B for each line) per line.
A
: 18 to 32 dots (setting per 2 dots)
B
: 18 to 32 dots (setting per 2 dots)
(These sizes are dot sizes of typical character. Each size of graphic characters uses half the number of dots
of typical characters. Note, however, that both of the typical and graphic characters are the same in character
area size.)
• Character types
Usable all 512 character types (font ROM+, font RAM)
Font ROM : 512 character types (all area user setting)
Font RAM : 8 character types (all area user command setting)
Capable of setting a specific eight-character area in font ROM so that the area is replaced with font RAM.
• Display modes
Character
: Normal character/graphic character (set for each character)
Character trimming
: Side trimming 1/side trimming 2/patern background 1/patern background 2
(set for each screen)
Character background : None/Solid-fill/Shaded background (concave) /Shaded background (convex)
(set for each character)
Line background
: None/Solid-fill/Shaded background (concave) /Shaded background (convex)
(set for each line)
Character enlargement : Normal, Double width, Double height, Double width × double height (set for each line)
Brink
: OFF/ON (set for each character)
• Main screen display position control
Horizontal display position : Control in 2-dot units (movable through the entire screen)
Vertical display position
: Control in 2-dot units (movable through the entire screen)
Line spacing control
: 0 to 14 dots, 2-dot units (set for each line)
Sprite character display control
Capable of displaying one block for an arbitrary character on the topmost layer on the screen.
Sprite character display
: OFF/ON (graphic character display)
Sprite character types
: 256 types (character codes 000H to 0FFH)
Sprite character configuration
: 1 character/2 characters horizontal/2 characters vertical/
2×2 characters
Sprite character horizontal display position : Control in 1-dot units
Sprite character vertical display position
: Control in 1-dot units
Screen background color display control
Capable of displaying an arbitrary color on the entire bottommost layer on the screen.
Screen background color display
: OFF/ON
• Display colors
Digital output : 16 colors selectable from among 64 colors (built in palette circuit)
Video output : Any 16 colors selectable (Command setting enable)
(Continued)
2
MB90050
(Continued)
• Display colors and setting units
Character color
: 16 colors (set for each character)
Character background color
: 16 colors (set for each character)
Character trimming color
: 16 colors (set for each line)
Line background color
: 16 colors (set for each line)
Graphic character color
: 16 colors (set for each dot)
Sprite character color
: 16 colors (set for each dot)
Screen background character color
: 16 colors (set for each dot)
Screen background color
: 16 colors (set for all screen)
Shaded background frame highlight color : 16 colors (set for all screen)
Shaded background frame shadow color : 16 colors (set for all screen)
• Digital display signal output
Color signal output
: DCOL5 to DCOL0 pins (6 bits)
Display period signal output
: DB pin
Translucent display period signal output : DH pin
• Analog (video) signal input/output
Composit video input/output : VIN, VOUT pins
Y/C video input/output
: YIN, YOUT pins, CIN, COUT pins
• Internal sync control
Internal sync signal generator and video signal generator supporting the NTSC and PAL systems.
• External interface
16-bit serial input (3-signal input)
Chip select signal
Serial clock signal
Serial data signal
• Package
QFP-48P (FPT-48P-M15)
• Supply voltage
+5 V±10%
* : 1 dot of graphic characters is the same size as 2 × 2 dots of normal characters.
3
MB90050
■ PIN ASSIGNMENT
YOUT
TESTI2
YIN
AVSS2
CIN
AVCC2
COUT
AVSS1
VOUT
AVCC1
VIN
TESTI1
48
47
46
45
44
43
42
41
40
39
38
37
(TOP VIEW)
FLDI
1
36
PO3
VSYNCI
2
35
PO2
HSYNCI
3
34
DCOL5
VCC
4
33
DCOL4
VSS
5
32
DCOL3
EXS
6
31
DCOL2
XS
7
30
DCOL1
FSC4O
8
29
DCOL0
VSYNCO
9
28
DCLKO
HSYNCO
10
27
DB
CSYNCO
11
26
DH
VBLKO
12
25
RESET
13
14
15
16
17
18
19
20
21
22
23
24
FLDO
SYNCST
CS
SCLK
SIN
BUSY
XD
EXD
VSS
VCC
PO0
PO1
MB90050
(FPT-48P-M15)
4
MB90050
■ PIN DESCRIPTIONS
Circuit
Pin
Pin name I/O
type
no.
Function
6,
7
EXS,
XS
I/O
A
Crystal oscillation circuit pins for color burst clock generator.
Connect an external crystal oscillator (14.31818 MHz for NTSC or 17.734475
MHz for PAL) and load capacitance (C) to these pins to form a crystal oscillation
circuit.
20,
19
EXD,
XD
I/O
B
LC oscillation circuit pins for display dot clock generator.
Connect these pins to external “L” and “C” to from an LC oscillation circuit.
15
CS
I
C
Chip select signal input pin.
For serial command transfer, set this pin to the Low level.
16
SCLK
I
C
Serial clock signal input pin.
This pin feeds a clock signal upon transfer of a serial command. It feeds serial
data at the rising edge.
17
SIN
I
C
Serial data signal input pin.
Input data during serial command transfer.
F
Busy signal output pin.
This pin outputs a significant level signal during VRAM filling. Do not input a
serial command while the pin outputs the significant level signal.
Supplying a low level signal to the CS pin during the significant level signal output period terminates the VRAM fill operation and causes this pin to output an
insignificant level signal.
The pin enables output (ON/OFF) control, output logic control, and internal pullup ON/OFF control depending on the command setting.
When the RESET pin inputs a low level signal, this pin outputs the busy signal,
turns off the internal pull-up resistor, and sets the output to OFF (output tied to
the low).
D
Vertical sync signal input pin.
Active low signal or active high signal input is command-selectable for the pin.
When the RESET pin inputs the low level signal, this pin inputs the active low
signal.
D
Horizontal sync signal input pin.
Active low signal or active high signal input is command-selectable for the pin.
When the RESET pin inputs the low level signal, this pin inputs the active low,
horizontal sync signal.
D
Field signal input pin.
The internal field signal identically detected from among input sync signals or the
input signal to this pin is command-selectable for field control.
During operation under external synchronization control, the input signal is used
to control the least significant bit of the font ROM/RAM raster address.
The input signal to this pin is disabled during operation under internal synchronization control.
18
2
3
1
BUSY
VSYNCI
HSYNCI
FLDI
O
I
I
I
(Continued)
5
MB90050
Pin
no.
9
10
11
12
13
14
Pin
name
VSYNCO
HSYNCO
CSYNCO
VBLKO
FLDO
SYNCST
I/O
O
O
O
O
O
O
Circuit
type
Function
F
Vertical sync signal output pin.
The pin enables output (ON/OFF) control, output logic control, and internal pullup ON/OFF control depending on the command setting.
When the RESET pin inputs the low level signal, this pin turns off the internal
pull-up resistor and sets the output to OFF (output tied to the high).
F
Horizontal sync signal output pin.
The pin enables output (ON/OFF) control, output logic control, and internal pullup ON/OFF control depending on the command setting.
When the RESET pin inputs the low level signal, this pin turns off the internal
pull-up resistor and sets the output to OFF (output tied to the high).
F
Composite sync signal output pin.
The pin enables output (ON/OFF) control, output logic control, and internal pullup ON/OFF control depending on the command setting.
When the RESET pin inputs the low level signal, this pin turns off the internal
pull-up resistor and sets the output to OFF (output tied to the high).
F
Vertical blanking interval (VBI) output pin.
The pin enables output (ON/OFF) control, output logic control, and internal pullup ON/OFF control depending on the command setting.
When the RESET pin inputs the low level signal, this pin turns off the internal
pull-up resistor and sets the output to OFF (output tied to the low).
F
Field signal output pin.
During operation under internal synchronization control, this pin outputs the internally generated field signal.
During operation under external synchronization control, the pin outputs the
field signal (internally detected field signal or external input field signal) used for
internal operations.
The pin enables output (ON/OFF) control, output logic control, and internal pullup ON/OFF control depending on the command setting.
When the RESET pin inputs the low level signal, this pin turns off the internal
pull-up resistor and sets the output to OFF (output tied to the low).
F
Synchronization detection signal output pin.
This pin outputs a significant level signal with a sync signal detected and an insignificant level signal with no sync signal detected.
The pin enables output (ON/OFF) control, output logic control, and internal pullup ON/OFF control depending on the command setting.
When the RESET pin inputs the low level signal, this pin turns off the internal
pull-up resistor and sets the output to OFF (output tied to the low).
(Continued)
6
MB90050
Pin
no.
28
8
26
27
34,
33,
32,
31,
30,
29
36,
35,
24,
23
Pin
name
DCLKO
FSC4O
DH
DB
I/O
O
O
O (I)
O (I)
DCOL5,
DCOL4,
DCOL3,
O (I)
DCOL2,
DCOL1,
DCOL0
PO3,
PO2,
PO1,
PO0
O (I)
Circuit
type
Function
G
Dot clock signal output pin.
This pin outputs an LC oscillation clock signal.
The pin enables output (ON/OFF) control depending on the command setting.
The normal clock (that stops oscillation during horizontal synchronization) or continuous clock (that does not stop oscillation during horizontal synchronization*)
can be command-selected for the output using the command setting for output selection control (CKS).
When the TESTI2 pin inputs a low level signal, this pin outputs the continuous
clock signal that does not stop oscillation during horizontal synchronization
(where the output selection control (CKS) setting is disabled).
When the RESET pin inputs the low level signal, the pin outputs a dot clock signal.
* : For continuous clock, this pin is used for frequency measurement. To measure
the dot clock, the pin sets display signal output that is not the standard and
cannot display correctly.
G
Crystal oscillator 4FSC clock signal output pin.
This pin enables output (ON/OFF) control depending on the command setting.
The crystal oscillation clock (4FSC) or its 1/4 frequency clock (FSC) can be command-selected for the output using the command setting for output selection control (FSS).
When the TESTI2 pin inputs the low level signal, this pin outputs the 4FSC clock
signal (where the output selection control (FSS) setting is disabled).
When the RESET pin inputs the low level signal, this pin outputs the 4FSC clock
signal.
H
Halftone display period signal output pin.
This pin enables output (ON/OFF) control and output logic control depending on
the command setting.
When the RESET pin inputs the low level signal, this pin sets the output to OFF
(output tied to the low).
(The input feature of the pin is a test function. Use the pin usually only for output.)
H
Display period signal output pin.
This pin enables output (ON/OFF) control and output logic control depending on
the command setting. When the RESET pin inputs the low level signal, this pin
sets the output to OFF (entering the low level signal fixed output state).
(The input feature of the pin is a test function. Use the pin usually only for output.)
H
Display color signal output pin.
This pin enables output (ON/OFF) control and output logic control depending on
the command setting. When the RESET pin inputs the low level signal, this pin
sets the output to OFF (entering the low level signal fixed output state).
(The input feature of the pin is a test function. Use the pin usually only for output.)
H
Port signal output pin.
This pin enables output level (High/Low) control depending on the command setting. When the RESET pin inputs the low level signal, this pin sets the output to
OFF (entering the low level signal fixed output state).
(The input feature of the pin is a test function. Use the pin usually only for output.)
(Continued)
7
MB90050
(Continued)
Pin
no.
I/O
Circuit
type
Function
25
RESET
I
C
Reset signal input pin.
Upon input of the low level signal, this pin causes an internal reset.
After the power supply is inserted, the reset input is required for normal operation.
During regular operation, the pin inputs the high level signal.
37
TESTI1
I
E
Test signal input pin. Input High level signal during normal operation.
(Input of the Low level signal activates test mode operation.)
47
TESTI2
I
E
Test signal input pin. Input High level signal during normal operation.
38
VIN
I
I
Composite video signal input pin. This pin inputs a DC-reproduced signal of
2 VP-P (pedestal level 1.57 V, sync tip level 1 V) .
46
YIN
I
I
Luminance video signal (Y video signal) input pin.
This pin inputs a DC-reproduced signal of 2 VP-P (pedestal level 1.57 V, sync
tip level 1 V) .
44
CIN
I
I
Saturation video signal (C video signal) input pin.
This pin inputs a signal at 1.57 VDC and a color burst signal amplitude of 0.57
VP-P.
I
Composite video signal output pin.
This pin outputs a signal of 2 VP-P (pedestal level 1.57 V, sync tip level 1 V) .
When the RESET signal inputs the low level signal, this pin outputs the black
video (pedestal level without color burst) signal.
I
Luminance video signal (Y video signal) output pin.
This pin outputs a signal of 2 VP-P (pedestal level 1.57 V, sync tip level 1 V) .
When the RESET pin inputs the low level signal, this pin outputs the black
video (pedestal level) signal.
40
48
8
Pin
name
VOUT
YOUT
O
O
42
COUT
O
I
Saturation video signal (C video signal) output pin.
This pin outputs a signal at 1.57 VDC and a color burst signal amplitude of
0.57 VP-P.
When the RESET pin inputs the low level signal, this pin outputs the black
video signal (a DC voltage of 1.57 V without color burst).
4,
22
VCC
⎯
⎯
Power supply pin for digital circuit. These pins supply +5 V and make all VCC
pins same potential.
5,
21
VSS
⎯
⎯
Digital ground pins. These pins make all VSS pins and AVSS1/AVSS2 pins same
potential.
39
AVCC1
⎯
⎯
Power supply pin for analog circuit and composite video signal Input/Output
(VIN-VOUT) circuit. This pin supplies +5 V. Input analog ground level when
not using this analog circuit.
43
AVCC2
⎯
⎯
Power supply pin for analog circuit, luminance video signal Input/Output
(YIN-YOUT) circuit, and saturation video signal Input/Output (CIN-COUT)
circuit. This pin supplies +5 V. Input analog ground level when not using this
analog circuit.
41,
45
AVSS1,
AVSS2
⎯
⎯
Analog ground pins. AVSS1 pin makes AVSS2 pin same potential.
VSS pins make these pins same potential.
MB90050
■ I/O CIRCUIT TYPES
Type
Circuit
• Crystal oscillation
Oscillator feedback resistor
(approx. 1MΩ)
EXS
A
Remarks
XS
TEST signal
• LC oscillation
EXD
B
XD
STOP signal
• TTL level, Hysteresis input
C
TTL
• CMOS level, Hysteresis input
D
CMOS
5V
• CMOS level, Hysteresis input
with pull-up resistor (approx. 50 kΩ)
E
CMOS
(Continued)
9
MB90050
(Continued)
Type
Circuit
Remarks
• Nch open-drain output
with pull-up resistor SW
(approx. 50 kΩ)
5V
Pch
F
Pull-up
control signal
Nch
• CMOS output
5V
Pch
G
Nch
• CMOS I/O
Input is for test.
5V
Pch
H
Nch
TEST signal
Input
(TEST)
• Analog I/O
CMOS analog SW
I
10
Control signal
MB90050
■ BLOCK DIAGRAM
SIN
SCLK
Serial input
control
Each block
CS
VIN
Analog
switch
YIN
CIN
VOUT
YOUT
COUT
HSYNCI
VSYNCI
Sync control
Video signal
generator circuit
FLDI
SYNCST
HSYNCO
DCOL5 to DCOL0
VSYNCO
CSYNCO
FLDO
Output control
NTSC/PAL
signal
generator
circuit
Display Memory control
BUSY
VRAM
(35 characters
× 16 lines)
EXS
XS
FSC4O
DH
Palette
(4 bits→6 bits)
VBLKO
DB
4FSC clock
oscillation
circuit
Font ROM
(512 characters)
Font RAM
(8 characters)
PO3
Each block
Port control
PO2
PO1
PO0
EXD
XD
DCLKO
RESET
Dot clock
oscillation
circuit
Each block
All reset
11
MB90050
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.5
VSS + 7.0
V
*2
AVCC1
VSS − 0.5
VSS + 7.0
V
*2
AVCC2
VSS − 0.5
VSS + 7.0
V
*2
VIN
VSS − 0.5
VCC + 0.5
V
VOUT
VSS − 0.5
VCC + 0.5
V
“L” level maximum output current
IOL
⎯
15
mA
“H” level maximum output current
IOH
⎯
−15
mA
Power consumption
Pd
⎯
500
mW
Operating temperature
Ta
−40
+85
°C
Tstg
−55
+125
°C
1
Power supply voltage*
Input voltage*1
Output voltage*1
Storage temperature
*1 : The parameter is based on VSS = AVSS1 = AVSS2 = 0 V.
*2 : Do not make a potential difference between AVSS (AVSS1/AVSS2) pins and VSS pin.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
12
MB90050
■ RECOMMENDED OPERATING CONDITIONS
(VSS = AVSS1 = AVSS2 = 0 V)
Parameter
Power supply voltage
“H” level input voltage
“L” level input voltage
Analog input voltage
Operating temperature
Symbol
Value
Unit
Remarks
(circuit type)
Min
Max
VCC
4.5
5.5
V
AVCC1
4.5
5.5
V
*1, *2
AVCC2
4.5
5.5
V
*1, *3
VIH1
0.7 × VCC
VCC + 0.3
V
(H)
VIH1S
0.8 × VCC
VCC + 0.3
V
(D, E)
VIH2S
0.6 × VCC
VCC + 0.3
V
(C)
VIL1
VSS − 0.3
0.3 × VCC
V
(H)
VIL1S
VSS − 0.3
0.2 × VCC
V
(D, E)
VIL2S
VSS − 0.3
0.6
V
(C)
AVIN1
0
AVCC1
V
VIN pin
AVIN2
0
AVCC2
V
YIN pin, CIN pin
Ta
−40
+85
°C
*1 : Do not make a potential difference between AVSS (AVSS1/AVSS2) pins and VSS pin.
*2 : It is possible to set AVCC1 = AVSS (AVSS1/AVSS2) when not using composite video signal (VIN pin, VOUT pin) .
*3 : It is possible to set AVCC2 = AVSS (AVSS1/AVSS2) when not using Y/C separated video signals (YIN pin, YOUT pin,
CIN pin and COUT pin) .
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
13
MB90050
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(VSS = AVSS1 = AVSS2 = 0 V, Ta = −40 °C to +85 °C)
Parameter
Symbol
Pin name
“H” level output voltage
VOH
All output
pins
“L” level output voltage
VOL
Pull-up resistor
Power supply current
Analog power supply
current
14
Conditions
Value
Unit
Min
Typ
Max
VCC = 4.5 V,
IOH = −4.0 mA
4.0
⎯
⎯
V
All output
pins
VCC = 4.5 V,
IOL = 4.0 mA
⎯
⎯
0.4
V
RP
E, F
VCC = 5.5 V
25
50
200
kΩ
ICC
VCC
VCC = 5.5 V,
4FSC = 20 MHz,
fDC = 20 MHz
⎯
35
45
mA
IA
AVCC1,
AVCC2
VCC = AVCC1 = AVCC2 = 5.5 V,
4FSC = 0 MHz,
AVIN1 = AVIN2 = 1.65 V,
No load
⎯
22
40
mA
VIN-VOUT,
VCC = AVCC1 = AVCC2 = 4.5 V,
YIN-YOUT,
IOL = 100 µA
CIN-COUT
⎯
215
310
Ω
ON resistor
RON
OFF leak current
IOFF
VIN,
YIN,
CIN
VCC = AVCC1 = AVCC2 = 5.5 V,
AVIN1 = AVIN2 = 5.5 V
⎯
0.1
10
µA
Output resistor
ROUT
VOUT,
YOUT,
COUT
VCC = AVCC1 = AVCC2 = 4.5 V,
IOL = 100 µA
100
⎯
1800
Ω
MB90050
Analog Ladder Voltage
Min
(VCC = AVCC1 = AVCC2 = 5.0 V)
Value
Unit
Typ
Max
Resistance ladder voltage 00 (−40 IRE)
930
1000
1040
mV
VOHR1
Resistance ladder voltage 01 (−36 IRE)
988
1057
1098
mV
VOHR2
Resistance ladder voltage 02 (−32 IRE)
1046
1114
1156
mV
VOHR3
Resistance ladder voltage 03 (−28 IRE)
1104
1171
1214
mV
VOHR4
Resistance ladder voltage 04 (−24 IRE)
1162
1229
1272
mV
VOHR5
Resistance ladder voltage 05 (−20 IRE)
1220
1286
1330
mV
VOHR6
Resistance ladder voltage 06 (−16 IRE)
1278
1343
1388
mV
VOHR7
Resistance ladder voltage 07 (−12 IRE)
1336
1400
1446
mV
VOHR8
Resistance ladder voltage 08 (−8 IRE)
1394
1457
1504
mV
VOHR9
Resistance ladder voltage 09 (−4 IRE)
1452
1514
1562
mV
VOHR10
Resistance ladder voltage 10 (0 IRE)
1510
1571
1620
mV
VOHR11
Resistance ladder voltage 11 (4 IRE)
1568
1629
1678
mV
Symbol
Parameter
VOHR0
VOHR12
Resistance ladder voltage 12 (8 IRE)
1626
1686
1736
mV
VOHR13
Resistance ladder voltage 13 (12 IRE)
1684
1743
1794
mV
VOHR14
Resistance ladder voltage 14 (16 IRE)
1742
1800
1852
mV
VOHR15
Resistance ladder voltage 15 (20 IRE)
1800
1857
1910
mV
VOHR16
Resistance ladder voltage 16 (24 IRE)
1858
1914
1968
mV
VOHR17
Resistance ladder voltage 17 (28 IRE)
1916
1971
2026
mV
VOHR18
Resistance ladder voltage 18 (32 IRE)
1974
2029
2084
mV
VOHR19
Resistance ladder voltage 19 (36 IRE)
2032
2086
2142
mV
VOHR20
Resistance ladder voltage 20 (40 IRE)
2090
2143
2200
mV
VOHR21
Resistance ladder voltage 21 (44 IRE)
2148
2200
2258
mV
VOHR22
Resistance ladder voltage 22 (48 IRE)
2206
2257
2316
mV
VOHR23
Resistance ladder voltage 23 (52 IRE)
2264
2314
2374
mV
VOHR24
Resistance ladder voltage 24 (56 IRE)
2322
2371
2432
mV
VOHR25
Resistance ladder voltage 25 (60 IRE)
2380
2429
2490
mV
VOHR26
Resistance ladder voltage 26 (64 IRE)
2438
2486
2548
mV
VOHR27
Resistance ladder voltage 27 (68 IRE)
2496
2543
2606
mV
VOHR28
Resistance ladder voltage 28 (72 IRE)
2554
2600
2664
mV
VOHR29
Resistance ladder voltage 29 (76 IRE)
2612
2657
2722
mV
VOHR30
Resistance ladder voltage 30 (80 IRE)
2670
2714
2780
mV
VOHR31
Resistance ladder voltage 31 (84 IRE)
2728
2771
2838
mV
VOHR32
Resistance ladder voltage 32 (88 IRE)
2786
2829
2896
mV
VOHR33
Resistance ladder voltage 33 (92 IRE)
2844
2886
2954
mV
VOHR34
Resistance ladder voltage 34 (96 IRE)
2902
2943
3012
mV
VOHR35
Resistance ladder voltage 35 (100 IRE)
2960
3000
3070
mV
15
MB90050
MB90050 Palette Initial Value
• Pedestal level
Color code
Comment
⎯
Pedestal
Relative value
Absolute value
Register setting value
PED (IRE)
PED (IRE)
PED (HEX)
0
40
0A
Relative value
Absolute value
Register setting value
SYN (IRE)
SYN (IRE)
SYN (HEX)
−40
0
00
Relative value
Absolute value
Register setting value
HAN (IRE)
HAN (IRE)
HAN (HEX)
32
72
12
• Sink chip level
Color code
Comment
⎯
Sink chip
• Translucence level
Color code
Comment
⎯
translucence
• Color burst level
Relative value
Color code
Comment
⎯
Burst
Absolute value
Register setting value
BST0 BST1 BST2 BST3 BST0 BST1 BST2 BST3 BST0 BST1 BST2 BST3
(IRE) (IRE) (IRE) (IRE) (IRE) (IRE) (IRE) (IRE) (HEX) (HEX) (HEX) (HEX)
0
−24
0
24
40
16
40
64
0A
04
0A
10
• Y (COLOR)
16
Relative value
Absolute value
Register setting value
Luminance (IRE)
YD (IRE)
YD (HEX)
White-1
100
140
23
14
Yellow-1
72
112
1C
13
Cyan-1
64
104
1A
12
Green-1
56
96
18
11
Magenta-1
40
80
14
10
Red-1
32
72
12
9
Blue-1
24
64
10
8
Black-1
16
56
0E
7
White-0
92
132
21
6
Yellow-0
64
104
1A
5
Cyan-0
56
96
18
4
Green-0
48
88
16
3
Magenta-0
32
72
12
2
Red-0
24
64
10
1
Blue-0
16
56
0E
0
Black-0
8
48
0C
Color code
Comment
15
MB90050
• C (COLOR)
Relative value
Color code
Comment
Absolute value
Register setting value
(degrees)
Amplitude
(IRE)
0
90
180
270
Phase
CD0
CD1
CD2
CD3
(HEX) (HEX) (HEX) (HEX)
15
White-1
0
0
40
40
40
40
0A
0A
0A
0A
14
Yellow-1
195
20
35
21
45
59
09
05
0B
0F
13
Cyan-1
284
36
5
49
75
31
01
0C
13
08
12
Green-1
241
30
14
25
66
55
03
06
11
0E
11
Magenta-1
61
30
66
55
14
25
11
0E
03
06
10
Red-1
104
36
75
31
5
49
13
08
01
0C
9
Blue-1
15
20
45
59
35
21
0B
0F
09
05
8
Black-1
0
0
40
40
40
40
0A
0A
0A
0A
7
White-0
0
0
40
40
40
40
0A
0A
0A
0A
6
Yellow-0
195
20
35
21
45
59
09
05
0B
0F
5
Cyan-0
284
36
5
49
75
31
01
0C
13
08
4
Green-0
241
30
14
25
66
55
03
06
11
0E
3
Magenta-0
61
30
66
55
14
25
11
0E
03
06
2
Red-0
104
36
75
31
5
49
13
08
01
0C
1
Blue-0
15
20
45
59
35
21
0B
0F
09
05
0
Black-0
0
0
40
40
40
40
0A
0A
0A
0A
• V (COLOR)
Absolute value
Color code
Comment
15
Register setting value
0
90
180
270
VD0
(HEX)
VD1
(HEX)
VD2
(HEX)
VD3
(HEX)
White-1
140
140
140
140
23
23
23
23
14
Yellow-1
107
93
117
131
1B
17
1D
21
13
Cyan-1
69
113
139
95
11
1C
23
18
12
Green-1
70
81
122
111
11
14
1F
1C
11
Magenta-1
106
95
54
65
1B
18
0D
10
10
Red-1
107
63
37
81
1B
10
09
14
9
Blue-1
69
83
59
45
11
15
0F
0B
8
Black-1
56
56
56
56
0E
0E
0E
0E
7
White-0
132
132
132
132
21
21
21
21
6
Yellow-0
99
85
109
123
19
15
1B
1F
5
Cyan-0
61
105
131
87
0F
1A
21
16
4
Green-0
62
73
114
103
0F
12
1D
1A
3
Magenta-0
98
87
46
57
19
16
0B
0E
2
Red-0
99
55
29
73
19
0E
07
12
1
Blue-0
61
75
51
37
0F
13
0D
09
0
Black-0
48
48
48
48
0C
0C
0C
0C
17
MB90050
• M (MONO)
Relative value
Absolute value
Register setting value
Luminance (IRE)
MD (IRE)
MD (HEX)
Level-17
100
140
23
14
Level-16
80
120
1E
13
Level-15
68
108
1B
12
Level-14
60
100
19
11
Level-13
44
84
15
10
Level-12
36
76
13
9
Level-11
24
64
10
8
Level-10
16
56
0E
7
Level-07
92
132
21
6
Level-06
72
112
1C
5
Level-05
60
100
19
4
Level-04
52
92
17
3
Level-03
36
76
13
2
Level-02
28
68
11
1
Level-01
16
56
0E
0
Level-00
8
48
0C
Color code
Comment
15
Note : Minimum value for absolute value of IRE is 0.
Maximum value for absolute value of IRE is 140.
Relative value is the value when the pedestal level is 0IRE.
• D (DIGITAL)
18
Color code
Comment
15
Display color signal output pin
Register setting value
DCOL5
DCOL4
DCOL3
DCOL2
DCOL1
DCOL0
DD (HEX)
Level-15
0
0
1
1
1
1
0F
14
Level-14
0
0
1
1
1
0
0E
13
Level-13
0
0
1
1
0
1
0D
12
Level-12
0
0
1
1
0
0
0C
11
Level-11
0
0
1
0
1
1
0B
10
Level-10
0
0
1
0
1
0
0A
9
Level-09
0
0
1
0
0
1
09
8
Level-08
0
0
1
0
0
0
08
7
Level-07
0
0
0
1
1
1
07
6
Level-06
0
0
0
1
1
0
06
5
Level-05
0
0
0
1
0
1
05
4
Level-04
0
0
0
1
0
0
04
3
Level-03
0
0
0
0
1
1
03
2
Level-02
0
0
0
0
1
0
02
1
Level-01
0
0
0
0
0
1
01
0
Level-00
0
0
0
0
0
0
00
MB90050
• VOUT Output
• YOUT Output
• COUT Output
Note : Voltage of each output depends on palette setting value.
19
MB90050
2. AC Characteristics
Parameter
Shift clock cycle time
Shift clock pulse width
Shift clock signal rise/fall time
Symbol
tCYC
tWCH
tWCL
tCR
tCF
(Ta = −40 °C to +85 °C, VCC = 5.0 V±10 %, VSS = 0 V)
Value
Pin name
Unit
Remarks
Min
Max
SCLK
SCLK
SCLK
⎯
ns
100
⎯
ns
100
⎯
ns
⎯
200
ns
⎯
200
ns
Shift clock start time
tSS
SCLK
100
⎯
ns
Data setup time
tSU
SIN
100
⎯
ns
Data hold time
tH
SIN
50
⎯
ns
Chip select end time
tEC
CS
100
⎯
ns
⎯
200
ns
⎯
200
ns
Chip select signal rise/fall time
tCRC
tCFC
CS
Horizontal sync signal rise time
tHR
HSYNCI
⎯
200
ns
Horizontal sync signal fall time
tHF
HSYNCI
⎯
200
ns
Vertical sync signal rise time
tVR
VSYNCI
⎯
200
ns
Vertical sync signal fall time
tVF
VSYNCI
⎯
200
ns
Horizontal sync signal pulse width
tWH
HSYNCI
4.0
8.0
µs
Vertical sync signal pulse width
tWV
VSYNCI
1
5
H*
1
⎯
H*
1
⎯
H*
tWFH
Field signal pulse width
FLDI
tWFL
Reset input pulse width
tWR
RESET
* : 1 H is assumed to be one horizontal sync signal period.
20
250
10
⎯
µs
Refer to
“Serial Input
Timing”
Refer to
“Vertical•
Horizontal
Sync Signal
Input
Timing”
Refer to
“Field
Signal Input
Timing”
Refer to
“Reset
Signal Input
Timing”
MB90050
• Serial Input Timing
CS
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tCRC
tSS
tCYC
tEC
tCFC
0.8 VCC
SCLK
0.2 VCC
tWCH
tCR
tWCL
tCF
tH
tSU
0.8 VCC
SIN
0.2 VCC
• Vertical•Horizontal Sync Signal Input Timing
HSYNCI
0.8 VCC
0.8 VCC
0.2 VCC
tHF
VSYNCI
tWH
0.8 VCC
tHR
0.8 VCC
0.2 VCC
tVF
0.2 VCC
tWV
0.2 VCC
tVR
21
MB90050
• Field Signal Input Timing
FLDI
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tWFL
tWFH
• Reset Signal Input Timing
RESET
0.2 VCC
tWR
22
0.2 VCC
MB90050
3. Recommended Input Timings
H/V-separated sync signal input timing
Parameter
NTSC
PAL
Unit
60 (59.94)
30
Hz
*1
1 to 5
1 to 4
H
*2
63.492 (63.5555)
64
µs
*1
4.19 to 5.71 (4.7 ± 0.1)
4.5 to 4.9
µs
*1
Vertical sync signal frequency
Vertical sync signal pulse width
Horizontal sync signal period
Horizontal sync signal pulse width
Remaeks
*1 : Parenthesized values are specifications for color information display.
*2 : 1 H is assumed to be one horizontal sync signal period.
4. Clock Timing
Parameter
Dot clock for display*
Clock for color burst
(NTSC) *
Clock for color burst
(PAL) *
Symbol
Pin
fDC
EXD
XD
4FSC
EXS
XS
Value
Unit
Min
Typ
Max
8
⎯
20
MHz
⎯
14.318185
⎯
MHz
⎯
17.734475
⎯
MHz
Remarks
* : Input the signal with a duty cycle of 50%.
23
MB90050
5. Output Timings
(1) Horizontal timing
Symbol
NTSC (or simple PAL)
PAL (or simple NTSC)
HPS
0
0
EQP1E
34
42
HPE
68
84
BSTS
76
100
BSTE
112
140
HBLKE
143
186
SEP1S
388
484
EQP2S
455
568
EQP2E
489
610
SEP2S
842
1050
HBLKS
888
1106
IHCLR
910
1135
(1137) *
Remarks
Refer to
“NTSC/PAL
Horizontal
Timing”.
* : Parenthesized values assume the last raster in each V cycle (field) .
Note : The values in the above list are 4FSC count values.
(2) Verticl timing
Symbol
NTSC (or simple NTSC)
PAL (or simple PAL)
Interlaced
Non interlaced
Interlaced
Non interlaced
VPS
0
0
0
0
VPE
6
6
5
5
EQPE
12
12
10
10
VBLKE
36
36
45
45
VBLKS
519
519
620
620
VPS
525
526
625
624
Remarks
Refer to
“NTSC
Vertical
Timing”
and
“PAL
Vertical
Timing”.
Note : The values in the about list are 1/2 H count values. (1 H is assumed to be one horizontal sync signal period.)
24
MB90050
• NTSC/PAL Horizontal Timing
Video signal
Horizontal sync signal
Horizontal retrace blanking
interval
Burst flag
Equalizing pulse
Cut-in pulse
EQP2E
EQP2S
SEP1S
IHCLR
HBLKS
SEP2S
HBLKE
BSTE
BSTS
HPE
EQP1E
HPS
HBLKS
25
26
Equalizing pulse interval
Vertical retrace blanking interval
Vertical sync interval
Composite video signal
Horizontal scanning line No.
Odd-numbered field
Equalizing pulse interval
Vertical retrace blanking interval
Vertical sync interval
Composite video signal
Horizontal scanning line No.
Even-numbered field
VBLKS
259 260 261
VBLKS
521 522 523
262
524
1
VPS
263
264
VPS
525
265
2
VPE
4
5
VPE
266 267 268
3
7
EQPE
269
270
EQPE
6
··
··
19
280
20
VBLKE
281 282
VBLKE
18
··
··
261
262
1
VPS
263
VPS
523 524 525
VBLKS
260
VBLKS
521 522
258 259
MB90050
• NTSC Vertical Timing
VBLKS
BSTE
VBLKS
621 622 623
BSTE
312
624
312
1
1
314
VPS
313
314
VPS
625
VPS
313
VPS
625
VPE
3
VPE
3
VPE
315 316
2
VPE
315 316
2
317
4
6
7
318 319
6
EQPE
320
7
BSTS
318 319
EQPE, BSTS
5
320
EQPE BSTS
5
EQPE BSTS
317
4
··
··
··
··
336
VBLKE
23
336
VBLKE
23
VBLKE
335
22
VBLKE
335
22
337
24
337
24
··
··
··
··
310
311
312
311
1
VPS
313
312
VPS
1
VPS
313
VPS
623 624 625
BSTE, VBLKS
310
VBLKS
623 624 625
BSTE VBLKS
621 622
308 309
BSTE
621 622
BSTE VBLKS
308 309
Notes : • ◆ indicates the HSYNC positions in the equalizing pulse intends.
• The arrows marks indicate the phase of color subcarrier. (↑ : +135°, ↓ : −135°)
BSTE, VBLKS
Color burst phase
309 310 311
Composite video signal
Horizontal scanning line No.
Vertical sync interval
Vertical retrace blanking interval
Equalizing pulse interval
Fourth field
Color burst phase
Composite video signal
Horizontal scanning line No.
Vertical sync interval
Vertical retrace blanking interval
Equalizing pulse interval
Third field
624
BSTE VBLKS
621 622 623
Color burst phase
Composite video signal
309 310 311
Horizontal scanning line No.
Vertical sync interval
Vertical retrace blanking interval
Equalizing pulse interval
Second field
Color burst phase
Composite video signal
Horizontal scanning line No.
Vertical sync interval
Vertical retrace blanking interval
Equalizing pulse interval
First field
MB90050
• PAL Vertical Timing
27
MB90050
■ COMMAND LIST
Command
no. 15 to 12
Command code/data
11
10
9
8
7
6
FL
0
5
4
3
2
1
0
VRAM write
address setting
0
0000
AY3 AY2 AY1 AY0
1
0001
MS1 MS0 MM1 MM0 MB3 MB2 MB1 MB0 MC3 MC2 MC1 MC0
Character data setting 1
2
0010
MR
M3
M2
M1
M0
Character data setting 2
3
0011
LHS LW2 LW1 LW0 LFD LFC LFB LFA LF3
LF2
LF1
LF0
Line control data
setting 1
4
0100
LDS
0
L3
L2
L1
L0
Line control data
setting 2
5-0
0101
0
0
DSP
0
0
0
0
Screen output
control 1
5-1
0101
0
1
FM1 FM0 BT1 BT0 BD1 BD0
0
0
0
0
Screen output
control 1
5-2
0101
1
0
0
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Vertical display
position control
5-3
0101
1
1
0
X8
X7
X6
X5
X4
X3
X2
X1
X0
Horizontal display
position control
6-0
0110
0
0
0
0
0
HA
Character vertical
size control
6-1
0110
0
1
0
0
Shaded
BH3 BH2 BH1 BH0 BS3 BS2 BS1 BS0 background frame
color control
6-2
0110
1
0
TC
HC
Transparent/semiTC3 TC2 TC1 TC0 HC3 HC2 HC1 HC0 transparent colors
control
6-3
0110
1
1
GF
GC
GF3 GF2 GF1 GF0 GC3 GC2 GC1 GC0
7-3
0111
1
1
1
0
8-1
1000
0
1
8-2
1000
1
0
9-0
1001
0
0
SY9 SY8 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0
Sprite character
control 3
9-1
1001
1
0
SX9 SX8 SX7 SX6 SX5 SX4 SX3 SX2 SX1 SX0
Sprite character
control 4
MG MBL
M8
LG1 LG0
0
0
M7
LD
M6
LE
SDS UDS
0
AX5 AX4 AX3 AX2 AX1 AX0
Function
M5
M4
LM1 LM0
0
HB2 HB1 HB0
0
0
0
0
U3
HA2 HA1
U2
U1
U0
SD1 SD0 SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0
1
SBL
0
SH2 SH1 SH0
0
0
0
0
Graphic color
control
Screen background
control
Sprite character
control 1
Sprite character
control 2
(Continued)
28
MB90050
(Continued)
Command
no. 15 to 12 11
Command code/data
10
9
8
7
FDS FDC MC
6
5
4
3
2
1
NP2 NP1 NP0
IN1
IN0
IE1
0
Function
11-0
1011
0
0
11-1
1011
0
1
0
0
VIX
HIX
0
0
VHE
HE
0
0
11-3
1011
1
1
0
0
0
H2
H1
H0
0
F2
F1
F0
12-0
1100
0
0
STO BUO VSO HSO CSO VBO FDO DHO DBO DCO Output pin control 1
12-1
1100
0
1
STX BUX VOX HOX COX VBX FDX DHX DBX DCX Output pin control 2
12-2
1100
1
0
STU BUU VSU HSU CSU VBU FDU
12-3
1100
1
1
CKO FSO CKS FSS
13-0
1101
0
0
13-1
1101
1
14-0
1110
0
0
0
14-1
1110
0
1
0
0
0
0
0
0
IE0 Sync control 1
0
Sync control 2
Sync detection control
Output pin control 3
PO3 PO2 PO1 PO0 Output pin control 4
PLV PLY PLC PLM PLD PL3 PL2 PL1 PL0 Color palette setting
AA2 AA1 AA0
0
0
AD5 AD4 AD3 AD2 AD1 AD0 Analog level control
0
0
0
0
FRS
0
0
0
0
0
0
0
0
FA1 FA0 Font RAM setting 1
FR2 FR1 FR0 Font RAM setting 2
Note : When a reset signal is input (L level signal input to RESET pin) , the screen output control 1 (command 5
to command 0) bits (SDS, UDS and DSP) and the output pin control 1 to 4 (command 12-0 to command 123) bits are initialized to “0”.The color palette setting (command 13-0) and analog level control (command
13-1) bits are internally set to their predetermined initial values.The contents of other register bits, VRAM
and font RAM are undefined. After reset input (release) is completed, set all command and font RAM settings.
29
MB90050
■ SAMPLE CIRCUIT
MB90050
Composite IN
Composite OUT
Video amplifier
&
clamp circuit
VIN
VOUT
Buffer circuit
YIN/CIN
YOUT/COUT
Video amplifier
&
clamp circuit
Sync
separation
circuit
YIN
YOUT
CIN
COUT
Buffer circuit
VSYNCI
HSYNCI
CS
Control
microcontroller
SCLK
SIN
BUSY
+5V
AVCC1
AVCC2
+
AVSS1
AVSS2
+5V
VCC
+
VSS
XD
EXD
3.3 µH
20 pF
XS
20 pF
(Approx. 14 MHz)
30
EXS
NTSC: 14.31818 MHz
PAL : 17.734475 MHz
MB90050
■ MB90050-001 FONT DATA (MB90050-001 is typical product. )
000
001
002
003
004
005
006
007
008
009
00A
00B
00C
00D
00E
00F
010
011
012
013
014
015
016
017
018
019
01A
01B
01C
01D
01E
01F
020
021
022
023
024
025
026
027
028
029
02A
02B
02C
02D
02E
02F
030
031
032
033
034
035
036
037
038
039
03A
03B
03C
03D
03E
03F
(Continued)
31
MB90050
040
041
042
043
044
045
046
047
048
049
04A
04B
04C
04D
04E
04F
050
051
052
053
054
055
056
057
058
059
05A
05B
05C
05D
05E
05F
060
061
062
063
064
065
066
067
068
069
06A
06B
06C
06D
06E
06F
070
071
072
073
074
075
076
077
078
079
07A
07B
07C
07D
07E
07F
(Continued)
32
MB90050
080
081
082
083
084
085
086
087
088
089
08A
08B
08C
08D
08E
08F
090
091
092
093
094
095
096
097
098
099
09A
09B
09C
09D
09E
09F
0A0
0A1
0A2
0A3
0A4
0A5
0A6
0A7
0A8
0A9
0AA
0AB
0AC
0AD
0AE
0AF
0B0
0B1
0B2
0B3
0B4
0B5
0B6
0B7
0B8
0B9
0BA
0BB
0BC
0BD
0BE
0BF
(Continued)
33
MB90050
0C0
0C1
0C2
0C3
0C4
0C5
0C6
0C7
0C8
0C9
0CA
0CB
0CC
0CD
0CE
0CF
0D0
0D1
0D2
0D3
0D4
0D5
0D6
0D7
0D8
0D9
0DA
0DB
0DC
0DD
0DE
0DF
0E0
0E1
0E2
0E3
0E4
0E5
0E6
0E7
0E8
0E9
0EA
0EB
0EC
0ED
0EE
0EF
0F0
0F1
0F2
0F3
0F4
0F5
0F6
0F7
0F8
0F9
0FA
0FB
0FC
0FD
0FE
0FF
(Continued)
34
MB90050
100
101
102
103
104
105
106
107
108
109
10A
10B
10C
10D
10E
10F
110
111
112
113
114
115
116
117
118
119
11A
11B
11C
11D
11E
11F
120
121
122
123
124
125
126
127
128
129
12A
12B
12C
12D
12E
12F
130
131
132
133
134
135
136
137
138
139
13A
13B
13C
13D
13E
13F
(Continued)
35
MB90050
140
141
142
143
144
145
146
147
148
149
14A
14B
14C
14D
14E
14F
150
151
152
153
154
155
156
157
158
159
15A
15B
15C
15D
15E
15F
160
161
162
163
164
165
166
167
168
169
16A
16B
16C
16D
16E
16F
170
171
172
173
174
175
176
177
178
179
17A
17B
17C
17D
17E
17F
(Continued)
36
MB90050
180
181
182
183
184
185
186
187
188
189
18A
18B
18C
18D
18E
18F
190
191
192
193
194
195
196
197
198
199
19A
19B
19C
19D
19E
19F
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
1AA
1AB
1AC
1AD
1AE
1AF
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
1B9
1BA
1BB
1BC
1BD
1BE
1BF
(Continued)
37
MB90050
(Continued)
38
1C0
1C1
1C2
1C3
1C4
1C5
1C6
1C7
1C8
1C9
1CA
1CB
1CC
1CD
1CE
1CF
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
1DA
1DB
1DC
1DD
1DE
1DF
1E0
1E1
1E2
1E3
1E4
1E5
1E6
1E7
1E8
1E9
1EA
1EB
1EC
1ED
1EE
1EF
1F0
1F1
1F2
1F3
1F4
1F5
1F6
1F7
1F8
1F9
1FA
1FB
1FC
1FD
1FE
1FF
MB90050
■ ORDERING INFORMATION
Part number
Package
MB90050PF
48-pin, plastic QFP
(FPT-48P-M15)
Remarks
39
MB90050
■ PACKAGE DIMENSION
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
48-pin, plastic QFP
(FPT-48P-M15)
15.30±0.40(.602±.016)SQ
* 12.00±0.10(.472±.004)SQ
36
0.17±0.06
(.007±.002)
25
Details of "A" part
24
37
+0.30
2.40 –0.20
+.012
.094 –.008
(Mounting height)
0.10(.004)
INDEX
0~8˚
13
48
1
0.80(.031)
C
"A"
12
0.32±0.05
(.013±.002)
0.20(.008)
0.85±0.30
(.033±.012)
+0.10
0.25 –0.20
+.004
.010 –.008
(Stand off)
M
2003 FUJITSU LIMITED F48025S-c-3-4
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
40
MB90050
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0412
© 2004 FUJITSU LIMITED Printed in Japan