SANYO LC868112A

Ordering number : ENN*6724
CMOS IC
LC868116/12/08A
8-Bit Single Chip Microcontroller with
16/12/08K-Byte ROM and 640-Byte RAM On Chip
Preliminary
Overview
The LC868116A/12A/08A microcontrollers are 8-bit single chip microcontrollers with the following on-chip functional
blocks :
- CPU : Operable at a minimum bus cycle time of 0.5µs (microseconds)
- On-chip ROM maximum capacity : 16K bytes
- On-chip RAM capacity : 640 bytes
- Dot-matrix liquid crystal display (LCD) automatic display controller / driver
- External memory
- 16-bit timer / counter (or two 8-bit timers)
- 16-bit timer / PWM (or two 8-bit timers)
- Two 8-bit synchronous serial-interface circuits
- 13-source 9-level vectored interrupt system
All of the above functions are fabricated on a single chip
Ver.1.1
21998
91400 RM (IM) HO No.6724-1/28
LC868116/12/08A
Features
16384 × 8 bits
12288 × 8 bits
8192 × 8 bits
(1) Read Only Memory (ROM)
: LC868116A
: LC868112A
: LC868108A
(2) Random Access Memory (RAM)
: 512 × 8 bits (calculation area)
128 × 8 bits (display area)
(3) Bus Cycle Time / Instruction Cycle Time
Bus cycle
Instruction
System clock
time
cycle time
oscillation
Ceramic (CF)
0.5µs
1µs
1µs
2µs
Ceramic (CF)
2µs
4µs
Ceramic (CF)
Internal RC
7.5µs
15µs
3.8µs
7.5µs
Crystal (XTAL)
183µs
366µs
91.5µs
183µs
* Bus cycle time means ROM-read period.
OCR7 : Bit-7 of the oscillation control register.
Oscillation
frequency
12MHz
6MHz
Voltage
Note
4.5-6.0V
OCR7=0
OCR7=1
4.5-6.0V
OCR7=0
OCR7=1
OCR7=0
OCR7=1
OCR7=0
OCR7=1
OCR7=0
OCR7=1
6MHz
3MHz
3MHz
1.5MHz
800kHz
2.5-6.0V
32.768kHz
2.5-6.0V
2.5-6.0V
excluding
external memory
access function
for external
memory access
(4) Ports
- Input / output ports
: 6 ports (47 terminals)
Input/output port programmable in a nibble
: 1 port (8 terminals)
Input/output port programmable every function unit : 1 port (7 terminals)
Input/output port programmable in a bit
: 4 ports (32 terminals)
- Input port
: 1 port (4 terminals)
- Ports at external memory mode
1. External Latch
Port 0 : Address output of lower 8-bit, input/output of data
Port 2 : Address output of upper 8-bit
Port 5 : Bank address output
2. No External Latch
Port 0 : Input/output of data
Port 3 : Address output of lower 8-bit
Port 2 : Address output of upper 8-bit
Port 5 : Bank address output
(Set whether the external latch is used or not by program.)
- LCD segment driver output ports
: 48 terminals
(Function change available : segment/common)
- LCD common driver output ports
: 16 terminals
(1/32 duty maximum : at using segment output ports as common output by mask option)
(5) External memory access
- External program memory access function
External program memory capacity : 64K bytes
Programable switch internal program/external program
(At initial : Internal program)
Enable/disable control of external program ! internal program memory switch
No.6724-2/28
LC868116/12/08A
- Ports
Port 2 : Address output of upper 8-bit
Uses EROE terminal ( OE signal of the external ROM)
1. Using the external latch
Port 0 : Address output of lower 8-bit, data input port
Uses the ADLC terminal (latch clock of the lower 8-bit address signal)
2. Not use the external latch
Port 0 : Input port of data
Port 3 : Address output of lower 8-bit
- External data memory access function
Using the LDC instruction
External memory capacity : 16M bytes
1. Internal program memory
Switch the reference of internal ROM data/external ROM data by program.
2. External program memory
Reference external ROM data only.
Ports
Port 2 : Address output of upper 8-bit
Port 5 : Bank address output
Uses EROE terminal ( OE signal of the external ROM)
1. Using external latch
Port 0 : Address output of lower 8-bit, input port of data
Uses the ADLC terminal (latch clock of the lower 8-bit address signal)
2. Not use external latch
Port 0 : Input port of data
Port 3 : Address output of lower 8-bit
- External RAM memory access function
Using the LDX, STX instruction
External memory capacity : 16M bytes
Ports
Port 2 : Address output of upper 8-bit
Port 5 : Bank address output
Uses the P46 terminal ( OE signal of external RAM) : the LDX instruction execution
Uses the P47 terminal ( WE signal of external RAM) : the STX instruction execution
1. Using the external latch circuit
Port 0 : Address output of lower 8-bit, input/output port of data
Uses the ADLC terminal (latch clock of the lower 8-bit address signal)
2. Not use the external latch circuit
Port 0 : Input/output port of data
Port 3 : Address output of lower 8-bit
(6) LCD automatic display controller
- Display duty
: 1/4 - 1/32 duty
* Up to 1/32 display duty can be specified by program.
this range.
- Display bias
: 1/4, 1/5, 1/7 bias
- Programmable character display / graphic display
- Character display
1. On-chip character generator ROM
ROM capacity
: 8960 bits
Character font
: 5 × 7 dots
Number of Characters
: 256
VDD allows up to 6V.
Select the preferable LCD panel within
No.6724-3/28
LC868116/12/08A
2. LCD instruction
Display
: ON/OFF
Cursor
: ON/OFF/BLINK
Character blink
: ON/OFF
Character scroll
: Control by specified starting address
- Graphic display
LC868100 series
: 1024 dots Maximum
External segment driver : Enable to extend of LCD drive
- LCD contrast
LCD display contrast programmable
- LCD display power supply
Doubler circuit available within VDD≤3V.
* Doubler generates up to 6V.
- LCD driver
Following two kinds of combination can be selected by mask option
No.
Segment output port
Common output port
1
48
16
2
32
32
* Up to 32 commons can be specified by mask option. As maximum LCD display voltage is 6V, please select
the preferable LCD panel and the display condition with this range.
* In general, the LCD driver cannot be expanded.
(7) Serial-interface
- Two 8-bit serial-interface circuits
LSB first / MSB first function available
- Internal 8-bit baud-rate generator in common with two serial-interface circuits
(8) Timers
- Timer0 (T0L, T0H)
16-bit timer / counter
2-bit prescaler + 8-bit programmable prescaler
Mode 0 : Two 8-bit timers with programmable prescaler
Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with a programmable prescaler
Mode 3 : 16-bit counter
- Timer1 (T1L, T1H)
16-bit timer / PWM
Mode 0 : Two 8-bit timers
Mode 1 : 8-bit timer + 8-bit PWM
Mode 2 : 16-bit timer
Mode 3 : Variable-bit PWM (9-16 bits)
- Base timer
Every 500ms overflow system for a clock application (using 32.768kHz crystal oscillation for Base timer clock)
The Base timer clock selectable ; 32.768kHz crystal oscillation, System clock, and programmable prescaler output of
Timer 0
(9) Buzzer output
- The Buzzer sound frequency selectable ; 4KHz, 2KHz
(10) Remote control receiver circuit (using P73/INT3/T0IN terminal)
- Noise rejection available
- The interrupt polarity selectable
No.6724-4/28
LC868116/12/08A
(11) Watchdog timer
- The watchdog timer is taken on RC outside. (using P70/INT0 terminal)
- Watchdog timer operation selectable : interrupt system, system reset
(12) Interrupts system
- 13-source 9-level vectored interrupts :
1. External interrupt INT0 (includes watchdog timer)
2. External interrupt INT1
3. External interrupt INT2, timer / counter T0L (timer 0 lower 8 bits)
4. External interrupt INT3, base timer
5. Timer / counter T0H (timer 0 upper 8-bit)
6. Timer T1L (timer 1 lower 8-bit), Timer T1H (timer 1 upper 8-bit)
7. Serial interface SIO0
8. Serial interface SIO1
9. Port 0 or Port 3
- Interrupt priority control available
Microcomputer allows 3 levels of interrupt; low level, high level and highest level of multiplex interrupt. It can specify
a low level or a high level interrupt priority from INT2/T0L through port 0 or port 3 (the above interrupt number from
three through nine). It can also specify a low level or the highest level interrupt priority to INT0 and INT1.
(13) Sub-routine stack levels
- 128 levels (Max.) : stack area included in RAM area
(14) Multiplication and division
- 16 bits × 8-bit (7 instruction cycle times)
- 16 bits / 8-bit (7 instruction cycle times)
(15) Three oscillation circuits
- On-chip RC oscillation circuit using for the system clock, for the LCD display and for the step-up circuit.
- On-chip CF oscillation circuit using for the system clock, for the LCD display and for the step-up circuit.
- On-chip crystal oscillation circuit using for the system clock, for time-base clock and for the LCD display.
(16) Standby function
- HALT mode function
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped.
This operation mode can be released by the interrupt request signals or setting to low level for the reset terminal
( RES ).
- HOLD mode function
The HOLD mode is used to freeze all the oscillations ;
RC (internal), CF and Crystal oscillations. This mode can be released by the following operations:
• Reset terminal ( RES ) set to low level.
• Set to assigned level to INT0/1 terminals.
• Set to assigned level to Port 0/3.
(17) Factory shipment
- Chip
QIC160 package shipping available for sample evaluation.
(18) Development support tools
- Evaluation (EVA) chip
- Emulator
: LC868099
: EVA86000 + ECB868000 (Evaluation chip board)
No.6724-5/28
LC868116/12/08A
Pin Assignment
VDD
P30
P31
P32
P33
P34
P35
P36
P37
P00
P01
P02
P03
P04
P05
P06
P07
P20
P21
P22
P23
P24
P25
P26
P27
ADLC
EROE
RES
XT1
XT2
VSS
CF1
4.98mm × 6.26mm
106µm × 106µm
90µm × 90µm
480µm±20µm
:
:
:
:
CF2
Chip size
Pad size
Bonding area size
Chip thickness
VDD
P50
S1
P51
S2
P52
S3
P53
S4
P54
S5
P55
S6
P56
S7
P57
S8
P17
S9
P16
S10
P15
S11
P14
S12
P13
S13
P12
S14
P11
S15
P10
S16
P73
S17
P72
S18
(0, 0)
P71
S19
P70
S20
P47
S21
P46
S22
P44
S23
P43
S24
P42
S25
P41
S26
P40
S27
VSS
S28
S29
V4
V3
V2
V1
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
S48
S47
S46
S45
S44
S43
S42
S41
S40
V5
S39
VLCD
S34
S38
VOUT2
S33
S37
CUP2
S32
S36
CUP1
S31
S35
S30
No.6724-6/28
LC868116/12/08A
Pad Name and coordinates table
Coordinates
Coordinates
Coordinates
Pad
Pad
Pad
Name
Name
Name
No.
No.
No.
Xµm
Yµm
Xµm
Yµm
Xµm
Yµm
1
VDD
-2240 2236
47
S46
-700 -2875
93
P16
2240
960
2
S1
-2240 2100
48
S47
-565 -2875
94
P17
2240
1096
3
S2
-2240 1965
49
S48
-429 -2875
95
P57
2240
1231
4
S3
-2240 1829
50
C16
-293 -2875
96
P56
2240
1367
5
S4
-2240 1694
51
C15
-158 -2875
97
P55
2240
1502
6
S5
-2240 1558
52
C14
-22
-2875
98
P54
2240
1638
7
S6
-2240 1422
53
C13
113
-2875
99
P53
2240
1774
8
S7
-2240 1287
54
C12
249
-2875
100
P52
2240
1909
9
S8
-2240 1151
55
C11
385
-2875
101
P51
2240
2045
10
S9
-2240 1016
56
C10
520
-2875
102
P50
2240
2180
11
S10
-2240
880
57
C9
656
-2875
103
VDD
2123
2875
12
S11
-2240
744
58
C8
791
-2875
104
P30
1987
2875
13
S12
-2240
609
59
C7
927
-2875
105
P31
1852
2875
14
S13
-2240
473
60
C6
1063 -2875
106
P32
1716
2875
15
S14
-2240
338
61
C5
1198 -2875
107
P33
1581
2875
16
S15
-2240
202
62
C4
1334 -2875
108
P34
1445
2875
17
S16
-2240
66
63
C3
1469 -2875
109
P35
1309
2875
18
S17
-2240
-69
64
C2
1605 -2875
110
P36
1174
2875
19
S18
-2240 -205
65
C1
1741 -2875
111
P37
1038
2875
20
S19
-2240 -340
66
V1
1876 -2875
112
P00
903
2875
21
S20
-2240 -476
67
V2
2012 -2875
113
P01
767
2875
22
S21
-2240 -612
68
V3
2147 -2875
114
P02
631
2875
23
S22
-2240 -747
69
V4
2283 -2875
115
P03
496
2875
24
S23
-2240 -883
70
V5
2240 -2479
116
P04
360
2875
25
S24
-2240 -1018
71
VLCD
2240 -2344
117
P05
225
2875
26
S25
-2240 -1154
72
VOUT2 2240 -2208
118
P06
89
2875
27
S26
-2240 -1290
73
CUP2
2240 -2072
119
P07
-47
2875
28
S27
-2240 -1425
74
CUP1
2240 -1937
120
P20
-182
2875
29
S28
-2240 -1561
75
VSS
2240 -1481
121
P21
-318
2875
30
S29
-2240 -1696
76
P40
2240 -1345
122
P22
-453
2875
31
S30
-2240 -1832
77
P41
2240 -1210
123
P23
-589
2875
32
S31
-2240 -1968
78
P42
2240 -1074
124
P24
-725
2875
33
S32
-2240 -2103
79
P43
2240
-938
125
P25
-860
2875
34
S33
-2240 -2239
80
P44
2240
-803
126
P26
-996
2875
35
S34
-2240 -2374
81
P46
2240
-667
127
P27
-1131 2875
36
S35
-2192 -2875
82
P47
2240
-532
128
ADLC -1267 2875
37
S36
-2056 -2875
83
P70
2240
-396
129
-1403 2875
EROE
38
S37
-1921 -2875
84
P71
2240
-260
130
-1538 2875
RES
39
S38
-1785 -2875
85
P72
2240
-125
131
XT1
-1674 2875
40
S39
-1649 -2875
86
P73
2240
11
132
XT2
-1809 2875
41
S40
-1514 -2875
87
P10
2240
146
133
VSS
-1945 2875
42
S41
-1378 -2875
88
P11
2240
282
134
CF1
-2081 2875
43
S42
-1243 -2875
89
P12
2240
418
135
CF2
-2216 2875
44
S43
-1107 -2875
90
P13
2240
553
45
S44
-971 -2875
91
P14
2240
689
46
S45
-836 -2875
92
P15
2240
824
The values (X, Y) indicate the coordinates of each pad center with the center of the chip as the origin.
Connect the substrate of chip to VSS or open.
No.6724-7/28
LC868116/12/08A
System Block Diagram
Interrupt Control
IR
CF
RC
X'tal
Base Timer
ROM
Clock
Generator
Standby Control
PLA
PC
Bus Interface
ACC
SIO0
Port 1
B Register
SIO1
Port 7
C Register
Timer 0
ALU
Timer 1
Port 2
Port 3
PSW
INT0-3
Noise Rejection Filter
Port 4
RAR
XRAM
128 Bytes
Port 5
RAM
Stack Pointer
CGROM
Port 0
LCD Display
Controller
EXT Register
Watchdog Timer
LCD Driver
No.6724-8/28
LC868116/12/08A
Pin Description
Name
VSS
VDD
VLCD
V1 to V5
VOUT2
CUP1,2
Port0
No.
75,133
1,103
71
66-70
72
74,73
P00 to P07
112-119
Port1
P10 to P17
87-94
Port2
P20 to P27
120-127
Port3
P30 to P37
104-111
I/O
I/O
I/O
I/O
I/O
Function description
Power terminal (-)
Power terminal (+)
Power terminal (+) for LCD driver *2
Voltage supply terminals to LCD drivers *2
Output terminals for doubler VOUT2 ≅ 2X(VDD-VSS)
Capacitor connecting terminals for doubler, tripler
•8-bit input/output port
•Input/output can be specified in 4-bit
•External memory mode
1. EXT resistor bit 2=0
Address output of lower 8-bit, input/output
of data
2. EXT resistor bit 2=1
•Input/output of data
•Input for key interrupt (P30INT=0) *1
•8-bit input/output port
•Input/output can be specified in a bit
•Another functions
P10 SIO0 data output
P11 SIO0 data input, bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input, bus input/output
P15 SIO1 clock input/output
P16 Buzzer output
P17 Timer 1 output (PWM output)
Option
•Pull-up resistor :
Provided/Not provided
•Output form :
CMOS/N-ch open drain
•8-bit input/output port
•Input/output can be specified in a bit
•External memory mode
Address output of upper 8-bit
•8-bit input/output port
•Input/output in a bit
•External memory mode
1. EXT resistor bit 2=0 : input/output port
2. EXT resistor bit 2=1 : address output of lower
8-bit for external memory
•Input for key interrupt (P30INT=L) *1
•Output form :
CMOS/N-ch open drain
•Output form :
CMOS/N-ch open drain
•Pull-up resistor :
Provided/Not provided
•Output form :
CMOS/N-ch open drain
*1 P30INT : Bit 0 of Port 3 interrupt control register.
*2 The structure of the LCD power supply is shown below.
VLCD
Resistor for
LCD contrast
adjustment
V5
V4
V3
Note : If the microcontroller is operated at 3V, the voltage doubler
output (VOUT2) should be connected to the LCD power
terminal (VLCD).
(or the output of an external voltage doubler should be
connected to VLCD)
V2
V1
VSS
No.6724-9/28
LC868116/12/08A
Name
Port4
P40 to P44
P46, P47
No.
76-80
81,82
Port5
P50 to P57
102-95
I/O
Port7
P70 to P73
I/O
I/O
I
83-86
Function description
•7-bit input/output port
•Input/output can be specified each upper
2 bits and lower 5 bits
•Another functions
P40 CL1 Latch clock
P41 CL2 Shift clock
P42 DO
Output data
P43 M
Alternate signal
P44 FRM Frame signal
P46
RD
Read signal
P47
WR
Write signal
(P40-P44 : LCD display extend signal,
P46, P47 : External RAM access signal)
•8-bit input/output port
•Input/output in bit unit
•External memory mode
1. EXT resistor bit 3=0 : input/output
2. EXT resistor bit 3=1 : bank address output for
external memory
•4-bit input port
•Another functions
P70 INT0 input/HOLD release/N-ch Tr.
output for watchdog timer
P71 INT1 input/HOLD release
P72 INT2 input/timer 0 event input
P73 INT3 input with noise filter/timer 0
event input
•Interrupt received form, vector address
leading trailing leading
high
low
&
level
level
trailing
INT0
enable enable disable enable enable
INT1
enable enable disable enable enable
INT2
enable enable enable disable disable
INT3
enable enable enable disable disable
Option
•Pull-up resistor :
Provided/Not provided
•Output form :
CMOS/N-ch open drain
•Pull-up resistor :
Provided/Not provided
•Output form :
CMOS/N-ch open drain
•Pull-up resistor :
Provided/Not provided
vector
03H
0BH
13H
1BH
No.6724-10/28
LC868116/12/08A
Name
C1 to C16
S1 to S48
No.
65-50
2-49
I/O
O
O
130
128
129
131
I
O
O
I
Function description
LCD output terminals for common
LCD output terminals for segment
Reset
Address control signal for external memory
Enable signal of external ROM output
EROE
XT1
Input for 32.768kHz crystal oscillation
In case of non use, connect to VDD
XT2
132
O
Output for 32.768kHz crystal oscillation
In case of non use, should be left unconnected
CF1
134
I
Input for ceramic resonator oscillation
In case of non use, connect to VDD
CF2
135
O
Output for ceramic resonator oscillation
In case of non use, should be left unconnected
* Port options can be specified in a bit.
RES
ADLC
* A state of port at initial
Pin name
Input/output mode
Port 0, 7
Input
Ports 1, 2
Input
Ports 3, 5
Port 4
Input
Name
C1 to C16
S1 to S48
Option
LCD output terminals :
segment/common
-
A state of pull-up resistor specified at pull-up option
Fixed pull-up resistor exist
Programmable pull-up resistor OFF
Programmable pull-up resistor ON
Output level
VSS (Display OFF)
VSS (Display OFF)
No.6724-11/28
LC868116/12/08A
1. Absolute Maximum Ratings at VSS=0V and Ta=25°C
Parameter
Symbol
Supply voltage
Input voltage
VDDMAX
VI(1)
Output voltage
VI(2)
VO(1)
VO(2)
Input/output
voltage
High
Peak
level
output
output current
current Total
output
current
Low
level
output
current
Peak
output
current
Total
output
current
Operating
temperature
range
Storage
temperature
range
VO(3)
VIO(1)
IOPH(1)
ΣIOAH(1)
ΣIOAH(2)
IOPL(1)
IOPL(2)
ΣIOAL(1)
ΣIOAL(2)
ΣIOAL(3)
ΣIOAL(4)
ΣIOAL(5)
ΣIOAL(6)
ΣIOAL(7)
Topr
Tstg
Pins
VDD
•Ports 71,72,73
• RES
VLCD
•C1 to C16
•S1 to S48
•VOUT2
•CUP1,CUP2
ADLC, EROE
•Ports 0,1,2,3,4,5
•Port 70
•Ports 0,1,2,3,4,5
•ADLC, EROE
•Ports 0,2,3
•C1-C16,S1-S48
•ADLC, EROE
Ports 1, 4, 5
•Ports 0,1,2,3,4,5
•ADLC, EROE
Port 70
Port 0
•Port 2
•ADLC, EROE
Port 3
Ports 1, 5
Port 4
Port 70
C1-C16,S1-S48
Conditions
VDD[V]
min.
-0.3
-0.3
Ratings
typ.
max.
+7.0
VDD+0.3
-0.3
-0.3
+7.0
VLCD+0.3
-0.3
VDD+0.3
-0.3
-0.3
VDD+0.3
VDD+0.3
•CMOS output
•At each pin
-4
Total all pins
-25
Total all pins
At each pin
-25
unit
V
mA
20
At each pin
Total all pins
Total all pins
15
40
40
Total all pins
Total all pins
Total all pins
Total all pins
Total all pins
-30
40
40
40
15
30
+70
-65
+150
°C
Notes :
The specifications above are for a die mounted in a QIC160 type package.
However, we ship this product as a die only, not a package chip.
Therefore, the operational characteristics may vary depending on the user’s packaging techniques.
No.6724-12/28
LC868116/12/08A
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS=0V
Parameter
Operating
supply voltage
range
Symbol
VDD(1)
Pins
VDD(3)
Hold voltage
VHD
VDD
LCD display
voltage
Input high
voltage
VLCD
VLCD
VIH(1)
Port 0
VIH(2)
•Ports 1,2,3,4,5
•Ports 72,73
(Schmitt)
•Port 70 for
Port input/interrupt
•Port 71
• RES (Schmitt)
Port 70 for watchdog
timer
Port 0 (Schmitt)
•Ports 1,2,4,5
•Ports 72,73
(Schmitt)
•Port 70
Port input/interrupt
•Port 71
• RES
Port 70 for watchdog
timer
VIH(4)
Input low
voltage
VIL(1)
VIL(2)
VIL(3)
VIL(4)
Operation
cycle time
VDD[V]
0.98µs ≤ tCYC ≤
400µs
1.9µs ≤ tCYC ≤
400µs
3.9µs ≤ tCYC ≤
400µs
RAMs and the
registers hold
voltage at HOLD
mode.
VDD
VDD(2)
VIH(3)
Conditions
(Schmitt)
tCYC
Oscillation
FmCF(1)
frequency
range
(Note 1)
FmCF(2)
CF1, CF2
CF1, CF2
FmCF(3)
CF1, CF2
FmRC
FsXtal
XT1, XT2
min.
4.5
Ratings
typ.
max.
6.0
4.5
6.0
2.5
6.0
2.0
6.0
6.0
6.0
VDD
VDD
Output disable
2.5-3.0
3.0-6.0
2.5-6.0
Output disable
2.5-6.0
VDD
VDD
0.4VDD
+0.9
0.75VDD
Output N-channel
Tr. OFF
2.5-6.0
0.75VDD
VDD
Output N-channel
Tr. OFF
Output disable
Output disable
2.5-6.0
0.9VDD
VDD
2.5-6.0
2.5-6.0
VSS
VSS
0.2VDD
0.25VDD
Output N-channel
Tr. OFF
2.5-6.0
VSS
0.25VDD
Output N-channel
Tr. OFF
excluding external
memory access
function
for external
memory access
•12MHz
(ceramic resonator
oscillation)
•Refer to figure 1
•6MHz
(ceramic resonator
oscillation)
•Refer to figure 1
•3MHz
(ceramic resonator
oscillation)
•Refer to figure 1
RC oscillation
•32.768kHz
(crystal oscillation)
•Refer to figure 2
Continue.
2.5-6.0
VSS
4.5-6.0
2.5-6.0
0.98
3.9
0.8VDD
-1.0
400
400
4.5-6.0
2.5-6.0
4.5-6.0
1.9
3.9
11.76
12
400
400
12.24
4.5-6.0
5.88
6
6.12
2.5-6.0
2.94
3
3.06
2.5-6.0
2.5-6.0
0.4
0.8
32.768
2.0
unit
V
µs
MHz
kHz
No.6724-13/28
LC868116/12/08A
Parameter
Oscillation
stabilizing
time period
(Note 1)
Symbol
Pins
tmsCF(1)
CF1, CF2
tmsCF(2)
CF1, CF2
tmsCF(3)
CF1, CF2
tssXtal
XT1, XT2
Conditions
•12MHz
(ceramic resonator
oscillation)
•Refer to figure 3
•6MHz
(ceramic resonator
oscillation)
•Refer to figure 3
•3MHz
(ceramic resonator
oscillation)
•Refer to figure 3
•32.768kHz
(crystal oscillation)
•Refer to figure 3
Ratings
typ.
0.02
max.
0.3
4.5-6.0
0.02
0.3
4.5-6.0
2.5-6.0
0.1
0.1
1
3
4.5-6.0
2.5-6.0
1
1
1.5
3
VDD[V]
4.5-6.0
min.
unit
ms
s
(Note 1) The oscillation constant is shown on table 1 and table 2.
No.6724-14/28
LC868116/12/08A
3. Electrical Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter
Input high
current
Input low
current
Symbol
IIH(1)
•Ports 1,2,3,4,5
•Port 0 without
pull-up MOS Tr.
IIH(2)
Port 7 without
pull-up MOS Tr.
IIH(3)
IIL(1)
IIL(2)
Output high
voltage
Output low
voltage
Pull-up MOS
Tr. resistor
Hysteresis
voltage
Pin capacitance
Pins
IIL(3)
VOH(1)
VOH(2)
VOH(3)
VOH(4)
VOL(1)
VOL(2)
VOL(3)
VOL(4)
VOL(5)
Rpu
VHIS
CP
RES
•Ports 1,2,3,4,5
•Port 0 without
pull-up MOS Tr.
Port 7 without
pull-up MOS Tr.
RES
Port 0 of
CMOS output
•Ports 1,2,3,4,5 of
CMOS output
•ADLC, EROE
•Ports 0,1,2,3,4,5
•ADLC, EROE
Port 70
•Ports 0,1,2,3,4,5
•Port 7
•Ports 0,1,2,3,4,5
•Port 7
• RES
All pins
Conditions
•Output disable
•Pull-up MOS Tr. OFF
•VIN=VDD
(including the offleak current of the
output Tr.)
•Output Nch Tr. OFF
•VIN=VDD
(including the offleak current of the
output Tr.)
VIN=VDD
•Output disable
•Pull-up MOS Tr. OFF
•VIN=VSS
(including the offleak current of the
output Tr.)
•Output Nch Tr. OFF
•VIN=VSS
(including the offleak current of the
output Tr.)
VIN=VSS
IOH=-10mA
IOH=-1mA
IOH=-1.0mA
IOH=-0.1mA
IOL=10mA
IOL=1.6mA
•IOL=1.0mA
•The current of any
measurement pin is
not over 1mA.
IOL=1mA
IOL=0.5mA
VOH=0.9VDD
Output disable
•f=1MHz
•Unmeasurement
terminals for the
input are set to
VSS level.
•Ta=25°C
VDD[V]
2.5-6.0
min.
Ratings
typ.
2.5-6.0
max.
1
µA
1
2.5-6.0
2.5-6.0
-1
2.5-6.0
-1
2.5-6.0
4.5-6.0
2.5-6.0
4.5-6.0
2.5-6.0
-1
VDD-2.2
VDD-0.4
VDD-1
VDD-0.5
1
V
4.5-6.0
4.5-6.0
2.5-6.0
1.5
0.4
0.4
4.5-6.0
2.5-6.0
4.5-6.0
2.5-4.5
2.5-6.0
0.4
0.4
70
120
2.5-6.0
unit
15
25
40
60
0.1VDD
10
kΩ
V
pF
No.6724-15/28
LC868116/12/08A
Serial output
Parameter
Symbol
Cycle
Low Level
pulse width
High Level
pulse width
Cycle
Low Level
pulse width
High Level
pulse width
Data set up time
Input clock
tCKCY(1)
tCKL(1)
Output clock
Serial input
Serial clock
4. Serial Input/Output Characteristics at Ta=-30°C to +70°C, VSS=0V
tCKCY(2)
tCKL(2)
Data hold time
tCKI
Output delay time
(Serial clock is
external clock)
tCKO(1)
Output delay time
(Serial clock is
internal clock)
Pins
SCK0,
SCK1
Conditions
Refer to figure 5.
VDD[V]
2.5-6.0
tCKH(1)
tCKO(2)
Ratings
typ.
max.
unit
tCYC
1
SCK0,
SCK1
tCKH(2)
tICK
min.
2
1
•SI0,SI1
•SB0,SB1
•SO0,SO1
•SB0,SB1
•SO0,SO1
•SB0,SB1
•Use pull-up
resistor (1kΩ)
when Nch opendrain output.
•Refer to figure 5.
•Data set-up to
SCK0,1
•Data hold from
SCK0,1
•Refer to figure 5.
•Data set-up to
SCK0,1
•Use pull-up
resistor (1kΩ)
when Nch opendrain output.
•Refer to figure 5.
•Data hold from
SCK0,1
•Use pull-up
resistor (1kΩ)
when Nch opendrain output.
•Refer to figure 5.
2.5-6.0
2
1/2
tCKCY
1/2
tCKCY
4.5-6.0
2.5-6.0
4.5-6.0
2.5-6.0
4.5-6.0
2.5-6.0
4.5-6.0
2.5-6.0
µs
0.1
0.4
0.1
0.4
7/12
tCYC
+0.2
7/12
tCYC
+1
1/3
tCYC
+0.2
1/3
tCYC
+1
No.6724-16/28
LC868116/12/08A
5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS=0V
Parameter
High/low level
pulse width
Symbol
tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
tPIL(5)
Pins
•INT0, INT1
•INT2/T0IN
•Refer to figure 6
•INT3/T0IN
(The noise rejection
clock is selected to
1/1.)
•Refer to figure 6
•INT3/T0IN
(The noise rejection
clock is selected to
1/16.)
•Refer to figure 6
•INT3/T0IN
(The noise rejection
clock is selected to
1/64.)
•Refer to figure 6
• RES
•Refer to figure 6
Conditions
VDD[V]
2.5-6.0
min.
1
•Interrupt acceptable
•Timer0-countable
2.5-6.0
2
•Interrupt acceptable
•Timer0-countable
2.5-6.0
32
•Interrupt acceptable
•Timer0-countable
2.5-6.0
128
Reset acceptable
2.5-6.0
200
•Interrupt acceptable
•Timer0-countable
Ratings
typ.
max.
unit
tCYC
µs
No.6724-17/28
LC868116/12/08A
6. Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter
Current
drain
during basic
operation
(Note 2)
Symbol
Pins
IDDOP(1)
VDD
IDDOP(2)
IDDOP(3)
IDDOP(4)
IDDOP(5)
Conditions
•FmCF=12MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
12MHz
•Internal RC
oscillation stops
•FmCF=6MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
6MHz
•Internal RC
oscillation stops
•FmCF=3MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
3MHz
•Internal RC
oscillation stops
OCR7 VDD[V] min.
0
4.5-6.0
Ratings
typ.
max.
10
25
1
4.5-6.0
10
25
0
1
0
4.5-6.0
3
6
1.5
9
15
5
0.7
1.2
0.4
0.8
3.4
4.5
2.8
3.6
38
60
15
25
150
300
70
120
IDDOP(6)
IDDOP(7)
IDDOP(8)
IDDOP(9)
•FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
0
1
0
1
IDDOP(10)
IDDOP(11)
IDDOP(12)
IDDOP(13)
•FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
32.768kHz
•Internal RC
oscillation stops
0
1
0
1
2.5-4.5
4.5-6.0
2.5-4.5
4.5-6.0
2.5-4.5
unit
mA
µA
*OSCR : Bit 7 of the oscillation control register.
Continue.
No.6724-18/28
LC868116/12/08A
Parameter
Symbol
Current
IDDHALT(1)
drain in
HALT mode
(Note 2)
IDDHALT(2)
IDDHALT(3)
IDDHALT(4)
IDDHALT(5)
IDDHALT(6)
IDDHALT(7)
IDDHALT(8)
IDDHALT(9)
IDDHALT(10)
IDDHALT(11)
IDDHALT(12)
IDDHALT(13)
Pins
VDD
Conditions
•HALT mode
•FmCF=12MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
12MHz
•Internal RC
oscillation stops
•HALT mode
•FmCF=6MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
6MHz
•Internal RC
oscillation stops
•HALT mode
•FmCF=3MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
3MHz
•Internal RC
oscillation stops
•HALT mode
•FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•HALT mode
•FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
32.768kHz
•Internal RC
oscillation stops
HOLD mode
OCR7 VDD[V] min.
0
4.5-6.0
Ratings
typ.
max.
5.0
14
1
4.5-6.0
5.0
14
0
1
0
4.5-6.0
2.3
4.5
0.8
7
15
4
0
1
0
1
4.5-6.0
400
600
200
350
1600
2400
1300
1500
0
1
0
1
4.5-6.0
25
36
8
12
100
140
55
85
2.5-4.5
2.5-4.5
2.5-4.5
Current
IDDHOLD(1) VDD
4.5-6.0
0.05
drain in
IDDHOLD(2)
2.5-4.5
0.02
HOLD mode
(Note 2)
(Note 2) The currents of the output transistors, pull-up transistors and the LCD bleeder resistors are ignored.
Refer to figure 7.
unit
mA
µA
30
20
No.6724-19/28
LC868116/12/08A
7. LCD Voltage and LCD Driver Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter
Symbol
VX-Ci drop
voltage (X : 1 to 5)
(i : 1 to 16)
|VD1|
VX-Ci drop
voltage (X : 1 to 5)
(i : 1 to 16)
|VD2|
VX-Si drop
voltage (X : 1 to 5)
(i : 1 to 48)
|VD3|
VX-Si drop
voltage (i : 1 to 5)
(i : 1 to 48)
|VD4|
V4 output voltage
VV4
V3 output voltage
VV3
V2 output voltage
VV2
V1 output voltage
VV1
LCD display
current
ILCD1
Step-up output
voltage
Contrast current
(VLCD terminal)
Pins, Conditions
VDD[V]
2.9
•Only a Ci terminal for –15µA
•LCD display ON
•1/5 bias
•V5=VDD
•Only a Ci terminal for +15µA
•LCD display ON
•1/5 bias
•V5=VDD
•Only a Si terminal for -15µA
•LCD display ON
•1/5 bias
•V5=VDD
•Only a Si terminal for +15µA
•LCD display ON
•1/5 bias
•V5=VDD
•LCD clock frequency=0Hz
•LCD display ON
•1/5 bias
•V5=VDD
•Refer to figure 9
•LCD display ON
•1/5 bias
ILCD2 •VLCD=VDD
•V1-V5 are opened
•Refer to figure 8
VOUT2 •V1-V5 resistor=20kΩ
•LCD display ON
•LVCR0=1 (doubler)
•VOUT2
•VDD=2.5 to 3.0V
•C5=C6=0.1µF
•Refer to figure 10
ILC1
•LCD display ON
•V5=VDD-0.5V
ILC2
•VLCD=VDD
ILC3
•Refer to figure 11
ILC4
ILC5
VCCR : The LCD contrast control register
LVCR0 : Bit 0 of the LCD bias control register
min.
Ratings
typ.
5.0
20kΩ
mode
4KΩ
mode
•IL=100µA
•step-up clock
: RC oscillation
•IL=500µA
•step-up clock
: RC oscillation
•IL=100µA
•step-up clock
: crystal
oscillation
•IL=500µA
•step-up clock
: crystal
oscillation
VCCR=1
VCCR=2
VCCR=4
VCCR=8
VCCR=10H
max.
120
mV
200
2.9
-120
5.0
-200
2.9
120
5.0
200
2.9
-120
5.0
-200
2.9
5.0
2.9
5.0
2.9
5.0
2.9
5.0
5
2.9
5
2.9
unit
0.75VDD 0.80VDD 0.85VDD
V
0.55VDD 0.60VDD 0.65VDD
0.35VDD 0.40VDD 0.45VDD
0.15VDD 0.20VDD 0.25VDD
25
15
125
75
50
29
250
150
100
60
500
300
µA
2.7
3
4.4
5.6
4.6
5.8
5.4
6.0
V
2.7
3
4.2
5.2
4.5
5.6
5.4
6.0
2.7
3
4.3
5.4
4.5
5.7
5.4
6.0
2.7
3
4.0
5.0
4.3
5.4
5.4
6.0
5
5
5
5
5
0.8
0.4
0.2
0.1
0.05
1.6
0.8
0.4
0.2
0.1
3.2
1.6
0.8
0.4
0.2
mA
µA
No.6724-20/28
LC868116/12/08A
Table 1. Ceramic resonator oscillation recommended constant (main clock)
Oscillation type
Maker
Oscillator
C1
C2
12MHz ceramic resonator
Murata
CSA12.0MT
33pF
33pF
oscillation
CST12.00MTW
on chip
Kyocera
KBR-12.0M
33pF
33pF
6MHz ceramic resonator
Murata
oscillation
on chip
Kyocera
on chip
3MHz ceramic resonator
Murata
CSA3.0MG
33pF
33pF
oscillation
CST3.0MGW
on chip
Kyocera
KBR-3.0MS
47pF
47pF
* Both C1 and C2 must use K rank (±10%) and SL characteristics.
Table 2. Crystal oscillation guaranteed constant (sub clock)
Oscillation type
Maker
Oscillator
C3
C4
32.768kHz crystal
CITIZEN
CFS-308
18pF
18pF
oscillation
SII
DT-VT-200
18pF
18pF
* Both C3 and C4 must use J rank (±5%) and CH characteristics.
(It is about the application which is not in need of high precision. Use K rank (±10%) and SL characteristics.)
(Notes)
•Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close
to the oscillation pins as possible with the shortest possible pattern length.
•If you use other oscillators herein, we provide no guarantee for the characteristics.
CF1
CF2
XT1
XT2
X’tal
CF
C1
Figure 1
C2
Ceramic oscillation circuit
C3
C4
Figure 2
Crystal oscillation circuit
No.6724-21/28
LC868116/12/08A
VDD
VDD limit
0V
Power supply
Reset time
RES
Internal RC oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
Unstable
Reset
Execution of instructions
Reset time and oscillation stable time
HOLD release signal
Valid
Internal RC oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
HOLD
Execution of instructions
HOLD release signal and oscillation stable time
Figure 3
Oscillation stable time
No.6724-22/28
LC868116/12/08A
VDD
RRES
RES
(Note) Fix the value of CRES, RRES that is
sure to reset until 200µs, after Power
supply has been over inferior limit of
supply voltage.
CRES
Figure 4
Reset circuit
0.5VDD
<AC Timing Point>
VDD
tCKCY
tCKL
tCKH
SCK0
SCK1
1KΩ
tICK
tCKI
SI0
SI1
tCKO
50pF
SO0, SO1
SB0, SB1
<Timing>
Figure 5
tPIL
Figure 6
<Test Load>
Serial input / output test condition
tPIH
Pulse input timing condition
No.6724-23/28
LC868116/12/08A
VDD
VDD
A
VDD
VDD
CUP1
OPEN
V5
V5
CUP2
CUP1
OPEN
CUP2
OPEN
VOUT2
V1
VOUT2
V1
VLCD
CF1
CF2
VSS
XT1
VLCD
XT2
CF1
CF2
VSS
XT1
XT2
A
VDD
VSS
Figure 7
VSS
Current dissipation measurement
Figure 8
VDD
LCD display current measurement
VDD
VDD
VDD
CUP1
IL
V5
VOUT2
V4
CUP2
OPEN
VDD
V5
CUP2
V1
V1
CF1
CF2
VSS
XT1
VLCD
XT2
CF1
V
CF2
VSS
XT1
XT2
V
VSS
Figure 9
OPEN
CUP1
VOUT2
VLCD
VSS
Output voltage of V1-V4 measurement
Figure 10
Step up output voltage measurement
VDD
A
VDD
VLCD
CUP1
OPEN
V5
CUP2
VDD-0.5V
V4
VOUT2
OPEN
V1
CF1
CF2
VSS
XT1
XT2
VSS
Figure 11
Contrast current measurement
No.6724-24/28
LC868116/12/08A
8. AC Characteristics at Ta=-30°C to +70°C, VSS=0V
Load capacity : 100pF
(Port 0, ADLC, EROE )
Load capacity : 80pF
(Output terminals except above)
*tCLCL=1/12 tCYC
External program memory timing
Parameter
Symbol
Pads and Conditions
ADLC pulse width
tLHLL
Address settling time
tAVLL
For ADLC
Address hold time
tLLAX
For ADLC
ADLC ! control signal
tLLEL
For EROE
EROE pulse width
tELEH
Data delay time
tELIV
From EROE
Data hold time
tEHIX
For EROE
EROE ! address in
tEHAV
VDD[V]
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
Ratings
min.
max.
2tCLCL-40
2tCLCL-160
tCLCL-40
tCLCL-160
tCLCL-35
tCLCL-140
tCLCL-25
tCLCL-100
3tCLCL-35
3tCLCL-140
3tCLCL-125
3tCLCL-400
0
0
tCLCL-8
tCLCL-32
unit
ns
Refer to figure 12.
tCLCL
1 tCYC
SCLK
tLHLL
ADLC
tLLEL
tELEH
EROE
tELIV
tEHAV
tLLAX
tAVLL
Port 0
tEHIX
A7-A0
IR
A7-A0
Port 2
A15-A8
A15-A8
Port 3
A7-A0
A7-A0
EROE
Port 0
Figure 12
A7-A0
DATA
Port 2
A15-A8
Port 3
A7-A0
Port 5
Bank
Timing of the external Program Memory/Data Memory
No.6724-25/28
LC868116/12/08A
External data memory timing
Parameter
Symbol
RD pulse width
tRLRH
WR pulse width
tWLWH
Data address hold time
tLLAX
Pads and Conditions
For ADLC (at LDX)
For ADLC (at STX)
Data delay time
tRLDV
From RD
Data hold time
tRHDX
From RD
Data floating time
tRHDZ
From RD
Data address setting
time
ADLC ! control signal
tAVLL
For ADLC
tLLRL
For RD
tLLWL
For WR
Data settling time
tQVWL
For WR
Data in WR =1
tQVWH
Data hold time
tWHQX
From WR
Control signal ! ADLC
tRHLH
For RD
tWHLH
For WR
Ratings
min.
max.
6tCLCL-80
6tCLCL-320
6tCLCL-80
6tCLCL-320
2tCLCL-35
2tCLCL-140
2tCLCL-35
2tCLCL-140
5tCLCL-125
5tCLCL-400
0
0
2tCLCL-70
2tCLCL+70
2tCLCL-280
2tCLCL+280
tCLCL-40
tCLCL-160
3tCLCL-50
3tCLCL+50
3tCLCL-200
3tCLCL+200
3tCLCL-50
3tCLCL+50
3tCLCL-200
3tCLCL+200
tCLCL-60
tCLCL-240
7tCLCL-140
7tCLCL-560
tCLCL-50
tCLCL-200
tCLCL-50
tCLCL+50
tCLCL-200
tCLCL+200
tCLCL-50
tCLCL+50
tCLCL-200
tCLCL+200
VDD[V]
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
unit
ns
Refer to figure 13.
tCLCL
1 tCYC
SCLK
ADLC
EROE
tRLRH
tLLRL
tRHLH
tRLDV
RD
tRHDZ
tAVLL
tLLAX
tRHDX
(at reading)
Port 0
A7-A0
DATA
tLLWL
tWLWH
Z
tWHLH
WR
tLLAX
(at writing)
Port 0
A7-A0
tQVWL
tWHQX
DATA
tQVWH
Port 2
A15-A8
Port 5
Bank
A7-A0
Port 3
Figure 13
Timing of the external RAM
No.6724-26/28
LC868116/12/08A
• Evaluation Sample (ES)
The factory shipment of this microcomputer is chip.
But there are two types of shipment of evaluation sample.
One type is chip and the other is package (QIC160).
If you selected package type, please refer to the following pin assignment and layout, and make the user target board.
85
90
P10
P73
P72
P71
P70
P47
P46
P44
P43
P42
P41
P40
VSS
CUP1
CUP2
VOUT2
P11
100
P15
P14
P13
P12
P16
110
P55
P56
P57
P17
P52
P53
P54
115
P51
P50
• Pin Assignment of evaluation sample (Package type)
VLCD
VSS
V5
V4
V3
V2
V1
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
CF1
CF2
S35
VDD
P30
125
75
P31
P32
P33
P34
P35
P36
P37
P00
P01
P02
P03
P04
P05
P06
P07
P20
P21
P22
P23
P24
P25
P26
P27
130
70
140
LC868116-QIC160
60
150
ADLC
EROM
RES
XT1
XT2
50
155
35
30
20
10
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
1
VDD
45
No.6724-27/28
LC868116/12/08A
• Layout of evaluation sample (Package type) : QIC160
PS No.6724-28/28