Ordering number : EN 4365B CMOS LSI LC5852N Four-Bit Single-Chip Microcontroller with On-Chip LCD Drivers for Small-Scale Control in Medium-Speed Applications Overview Package Dimensions The LC5852N is a high-performance four-bit single-chip built-in LCD driver microprocessor that provides a variety of attractive features including low-voltage operation and low power dissipation. The LC5852N was developed as an upwardly compatible version of the LC5851N and provides a ROM capacity increased from 1024 to 2048 15bit words and a RAM capacity increased from 64 × 4 bits to 128 × 4 bits. unit: mm 3057-QIP64A [LC5852N] Applications • System control and LCD display in cameras, radios and similar products • System control and LCD display in miniature electronic test equipment and consumer health maintenance products • The LC5852N is optimal for end products with LCD displays and, in particular, for battery operated products. SANYO: QIP64A Features The LC5852N is an upwardly compatible version of the LC5851N and, as such, has the following features. • Extremely broad allowable operating ranges Power supply option Cycle time Power supply voltage range Note EXT-V 10 µs VSS2 = –4.0 to –5.5 V When using an 800 kHz ceramic resonator EXT-V 20 µs VSS2 = –4.0 to –5.5 V When using a 400 kHz ceramic resonator EXT-V 61 µs VSS2 = –2.3 to –5.5 V When using a 65 kHz crystal oscillator EXT-V 122 µs, 244 µs VSS2 = –2.0 to –5.5 V When using a 32 kHz crystal oscillator Li 122 µs, 244 µs VSS2 = –2.6 to –3.6 V* When using a 32 kHz crystal oscillator Ag 122 µs, 244 µs VSS1 = –1.3 to –1.65 V When using a 32 kHz crystal oscillator Note: * When the backup flag is set, the BAK pin is shorted to VSS2. (See the user’s manual for details.) • Low current drain — Ceramic oscillator (CF): — Crystal oscillator (Xtal): — Crystal oscillator (Xtal): 400 kHz (5.0 V) 32 kHz (1.5 V, Ag specifications) 32 kHz (3.0 V, Li specifications) HALT mode (typical) 150 µA 2.0 µA (for LCD biases other than 1/3) 3.5 µA (for an LCD bias of 1/3) 1.0 µA (for LCD biases other than 1/3) 5.0 µA (for an LCD bias of 1/3) SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN O3095HA (OT)/91994TH (OT) No. 4365-1/29 LC5852N • Timer functions — One six-bit programmable timer — Time base timer (for clock applications) • Standby functions — Clock standby function (HALT mode) The LC5852N provides a halt function that reduces power dissipation. In halt mode, only the oscillator, divider and LCD driver circuits operate. All other internal operations are stopped. This mode allows the LC5852N to easily implement a low-power clock function. — Full standby function (HOLD mode) — HALT mode is cleared by two external factors and two internal factors. • Improved I/O functions — External interrupt pins — Input pins that can clear HALT mode (up to 9 pins) — Input ports with software controllable input resistors: up to 8 pins — Input ports with built-in floating prevention circuits: up to 8 pins — LCD drivers; common: 4 pins, segment pins: 25 pins — General-purpose I/O ports: 8 pins — General-purpose inputs: 9 pins — General-purpose outputs (1): 6 pins (ALM pin, LIGHT pin) — General-purpose outputs (2): 25 pins (when all 25 LCD segment ports are used as generalpurpose outputs) — Pseudo-serial output port: 1 set (Three pins: output, BUSY, clock) • Powerful hardware to improve processing capabilities — On-chip segment PLA circuit and segment decoder: The LCD driver outputs can handle LCD panel segment display without incurring software overhead. — All LCD driver output pins can be switched to be used as output ports. — One six-bit programmable timer — Part of the RAM area can be used as a working area. — Built-in clock oscillator and 15-stage divider (also used for LCD alternation signal generation) • Highly flexible LCD panel drive output pins (25) Supported Maximum number Required drive types of segments common pins 1/3 bias—1/4 duty......100 segments ..........4 pins 1/3 bias—1/3 duty......75 segments ............3 pins 1/2 bias—1/4 duty......100 segments ..........4 pins 1/2 bias—1/3 duty......75 segments ............3 pins 1/2 bias—1/2 duty......50 segments ............2 pins Static ..........................25 segments ............1 pin — The LCD output pins can be converted to use as general-purpose output pins. CMOS type: 25 pins (maximum) p-channel open drain type: 3 pins (maximum) • An oscillator appropriate for the system specifications can be selected. 32 or 65 kHz crystal oscillator, or 400 or 800 kHz ceramic oscillator Delivery formats QIP-64A or chip product Function Overview Program ROM: 2048 × 15 bits On-chip RAM: 128 × 4 bits All instructions execute in a single cycle HALT mode clear and interrupt functions (External factors) Changes in the S and M port input signals Changes in the INT pin input signal (Internal factors) Overflow from the clock divider circuit Timer underflow • Subroutines can be nested up to four levels (including interrupts) • • • • No. 4365-2/29 LC5852N Pin and Pad Assignment Chip size: 4.19 × 3.66 mm Pad size: 120 × 120 µm Chip thickness: 480 µm (chip specification products) Pin No. Pad No. Symbol 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 VDD BAK VSS1 VSS2 ALM LIGHT S4 S3 I/O A1 I/O A2 I/O A3 I/O A4 I/O B1 I/O B2 I/O B3 I/O B4 RES INT P1 P2 P3 P4 M1 Note: 1. 2. 3. 4. 5. 6. 7. 8. Coordinates Xµm Yµm Pin No. Pad No. Symbol 1899 1899 1899 1899 1899 1899 1899 1899 1899 1595 1415 1235 1055 875 695 515 253 73 –107 –287 –707 –887 –1067 138 358 538 718 898 1078 1258 1438 1630 1630 1630 1630 1630 1630 1630 1630 1630 1630 1630 1630 1630 1630 1630 63 64 1 2 3 4 5 6 7 — 8 — 9 10 — 11 12 13 14 15 16 — — 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 M2 M3 M4 TESTA TEST CUP1 CUP2 S2 S1 (VDD) OSC-IN 10P OSC-OUT COM1 COM4 Seg01 Seg02 Seg03 Seg04 Seg05 Seg06 TEST TEST Coordinates Xµm –1247 –1427 –1899 –1899 –1899 –1899 –1899 –1899 –1899 –1899 –1899 –1899 –1899 –1899 –1899 –1899 –1899 –1899 –1899 –1899 –1899 –1553 –1373 Yµm Pin No. Pad No. Symbol 1630 1630 1630 1450 1270 1090 910 730 550 370 190 10 –169 –349 –529 –709 –889 –1069 –1249 –1429 –1609 –1630 –1630 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 Seg07 Seg08 Seg09 Seg10 Seg11 Seg12 Seg13 COM4 Seg14 Seg15 Seg16 Seg17 Seg18 Seg19 Seg20 Seg21 Seg22 Seg23 Seg24 Seg25 COM3 COM2 VSS3 Coordinates Xµm –1033 –853 –673 –493 –313 –133 46 226 459 639 819 999 1179 1359 1539 1719 1899 1899 1899 1899 1899 1899 1899 Yµm –1630 –1630 –1630 –1630 –1630 –1630 –1630 –1630 –1630 –1630 –1630 –1630 –1630 –1630 –1630 –1630 –1630 –954 –774 –594 –414 –234 –54 The pin numbers are those for the QIP-64A mass production package. The pad coordinates given above take the center of the chip as the origin and specify the center of the pad. TESTA pin (pin 2) in the QIP-64A product must be connected to the minus side of the power supply. TEST pin (pin 3) in the QIP-64A product must be left open. Pad 27 in the chip product must either be connected to the minus side of the power supply or left open. Pads 28, 45 and 46 in the chip product must be left open. If the chip product is used, the substrate must be connected to VDD. Do not use dip-soldering techniques to mount the QIP-64A package product. No. 4365-3/29 LC5852N System Block Diagram LC5852N System Block Diagram AC: ALU: INT CTL: PC: TM: IR: HALT: SCG: STS1: STS2: STS3: Accumulator Arithmetic and logic unit Interrupt control circuit Program counter Preset timer (6 bits) Instruction register Intermittent control circuit System clock generator Status register 1 Status register 2 Status register 3 CF: BCF: SCF1: SCF2: SCF3: SCF4: SCF5: ø15: SCF7: Carry flag Backup flag M port flag STS3 flag S port flag INT signal change flag Timer overflow flag Contents of the fifteenth stage of the divider circuit Divider circuit overflow flag No. 4365-4/29 LC5852N Pin Functions I/O QIP-64 Pin No. VDD — 40 Power supply plus side BAK — 41 LSI internal logic block minus power supply In Li specification products, connect a capacitor between BAK and VDD to prevent incorrect operation. Pin Function VSS1 VSS2 VSS3 — — — 42 43 39 Power supply minus side • External component connections differ depending on mask options and other factors. In products for Ag use, connect VSS1 to the power supply minus side. In other products, connect VSS2 to the power supply minus side. • The pins other than the minus pin are used for the LCD driver power supply. CUP1 CUP2 — — 4 5 Connections for the LCD drive voltage boost (cut) capacitor. Input 8 OSC-IN Used for real-time clock and the system clock. OSC-OUT Option At reset Backup flag set Backup flag cleared (depending on the power supply option) • Ag specifications • Li specifications • EXT-V specifications • Crystal oscillator use (XT option) • Ceramic resonator use (CF option) The CF option can only be specified for EXT-V specification products. Output 9 — — Connected to OSC-IN or OSC-OUT and used for the oscillator phase compensation capacitor. Can only be used in the chip product. S1 S2 S3 S4 Input 7 6 47 46 Dedicated input port • Includes either a ø10 (32 ms), ø8 (8 ms), or ø2 (2 ms) chattering exclusion circuit (PLA mask option). * These values are for the case where a 32.768 kHz crystal is used. • Pull-down resistors are built in. Inclusion (or exclusion) of a low level hold transistor The pull-down resistor transistor is on. M1 M2 M3 M4 Input 62 63 64 1 Dedicated input port • Input connections for acquiring data to internal RAM • Pull-down resistors are built in. Inclusion (or exclusion) of a low level hold transistor The pull-down resistor transistor is on. I/O A1 I/O A2 I/O A3 I/O A4 I/O 48 49 50 51 I/O port • Input connections for acquiring data to internal RAM • Output connections for data output from internal RAM • The input or output state can be switched by two instructions. Input mode I/O B1 I/O B2 I/O B3 I/O B4 I/O 52 53 54 55 I/O port • Input connections for acquiring data to internal RAM • Output connections for data output from internal RAM • The input or output state can be switched by two instructions. Input mode Output 58 59 60 61 Output port • Output connections for data output from internal RAM Either a high- or low-level output. (Undefined) 10P P1 P2 P3 P4 ALM Output 44 Dedicated output This pin can output a signal modulated either at 4 kHz or 2 kHz, or at 4 kHz or 1 kHz under program control. Alternatively, an unmodulated signal can be output. * These values are for the case where a 32.768 kHz crystal is used. LIGHT Output 45 Dedicated output This pin can drive a power transistor. • Modulated signals (4 kHz, 2 kHz, or unmodulated) • Modulated signals (4 kHz, 1 kHz, or unmodulated) Low-level output Low-level output Continued on next page. No. 4365-5/29 LC5852N Continued from preceding page. Pin RES I/O QIP-64 Pin No. Input 56 Function Option LSI internal reset input • Reset can be performed on either a high or low input level. • Built-in pull-up or pull-down resistor Note: The applied signal must be held for at least 500 µs. Pull-up or pull-down resistor selection • Pull-up or pulldown resistor selection • Signal change type (rising or falling) selection INT Input 57 External interrupt request input • Interrupt detection can be performed for either falling or rising edges. • Built-in pull-up or pull-down resistor TESTA Input 2 Test input • QIP-64 products: connect to the power supply – side • Chip products: Leave open or connect to the power supply – side — 3 Test input This pin must be left open. (It cannot be used in user systems.) TEST Seg1 Seg2 to Seg25 Output 11 12 to36 • LCD drive/general-purpose output pins — LCD drive I STATIC II 1/2 bias – 1/2 duty III 1/2 bias – 1/3 duty IV 1/2 bias – 1/4 duty V 1/3 bias – 1/3 duty VI 1/3 bias – 1/4 duty Items I to V are specified as master options. • General-purpose output mode (CMOS output) — LCD/general-purpose output control under program control is disabled by adoption of the segment PLA. — Arbitrary combinations of LCD drive and general purpose outputs are possible. • Switching between LCD drive outputs and generalpurpose outputs • LCD drive method switching — STATIC — 1/2 bias – 1/2 duty — 1/2 bias – 1/3 duty — 1/2 bias – 1/4 duty — 1/3 bias – 1/3 duty — 1/3 bias – 1/4 duty • General-purpose outputs — CMOS At reset • LCD drive — All segments lit — All segments off * Set by a mask option • General-purpose outputs — High level — Low level * Set by a mask option LCD common polarity drive outputs These pins are used as follows depending on the LCD drive method used. (Note that these are typical specifications for 32.768 kHz when ø0 is used for the alternation frequency.) COM1 COM2 COM3 COM4 Output 10 38 37 24 COM1 COM2 COM3 COM4 Alternation frequency Static 1/2 duty 1/3 duty 1/4 duty ❍ ❍ ❍ ❍ ❍ ❍ × ❍ ❍ ❍ ❍ 42.7 Hz 32 Hz × × × 32 Hz × × 32 Hz Note: An × indicates that the corrsponding common pin is not used with that LCD drive method. LCD drive type. Do not use hold mode in CF specification products that use the LCD driver. (The alternation frequency signal is stopped in hold mode.) No. 4365-6/29 LC5852N Application Circuit Examples 1. Representative application for Ag specification products (1/3 bias - 1/4 duty) 2. Representative application for lithium specification products (1/2 bias - 1/4 duty) 3. Representative application for EXT-V specification products (1/2 bias - 1/4 duty) No. 4365-7/29 LC5852N Oscillator Circuit Options Option Circuit Form Note CF • 400 kHz • 800 kHz • The cycle time is 4 × n times the f1 period (n : 2). • The divider outputs (ø1 to ø15) are used, for example, as the LCD drive waveform generation clock and as the S and K port chattering prevention clock. Xtal (32.768 kHz) • The cycle time is four times the f1 period. • The divider outputs (ø1 to ø15) are used, for example, as the LCD drive waveform generation clock, as the S and K port chattering prevention clock and as a clock time base. • The 10P connection can only be used in chip products. Xtal (65 kHz) • The cycle time is four times the f1 period. (Used when the cycle time is 61 µs.) • The divider outputs (ø1 to ø15) are used, for example, as the LCD drive waveform generation clock and as the S and K port chattering prevention clock. • The 10P connection can only be used in chip products. No. 4365-8/29 LC5852N Crystal Oscillator Options Option Circuit Form Note The resistor Rd for use with a 32 kHz frequency is built in. 32 kHz 65 kHz INT Pin Options Option Circuit Form Note Pull-up resistor, pull-down resistor, or resistor open selection Built-in resistor selection • Use of the pull-up resistor • Use of the pull-down resistor • Open Rising edge, falling edge detection selection Signal change edge detection selection • Rising edge detection • Falling edge detection RES Pin Options Option Pull-up resistor, pull-down resistor, or resistor open and level selection Circuit Form Note Built-in resistor and polarity selection • Pull-up resistor and reset on low • Pull-down resistor and reset on high • Both resistors open and reset on low • Both resistors open and reset on high No. 4365-9/29 LC5852N Input Port Options Option Circuit Form Note Use of the hold transistor (low level hold transistor) This option can be specified individually for each pin in S1 to S4 and M1 to M4. When use of the hold transistor is selected: • This transistor is used to reduce the current drain in the pull-up or pull-down resistor when, for example, a push-button switch is used for S1 or a slide switch is used for S2. • When the input open specifications are used, this transistor turns the resistor on prior to reading the input value and then turns the resistor off after the input value is read. If the input is floating when read, the low-level input hold transistor will operate and hold that level. Hold transistor unused (open) When the hold transistor is unused: • The pull-down transistor can be used as a pull-down resistor. • The pull-down transistor can be turned on and off under program control. • The pull-down resistor can be used in the on state without change. • Select the unused option if the input is connected to an external control signal line that will never go to the floating state. • On reset — The resistor will be in the on state during the reset period. — The resistor will keep up the on state when reset is cleared. The use of the low level hold transistor can be specified individually for each pin in the S1 to S4 and M1 to M4 ports. 1. The S port includes independent (in bit units) chattering exclusion circuits with periods of ø10, ø8, or ø6. 2. The M port includes chattering exclusion circuits that operate for halt mode clear request signals. These circuits exclude chattering for periods of ø10, ø8, or ø6 when three of the ports are at the low level and a signal change occurs on the remaining port. LCD Output Options Option Circuit Form LCD drive • Used as LCD segment drive pins • The LCD drive type is specified independently. The LCD drive type is common to all LCD drive pins and can be selected from the following set: static, 1/2 bias—1/2 duty, 1/2 bias—1/3 duty, 1/2 bias—1/4 duty, 1/3 bias—1/3 duty, or 1/3 bias—1/4 duty. CMOS output port • General-purpose CMOS output ports P-channel open-drain output port • General-purpose p-channel open-drain output ports This option can be specified for three specific ports using PLA option specification. Available ports...Pads 64 to 66 (pins 34 to 36) No. 4365-10/29 LC5852N Mask Option Overview 1. Power supply specification selection • Ag (Silver battery/1.5 V) specifications • Li (Lithium battery/3.0 V) specifications • EXT-V specifications (the operating voltage range depends on the oscillator used) 2. Oscillator selection • Crystal oscillator (32.768 kHz) • Crystal oscillator (65.536 kHz) • Ceramic oscillator 3. LCD drive • Static • 1/2 bias—1/2 duty • 1/2 bias—1/3 duty • 1/2 bias—1/4 duty • 1/3 bias—1/3 duty • 1/3 bias—1/4 duty Note: The LCD ports can all be used as general-purpose outputs. In this case, specify the “UNUSE” option. 6. LCD alternation frequency • SLOW (OSC/2048) • TYP (OSC/1024) • FAST (OSC/512) • STOP 5. S port low-level hold transistor • Level hold transistor present • No level hold transistor 6. M port low-level hold transistor • Level hold transistor present • No level hold transistor 7. S and M port chattering exclusion frequency • SLOW (OSC/1024) • TYP (OSC/256) • FAST (OSC/64) 8. INT pin resistor selection and signal edge type selection • Pull-up resistor (negative) • Pull-down resistor (positive) • Open (negative) • Open (positive) 9. External reset • RES pin • Simultaneous input to S1 through S4 10. RES pin • Pull-up resistor (low-level reset) • Pull-down resistor (high-level reset) • Open (low-level reset) • Open (high-level reset) 11. Power-on reset function (internal reset) • USE • UNUSE 12. Timer input clock • SLOW (OSC/512) • FAST (OSC/8) 13. Alarm modulation base frequency • SLOW (OSC/8, OSC/32) • TYP (OSC/8, OSC/16) 14. Cycle time • SLOW (OSC/8) • FAST (OSC/4) Note: Specify “SLOW” for this option if a ceramic oscillator is used. No. 4365-11/29 LC5852N Internal Register Functions Symbol R/W Initialization value at reset Function Program counter The PC is an 11-bit counter that specifies the program memory (ROM) address of the next instruction to be executed. Normally, the PC is incremented on each instruction execution, from 000H to 7FFH. However, when a branch or subroutine call is executed, or when an interrupt or initializing reset occurs, the PC is set to a value corresponding to the particular operation. The table below shows how the PC is set for these operations. PC Operation Initializing reset PC — PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 0 0 0 0 0 0 0 0 0 0 0 INT pin external interrupt 0 0 0 0 0 0 1 0 0 0 0 S or M port external interrupt 0 0 0 0 0 0 1 0 1 0 0 Timer internal interrupt 0 0 0 0 0 0 1 1 0 0 0 Divider internal interrupt 0 0 0 0 0 0 1 1 1 0 0 Page P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 Conditional jump (BAB0, BAB1, BAB2, BAB3, Page BAZ, BANZ, BCH, BCNH) Unconditional jump (JMP) P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 Subroutine call instruction (CALL) Page P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 Return instruction (RTS, RTSR) CALL address + 1 Page: P0 – P9: ROM paging performed in 1024 word pages Pages are specified with the SF and RF instructions. Instruction code bits (immediate data) Program memory The on-chip ROM consists of 2048 15-bit words and holds the user programs to be executed. ROM RAM R/O R/W Data memory The on-chip RAM consists of 128 4-bit digits of static RAM in two pages with 64 4-bit digits per page. This RAM has the following features: • RAM addresses can be specified directly (immediate addressing) as values in the range 00H to 3FH. • Arithmetic operations can be performed between the AC and any RAM location. • Due to the provision of the segment PLA circuit, RAM dedicated to display is not required. • RAM locations 38H to 3FH have a function that allows direct arithmetic operations with other data without using the AC. • The AC is used for RAM input, i.e., writing. Undefined Continued on next page. No. 4365-12/29 LC5852N Continued from preceding page. Symbol RAM R/W Initialization value at reset Function R/W Undefined Accumulator AC R/W Undefined Stack pointer The stack consists of four 13-bit words supporting subroutine calls and interrupts up to four levels deep. STACK R/W 01H P0 to P10: Program counter (PC) APG: RAM page flag OPG: ROM page flag APG R/W RAM page flag The RAM page flag is a single bit that allows the RAM to be expanded to two pages, where a single RAM page is 64 × 4 bits. 00H OPG R/W ROM page flag The ROM page flag is a single bit that allows the ROM to be expanded to two pages, where a single ROM page is 1024 × 15 bits. 00H TIM W Timer counter The timer is a 6-bit down counter. The timer is set from immediate data in an instruction. Undefined Continued on next page. No. 4365-13/29 LC5852N Continued from preceding page. Symbol R/W Function Initialization value at reset Status register 1 (STS1) Status register 1 is a four-bit register whose bits are used as shown below. STS1 R/W 00H * The test flags cannot be used by application programs. Status register 2 (STS2) Status register 2 is a four-bit register whose bits are used as shown below. STS2 R/O Undefined SCF1: Set when there was a change in an M port signal (when enabled by an SSW instruction). SCF2: Set when any bit in STS3 is set. SCF3: Set when there was a change in an S port signal (when enabled with an SSW instruction). Status register 3 (STS3) Status register 3 is a four-bit register whose bits are used as shown below. STS3 R/O Undefined SCF4: Set when there was a change in the INT pin signal (when enabled by an SIC instruction). SCF5: Timer underflow (when enabled by an SIC instruction) SCF4: Divider overflow (when enabled by an SIC instruction) No. 4365-14/29 LC5852N Specifications These electrical specifications are provisional and subject to change. EXT-V Specifications Absolute Maximum Ratings at VDD = 0 V Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Symbol max Unit VSS1 Conditions/Pins min –7.0 typ +0.3 V VSS2 –7.0 +0.3 V VSS3 LCD drive method (1/3 bias) –8.5 +0.3 V VSS3 LCD drive method (Any method other than 1/3 bias) –7.0 +0.3 V VIN1 S1 to 4, M1 to 4, I/OA1 to 4, I/OB1 to 4, INT, RES, OSCIN, 10P, TESTA (with I/OA1 to 4 and I/OB1 to 4 in input mode, 10P is for chip products) VSS2 – 0.3 +0.3 V VOUT1 ALM, LIGHT, P1 to 4, CUP2, OSCOUT, TEST, I/OA1 to 4, I/OB1 to 4 (with I/OA and I/OB in output mode) VSS2 – 0.3 +0.3 V VOUT2 SEGOUT, COM1 to 4, CUP1 VSS3 V Operating temperature Topr –20 +70 °C Storage temperature Tstg –30 +125 °C max Unit Allowable Operating Ranges at Ta = –20 to +70°C, VDD = 0 V Parameter Symbol Conditions/Pins VSS1 Supply voltage Supply voltage Supply voltage Supply voltage min typ –5.5 –1.3 V –5.5 –2.0 V VSS3 –8.25 –2.0 V VSS1 –5.5 –1.3 V V VSS2 VSS2 32 kHz crystal oscillator specifications –5.5 –2.3 VSS3 –8.25 –2.3 V VSS1 –5.5 –1.7 V V VSS2 65 kHz crystal oscillator specifications –5.5 –3.5 VSS3 –8.25 –3.5 V VSS1 –5.5 –2.0 V VSS2 External input used –5.5 –4.0 V VSS3 400 kHz CF specifications –8.25 –4.0 V Input high level voltage VIH1 0.3 × VSS2 0 V Input low level voltage VIL1 VSS2 0.7 × VSS2 V Input high level voltage VIH2 0.2 × VSS2 0 V Input low level voltage VIL2 V All input ports except OSCIN OSCIN pin, when external input used, Figure 8 VSS2 0.8 × VSS2 32 33 kHz Operating frequency fopg1 VSS2 = –2.0 to –5.5 V OSCIN/OSCOUT, 32 kHz crystal oscillator, Figure 2 Operating frequency fopg2 VSS2 = –2.3 to –5.5 V OSCIN/OSCOUT, 65 kHz crystal oscillator, Figure 2 60 66 kHz Operating frequency fopg3 VSS2 = –3.5 to –5.5 V OSCIN external input, Figure 8 32 220 kHz Operating frequency fopg4 VSS2 = –4.0 to –5.5 V OSCIN/OSCOUT, CF 400 kHz, Figure 1 360 400 440 kHz Operating frequency fopg5 VSS2 = –4.0 to –5.5 V OSCIN/OSCOUT, CF 800 kHz, Figure 1 720 800 880 kHz Continued on next page. No. 4365-15/29 LC5852N Electrical Characteristics at Ta = –20 to +70°C, VDD = 0 V Parameter Input resistance Symbol Conditions/Pins min typ RIN1A VSS2 = –2.9 V, VIN = 0.8 × VSS2 Low-level hold transistor*, Figure 3 RIN1B VSS2 = –2.9 V, VIN = VDD Low-level pull-in transistor*, Figure 3 200 RIN2A VSS2 = –2.9 V, VIN = VSS2 INT pin pull-up resistor RIN2B VSS2 = –2.9 V, VIN = VDD INT pin pull-down resistor VSS2 = –2.9 V, VIN = VDD or VSS2 RES 5 –1 Input resistance RIN3 max 10 Unit 200 kΩ 700 2000 kΩ 200 700 2000 kΩ 200 700 2000 kΩ 50 kΩ Output high level voltage VOH (1) VSS2 = –2.4 V, IOH = 1 mA ALM Output low level voltage VOL (1) VSS2 = –2.4 V, IOL = 1 mA ALM Output high level voltage VOH (2) VSS2 = –2.4 V, IOH = 0.3 mA LIGHT, Port P Output low level voltage VOL (2) VSS2 = –2.4 V, IOL = 0.5 mA LIGHT, Port P Output high level voltage VOH (3) VSS2 = –2.4 V, IOH = 0.1 mA I/O ports –1 –0.3 V Output high level voltage VOH (4) VSS2 = –2.4 V, IOH = –50 µA I/O ports –0.6 –0.2 V Output low level voltage VOL (4) VSS2 = –2.4 V, IOL = 0.1 mA I/O ports Output high level voltage VOH (5) VSS2 = –2.4 V, IOH = –10 µA Output low level voltage VOL (5) VSS2 = –2.4 V, IOL = 100 µA Output high level voltage VOH (6) VSS2 = –2.4 V, IOH = –5 µA Output low level voltage VOL (6) VSS2 = –2.4 V, IOL = 20 µA –0.3 VSS2 + 0.3 –1 V VSS2 + 1 –0.3 VSS2 + 0.3 VSS2 + 0.3 V V VSS2 + 1 VSS2 + 1 V V Segment driver output impedances • When used as CMOS output ports Segment Pads 62 to 64, QIP64 pins 34 to 36 –1 Segment Pads 38 to 41 and 44 to 61, QIP64 pins 11 to 23 and 25 to 33 –1 Segment Pads 62 to 64, QIP64 pins 34 to 36 –1 –0.3 VSS2 + 0.3 V VSS2 + 1 –0.3 VSS2 + 0.3 V V VSS2 + 1 V • When used as p-channel open-drain output ports Output high level voltage VOH (5) VSS2 = –2.4 V, IOH = –10 µA Output off leakage current IOFF VSS2 = –2.9 V, VOL = VSS2 VOH (5) VSS2 = –2.4 V, IOH = –0.4 µA, –0.3 V 1 µA • Static drive Output high level voltage Output low level voltage VOL (5) VSS2 = –2.4 V, IOL = 0.4 µA Output high level voltage VOH (7) VSS2 = –2.4 V, IOH = –4 µA Output low level voltage VOL (7) VSS2 = –2.4 V, IOL = 4 µA VOH (5) VSS2 = –2.4 V, IOH = –0.4 µA –0.2 V All segments VSS2 + 0.2 –0.2 V V COM1 VSS2 + 0.2 V • Duplex drive (1/2 bias—1/2 duty) Output high level voltage Output low level voltage VOL (5) VSS2 = –2.4 V, IOL = 0.4 µA Output high level voltage VOH (7) VSS2 = –2.4 V, IOH = –4 µA VOM VSS2 = –2.4 V, IOH = –4µA, IOL = 4 µA VOL (7) VSS2 = –2.4 V, IOL = 4 µA Output middle level voltage Output low level voltage –0.2 V All segments VSS2 + 0.2 –0.2 COM1, 2 VSS2/2 – 0.2 V V VSS2/2 + 0.2 V VSS2 + 0.2 V Note: * S1, S2, S3, S4, M1, M2, M3, M4 Continued on next page. No. 4365-16/29 LC5852N Continued from preceding page. Parameter Symbol Conditions min typ max Unit • 1/2 bias—1/3 duty and 1/2 bias—1/4 duty methods Output high level voltage VOH (5) VSS2 = –2.4 V, IOH = –0.4 µA Output low level voltage VOL (5) VSS2 = –2.4 V, IOL = 0.4 µA Output high level voltage VOH (7) VSS2 = –2.4 V, IOH = –4 µA Output middle level voltage Output low level voltage VOM VSS2 = –2.4 V, IOH = –4 µA, IOL = 4 µA VOL (7) VSS2 = –2.4 V, IOL = 4 µA –0.2 V All segments VSS2 + 0.2 –0.2 COM1 to 3 (for 1/3 duty methods) COM1 to 4 (for 1/4 duty methods) V V VSS2/2 – 0.2 VSS2/2 + 0.2 V VSS2 + 0.2 V • 1/3 bias—1/3 duty and 1/3 bias—1/4 duty methods VOH (5) VSS2 = –2.4 V, IOH = –0.4 µA VOM1-1 VSS2 = –2.4 V, IOH = –0.4 µA VOM1-2 IOL = 0.4 µA Output low level voltage VOL (5) VSS2 = –2.4 V, IOL = 0.4 µA Output high level voltage VOH (7) VSS2 = –2.4 V, IOH = –4 µA Output high level voltage Output middle level voltage Output middle level voltage Output low level voltage VOM2-1 VSS2 = –2.4 V, IOH = –4 µA VOM2-2 IOL = 4 µA VOL (7) VSS2 = –2.4 V, IOL = 4 µA –0.2 All segments V VSS2/2 – 0.2 VSS2/2 + 0.2 V VSS2 – 0.2 VSS2 + 0.2 V VSS3 + 0.2 V –0.2 COM1 to 3 (for 1/3 duty methods) COM1 to 4 (for 1/4 duty methods) V VSS2/2 –0.2 VSS2/2 +0.2 V VSS2 – 0.2 VSS2 + 0.2 V VSS3 + 0.2 V max Unit Electrical Characteristics at Ta = –20 to +70°C, VDD = 0 V Parameter Input resistance Symbol Conditions RIN1A VSS2 = –5.0 V, VIN = 0.8 · VSS2 Low-level hold transistor*, Figure 3 RIN1B VSS2 = –5.0 V, VIN = VDD RIN2A RIN2B RIN3 min typ 10 45 150 kΩ Low-level pull-in transistor*, Figure 3 100 350 1000 kΩ VSS2 = –5.0 V, VIN = VSS2 INT pin pull-up resistor 100 350 1000 kΩ VSS2 = –5.0 V, VIN = VDD INT pin pull-down resistor 100 350 1000 kΩ VSS2 = –5.0 V, VIN = VDD or VSS2 RES 10 20 50 kΩ –1 –0.3 Output high level voltage VOH (1) VSS2 = –3.5 to –5.25 V, IOH = –1.5 mA ALM Output low level voltage VOL (1) VSS2 = –3.5 to –5.25 V, IOL = 1.5 mA ALM Output high level voltage VOH (2) VSS2 = –3.5 to –5.25 V, IOH = –0.5 mA LIGHT, Port P Output low level voltage VOL (2) VSS2 = –3.5 to –5.25 V, IOL = 0.7 mA LIGHT, Port P Output high level voltage VOH (3) VSS2 = –3.5 to –5.25 V, IOH = –0.13 mA I/O ports –1 –0.3 V Output high level voltage VOH (4) VSS2 = –3.5 to –5.25 V, IOH = –50 µA I/O ports –0.6 –0.2 V Output low level voltage VOL (4) VSS2 = –3.5 to –5.25 V, IOL = 0.13 mA I/O ports VSS2 + 0.3 –1 V VSS2 + 1 –0.3 VSS2 + 0.3 VSS2 + 0.3 V V VSS2 + 1 VSS2 + 1 V V Note: * S1, S2, S3, S4, M1, M2, M3, M4 Continued on next page. No. 4365-17/29 LC5852N Continued from preceding page. Parameter Symbol Conditions min typ max Unit Segment driver output impedances • When used as CMOS output ports Output high level voltage VOH (5) VSS2 = –3.5 to –5.25 V, IOH = –15 µA Output low level voltage VOL (5) VSS2 = –3.5 to –5.25 V, IOL = 150 µA Output high level voltage VOH (6) VSS2 = –3.5 to –5.25 V, IOH = –10 µA Output low level voltage VOL (6) VSS2 = –3.5 to –5.25 V, IOL = 60 µA Segment Pads 62 to 64, QIP64 pins 34 to 36 –1 –0.3 VSS2 + 0.3 Segment Pads 38 to 41 and 44 to 61, QIP64 pins 11 to 23 and 25 to 33 –1 Segment Pads 62 to 64, QIP64 pins 34 to 36 –1 V VSS2 + 1 –0.3 VSS2 + 0.3 V V VSS2 + 1 V • When used as p-channel open-drain output ports Output high level voltage VOH (5) VSS2 = –3.5 to –5.25 V, IOH = –15 µA Output off leakage current IOFF VSS2 = –3.5 to –5.25 V, VOL = VSS2 VOH (5) VSS2 = –3.5 to –5.25 V, IOH = –0.4 µA –0.3 V 1 µA • Static drive Output high level voltage Output low level voltage VOL (5) VSS2 = –3.5 to –5.25 V, IOL = 0.4 µA Output high level voltage VOH (7) VSS2 = –3.5 to –5.25 V, IOH = –4 µA Output low level voltage VOL (7) VSS2 = – 3.5 to –5.25 V, IOL = 4 µA VOH (5) VSS2 = –3.5 to –5.25 V, IOH = –0.4 µA –0.2 V All segments VSS2 + 0.2 –0.2 V V COM1 VSS2 + 0.2 V • Duplex drive (1/2 bias—1/2 duty) Output high level voltage Output low level voltage VOL (5) VSS2 = –3.5 to –5.25 V, IOL = 0.4 µA Output high level voltage VOH (7) VSS2 = –3.5 to –5.25 V, IOH = –4 µA Output middle level voltage VOM2-1 VSS2 = –3.5 to –5.25 V, IOH = –4 µA, IOL = 4 µA Output low level voltage VOL (7) VSS2 = –3.5 to –5.25 V, IOL = 4 µA –0.2 V All segments VSS2 + 0.2 –0.2 COM1, 2 VSS2/2 – 0.2 V V VSS2/2 +0.2 V VSS2 +0.2 V • 1/2 bias—1/3 duty and 1/2 bias—1/4 duty methods Output high level voltage VOH (5) VSS2 = –3.5 to –5.25 V, IOH = –0.4 µA Output low level voltage VOL (5) VSS2 = –3.5 to –5.25 V, IOL = 0.4 µA Output high level voltage VOH (7) VSS2 = –3.5 to –5.25 V, IOH = –4 µA Output middle level voltage VOM2-1 VSS2 = –3.5 to –5.25 V, IOH = –4 µA, IOL = 4 µA Output low level voltage VOL (7) VSS2 = –3.5 to –5.25 V, IOL = 4 µA –0.2 V All segments VSS2 + 0.2 COM1 to 3 (for 1/3 duty methods) COM1 to 4 (for 1/4 duty methods) –0.2 VSS2/2 – 0.2 V V VSS2/2 +0.2 V VSS2 + 0.2 V • 1/3 bias—1/3 duty and 1/3 bias—1/4 duty methods Output high level voltage Output middle level voltage VOH (5) VOM1-1 VOM1-2 VSS2 = –3.5 to –5.25 V, IOH = –0.4 µA VSS2 = –3.5 to –5.25 V, IOH = –0.4 µA, IOL = 0.4 µA Output low level voltage VOL (5) VSS2 = –3.5 to –5.25 V, IOL = 0.4 µA Output high level voltage VOH (7) VSS2 = –3.5 to –5.25 V, IOH = –0.4 µA Output low level voltage VOM2-1 VOM2-2 Output low level voltage VOL (7) VSS2 = –3.5 to –5.25 V, IOH = –4 µA, IOL = 4 µA VSS2 = –3.5 to –5.25 V, IOL = 4 µA –0.2 All segments V VSS2/2 – 0.2 VSS2/2 +0.2 V VSS2 – 0.2 VSS2 + 0.2 V VSS3 + 0.2 V –0.2 V COM1 to 3 (for 1/3 duty methods) VSS2/2 – 0.2 VSS2/2 +0.2 V COM1 to 4 (for 1/4 duty methods) VSS2 – 0.2 VSS2 + 0.2 V VSS3 + 0.2 V Continued on next page. No. 4365-18/29 LC5852N Continued from preceding page. Parameter Power supply leakage current Input leakage current Output voltage Output voltage Symbol Conditions ILEK VSS2 = VSS3 = –4.5 V Ta = 25°C IIN VSS2 = –2.0 to +4.5 V VIN = VSS2 to VDD VSS1 VSS2 = –2.9 V VSS3 VSS2 = –2.9 V C1 = C2 = C3 = 0.1 µF, fopg = 32.768 kHz, Ta = 25°C, Figure 7 C1 = C2 = C3 = 0.1 µF, fopg = 32.768 kHz, Ta = 25°C, Figure 7 VSS1 VSS2 = –4.5 V VSS3 VSS2 = –4.5 V min typ max Unit 10 µA +1 µA –1.45 –1.35 V –4.35 –4.1 V –2.25 –2.2 V –6.70 –6.6 V 3.0 6.0 µA 7 13 µA –1 | IDD1 | VSS2 = –2.9 V, Ta = 25°C, HALT mode | IDD2 | VSS2 = –4.5 V, Ta = 25°C, HALT mode, Stack: Figure 9, 1/3 bias—1/3 duty: Figure 7, other methods: Figure 4 | IDD3 | VSS2 = –4.5 V, Ta = 25°C, HALT mode Stack: Figure 9, 1/3 bias—1/3 duty: Figure 7, other methods: Figure 4 C1 = C2 = 0.1 µF, Cl = 25 kΩ, fopg = 65.536 kHz, Cg = 10 pF 10 20 µA | IDD4 | VSS2 = –4.5 V, Ta = 25°C, HALT mode C1 = C2 = 0.1 µF, fopg = 400 kHz, Cg = Cd = 100 pF or 330 pF, Rf = 1 MΩ, Figure 6 90 150 µA | IDD5 | VSS2 = –4.5 V, Ta = 25°C, HALT mode C1 = C2 = 0.1 µF, fopg = 800 kHz, Cg = Cd = 100 pF, Rf = 1 MΩ, Figure 6 130 200 µA Oscillator hold voltage | VHOLD1 | Ta = 25°C, Stack: Figure 9, 1/3 bias—1/3 duty: Figure 7, other methods: Figure 4 C1 = C2 = 0.1 µF, Cl = 25 kΩ, fopg = 32.768 kHz, Cg = 20 pF 2.0 5.5 V Oscillator hold voltage | VHOLD2 | Ta = 25°C C1 = C2 = 0.1 µF, Cl = 25 kΩ, fopg = 65.536 kHz, Cg = 10 pF 2.3 5.5 V C1 = C2 = 0.1 µF, Cl = 25 kΩ, Figure 5, fopg = 32.768 kHz, Cg = 20 pF 2.2 V 2.6 V 10 S 10 S 10 S 10 S 4.0 V 5.5 V 30 ms Power supply current Power supply current Power supply current Power supply current C1 = C2 = 0.1 µF, Cl = 25 kΩ, fopg = 32.768 kHz, Cg = 20 pF Oscillator start voltage | VStt1 | Stack: Figure 10, 1/3 bias—1/3 duty: Figure 7, other methods: Figure 4, Ta = 25°C Oscillator start voltage | VStt2 | Ta = 25°C C1 = C2 = 0.1 µF, Cl = 25 kΩ, Figure 5, fopg = 65.536 kHz, Cg = 10 pF VSS2 = –2.9 V, Ta = 25°C, VSS2 = –4.5 V, Ta = 25°C C1 = C2 = 0.1 µF, Cl = 25 kΩ, Figure 5, fopg = 32.768 kHz, Cg = 20 pF VSS2 = –2.9 V, Ta = 25°C, VSS2 = –4.5 V, Ta = 25°C C1 = C2 = 0.1 µF, Cl = 25 kΩ, Figure 5, fopg = 65.536 kHz, Cg = 10 pF Oscillator start time Oscillator start time TStt1 TStt2 Oscillator start voltage | VStt4 | Ta = 25°C fopg = 400 kHz, Figure 6, Cg = Cd = 100 pF or 330 pF, Rf = 1 MΩ Oscillator hold voltage | VHOLD4 | Ta = 25°C fopg = 400 kHz, Figure 6, Cg = Cd = 100 pF or 330 pF, Rf = 1 MΩ VSS2 = –4.5 V, Ta = 25°C fopg = 400 kHz, Figure 6, Cg = Cd = 100 pF or 330 pF, Rf = 1 MΩ Oscillator start time TStt4 3.5 Continued on next page. No. 4365-19/29 LC5852N Continued from preceding page. Parameter Symbol Conditions min typ max Unit 4.0 V 5.5 V 30 ms Oscillator start voltage | VStt5 | Ta = 25°C fopg = 800 kHz, Figure 6, Cg = Cd = 100 pF, Rf = 1 MΩ Oscillator hold voltage | VHOLD5 | Ta = 25°C fopg = 800 kHz, Figure 6, Cg = Cd = 100 pF, Rf = 1 MΩ TStt5 VSS2 = –4.5 V, Ta = 25°C fopg = 800 kHz, Figure 6, Cg = Cd = 100 pF, Rf = 1 MΩ 10P VSS2 = –2.9 V 10P pin (chip products only) 10 pF 10P VSS2 = –4.5 V 10P pin (chip products only) 10 pF 20P VSS2 = –2.9 V OSCOUT pin 20 pF 20P VSS2 = –4.5 V OSCOUT pin 20 pF Oscillator start time Oscillator correction capacitance Figure 1 Ceramic Oscillator Specifications 3.5 Figure 2 Crystal Oscillator Specifications (32 kHz or 65 kHz) Recommended Ceramic Oscillators Manufacturer Murata Kyocera Item frequency Type number Cg (pF) Cd (pF) Rf (MΩ) Type number Cg (pF) Cd (pF) Rf (MΩ) 400 kHz CSB400P 100 100 1 KBR-400B 330 330 1 800 kHz CSB800J 100 100 1 KBR-800H 100 100 1 Figure 3 S1 to S4 and M1 to M4 Input Circuits Figure 4 Power Supply Current and Oscillator Hold Voltage Test Circuit Figure 5 Oscillator Start Voltage, Oscillator Start Time and Frequency Stability Test Circuit Figure 6 Oscillator Start Voltage, Oscillator Start Time, Power Supply Current and Oscillator Hold Voltage Test Circuit No. 4365-20/29 LC5852N Figure 7 Power Supply Current and Oscillator Hold Voltage Test Circuit Figure 8 External Input Specifications Figure 9 Power Supply Current and Oscillator Hold Time Test Circuit No. 4365-21/29 LC5852N These electrical specifications are provisional and subject to change. Ag Specifications Absolute Maximum Ratings at Ta = 25°C, VDD = 0 V Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Symbol max Unit VSS1 Conditions/Pins min –4.0 typ +0.3 V VSS2 –4.0 +0.3 V VSS3 LCD drive method (1/3 bias) –5.5 +0.3 V VSS3 LCD drive method (methods other than 1/3 bias) –4.0 +0.3 V VIN1 S1 to 4, M1 to 4, I/OA1 to 4, I/OB1 to 4, INT, TESTA (with I/OA1 to 4 and I/OB1 to 4 in input mode), 1OP, OSCIN, RES, BAK VSS1 – 0.3 +0.3 V VOUT1 ALM, LIGHT, P1 to 4, I/OA1 to 4, I/OB1 to 4, CUP2 (with I/OA1 to 4 and I/OB1 to 4 in output mode), TESTA, OSCOUT VSS1 – 0.3 +0.3 V VOUT3 SEGOUT, COM1 to 4, CUP1 VSS1 – 0.3 +0.3 V Operating temperature Topr –20 +65 °C Storage temperature Tstg –30 +125 °C max Unit Allowable Operating Ranges at Ta = 25 ± 2°C, VDD = 0 V Parameter Symbol VSS1 Supply voltage Conditions/Pins VBAK = VSS1 VSS2 VSS3 LCD drive method (1/3 bias) VSS3 LCD drive method (methods other than 1/3 bias) Input high level voltage VIH S1 to 4, M1 to 4, I/OA1 to 4, I/OB1 to 4, RES, INT (with I/OA1 to 4 and I/OB1 to 4 in input mode) Input low level voltage VIL S1 to 4, M1 to 4, I/OA1 to 4, I/OB1 to 4, INT (with I/OA1 to 4 and I/OB1 to 4 in input mode) Operating frequency fopg Ta = –20 to +65°C min typ –1.65 –1.3 –3.3 –2.4 V V –4.95 –3.7 V –0.2 0 V VSS1 VSS1 + 0.2 V 32 33 VSS3 = VSS2 kHz Electrical Characteristics at Ta = 25 ± 2°C, VDD = 0 V Parameter min typ 10 50 200 kΩ Low-level pull-down resistor*, Figure 1 200 550 2000 kΩ VSS1 = –1.55 V, VIL = VSS1 INT pull-up resistor 200 400 2000 kΩ RIN2B VSS1 = –1.55 V, VIH = VDD INT pull-down resistor 200 550 2000 kΩ RIN3 VSS1 = –1.55 V, VIH = VDD RES pull-down resistor 50 kΩ VOH (1) VSS = –1.35 V, IOH = –250 µA ALM, LIGHT Output low level voltage VOL (1) VSS1 = –1.35 V, IOL = 250 µA Output high level voltage VOH (2) VSS = –1.55 V, I/OA1 to 4, I/OB1 to 4, IOH = –20 µA, P1 to 4 (with I/OA1 to 4 and I/OB1 to 4 in output mode) Output low level voltage VOL (2) VSS1 = –1.55 V, I/OA1 to 4, I/OB1 to 4, IOL = 20 µA, P1 to 4 (with I/OA1 to 4 and I/OB1 to 4 in output mode) Input resistance Output high level voltage Symbol Conditions/Pins RIN1A VSS1 = –1.55 V, VIL = VSS1 + 0.2 V Low-level hold transistor*, Figure 1 RIN1B VSS1 = –1.55 V RIN2A 5 max Unit –0.65 V VSS1 + 0.65 ALM, LIGHT –0.2 V V VSS1 + 0.2 Note: * S1, S2, S3, S4, M1, M2, M3, M4 Continued on next page. No. 4365-22/29 LC5852N Continued from preceding page. Parameter Symbol Conditions/Pins min typ max Unit Segment driver output impedances • When used as CMOS output ports Output high level voltage VOH (3) VSS1 = –1.55 V, IOH = –3 µA Output low level voltage VOL (3) VSS1 = –1.55 V, IOL = 3 µA Segment Pads 38 to 41 and 44 to 61, QIP64 pins 11 to 23 and 25 to 33 –0.3 V VSS2 + 0.3 V –0.3 V • When used as p-channel open drain outputs Output high level voltage VOH (3) VSS1 = –1.55 V, IOH = –3 µA Output off leakage current IOFF VSS1 = –1.55 V, VOL = VSS1 VOH (3) VSS1 = –1.55 V, IOH = –0.4 µA Segment Pads 62 to 64, QIP64 pins 34 to 36 –1 1 µA • Static drive Output high level voltage Output low level voltage VOL (3) VSS1 = –1.55 V, IOL = 0.4 µA Output high level voltage VOH (4) VSS1 = –1.55 V, IOH = –4 µA Output low level voltage VOL (4) VSS1 = –1.55 V, IOL = 4 µA VOH (3) VSS1 = –1.55 V, IOH = –0.4 µA –0.2 V SEGOUT VSS2 + 0.2 –0.2 V V COM1 VSS2 + 0.2 V • Duplex drive (1/2 bias—1/2 duty) Output high level voltage Output low level voltage VOL (3) VSS1 = –1.55 V, IOL = 0.4 µA Output high level voltage VOH (4) VSS1 = –1.55 V, IOH = –4 µA Output middle level voltage Output low level voltage VOM VOL (4) VSS1 = –1.55 V, IOH = –4 µA, IOL = 4 µA –0.2 V SEGOUT VSS2 + 0.2 –0.2 COM1, 2 VSS1 – 0.2 VSS2 = –1.55 V, IOL = 4 µA V V VSS1 + 0.2 V VSS2 + 0.2 V • 1/2 bias—1/3 duty and 1/2 bias—1/4 duty methods Output high level voltage VOH (3) VSS1 = –1.55 V, IOH = –0.4 µA Output low level voltage VOL (3) VSS1 = –1.55 V, IOL = 0.4 µA Output high level voltage VOH (4) VSS1 = –1.55 V, IOH = –4 µA Output middle level voltage Output low level voltage VOM VOL (4) VSS1 = –1.55 V, IOH = –4 µA, IOL = 4 µA VSS2 = –1.55 V, IOL = 4 µA –0.2 V SEGOUT VSS2 + 0.2 V VSS1 + 0.2 V VSS2 + 0.2 V –0.2 COM1 to 3 (for 1/3 duty methods) COM 1 to 4 (for 1/4 duty methods) VSS1 – 0.2 • 1/3 bias—1/3 duty and 1/3 bias—1/4 duty methods Output high level voltage VOH (3) VSS1 = –1.55 V, IOH = –0.4 µA Output M1 level voltage VOM1-3 VSS1 = –1.55 V, IOH = –0.4 µA, IOL = 0.4 µA Output M2 level voltage VOM2-3 VSS1 = –1.55 V, IOH = –0.4 µA, IOL = 0.4 µA Output low level voltage VOL (3) VSS1 = –1.55 V, IOL = 0.4 µA Output high level voltage VOH (4) VSS1 = –1.55 V, IOH = –4 µA Output M1 level voltage VOM1-4 VSS1 = –1.55 V, IOH = –4 µA, IOL = 4 µA Output M2 level voltage VOM2-4 VSS1 = –1.55 V, IOH = –4 µA, IOL = 4 µA Output low level voltage VOL (4) VSS2 = –1.55 V, IOL = 4 µA –0.2 V VSS1 – 0.2 VSS1 + 0.2 V VSS2 – 0.2 VSS2 + 0.2 V VSS3 + 0.2 V VSS1 – 0.2 VSS1 + 0.2 V VSS2 – 0.2 VSS2 + 0.2 V VSS3 + 0.2 V SEGOUT –0.2 COM1 to 3 (for 1/3 duty methods) COM 1 to 4 (for 1/4 duty methods) Continued on next page. No. 4365-23/29 LC5852N Continued from preceding page. Parameter Symbol Conditions/Pins min typ max Unit • Output voltage LCD drive: 1/3 bias methods (doubler) VSS2 VSS1 = –1.35 V, C1 to 4 = 0.1 µF fopg = 32.768 kHz, Figure 7 –2.5 V (tripler) VSS3 VSS1 = –1.35 V, C1 to 4 = 0.1 µF fopg = 32.768 kHz, Figure 7 –3.75 V LCD drive: 1/2 bias methods (doubler) VSS2 VSS1 = –1.35 V, C1 = C2 = 0.1 µF fopg = 32.768 kHz, Figure 2 –2.5 V • Supply current (when the backup flag is cleared to zero) LCD drive: 1/3 bias methods | IDD | VSS1 = –1.55 V, C1 to 4 = 0.1 µF Cd = Cg = 20 pF In HALT mode, Cl = 25 kΩ, Figure 7, 32.768 kHz, X’tal 1.3 4.5 µA LCD drive: methods other than 1/3 bias | IDD | VSS1 = –1.55 V, C1 = C2 = 0.1 µF Cd = Cg = 20 pF In HALT mode, Cl = 25 kΩ, Figure 2, 32.768 kHz, X’tal 1.1 4.5 µA Oscillator start voltage VSS1 | Vstt | Cd = Cg = 20 pF Cl = 25 kΩ, Figure 3, 32.768 kHz, X’tal 1.35 V Oscillator hold voltage VSS1 | VHOLD | Cd = Cg = 20 pF Cl = 25 kΩ, Figure 2, 32.768 kHz, X’tal 1.6 V Tstt VSS1 = –1.35 V, Cd = Cg = 20 pF Cl = 25 kΩ, Figure 3, 32.768 kHz, X’tal 10 s 10P External connection (for chip products) 20P OSCOUT Oscillator start time Oscillator correction capacitance 1.3 8 10 12 pF 16 20 24 pF No. 4365-24/29 LC5852N These electrical specifications are provisional and subject to change. Li Specifications Absolute Maximum Ratings at Ta = 25 ± 2°C, VDD = 0 V Parameter Symbol VSS1 Maximum supply voltage VSS2 min typ max Unit –4.0 +0.3 V –4.0 +0.3 V V VSS3 LCD drive: 1/3 bias methods –5.5 +0.3 VSS3 LCD drive: methods other than 1/3 bias –4.0 +0.3 V VIN1 10P, OSCIN VBAK – 0.3 +0.3 V VIN2 S1 to 4, M1 to 4, I/IA1 to 4, I/OB1 to 4, RES, INT, TESTA, (with I/OA1 to 4 and I/OB1 to 4 in input mode) VSS2 – 0.3 +0.3 V VOUT1 TEST, OSCOUT VBAK – 0.3 +0.3 V VOUT2 ALM, LIGHT, P1 to 4, I/OA1 to 4, I/OB1 to 4, CUP2 (with I/OA1 to 4 and I/OB1 to 4 in output mode) VSS2 – 0.3 +0.3 V VOUT3 SEGOUT, COM1 to 4, CUP1 Maximum input voltage Maximum output voltage Conditions/Pins VBAK = VSS1 or VSS2 VSS3 – 0.3 +0.3 V Operating temperature Topr –20 +65 °C Storage temperature Tstg –30 +125 °C max Unit Allowable Operating Ranges at Ta = 25 ± 2°C, VDD = 0 V Parameter Symbol Conditions/Pins VBAK Supply voltage min typ –3.6 –1.3 V VSS2 VBAK = VSS2/2 (with the backup flag cleared to zero) –3.6 –2.6 V VSS2 VBAK = VSS2 (with the backup flag cleared to zero) –3.6 –1.3 V VSS3 LCD drive: 1/3 bias methods –4.95 –3.7 VSS3 LCD drive: methods other than 1/3 bias Input high level voltage VIH S1 to 4, M1 to 4, I/OA1 to 4, I/OB1 to 4, INT (with I/OA1 to 4 and I/OB1 to 4 in input mode) Input low level voltage VIL S1 to 4, M1 to 4, I/OA1 to 4, I/OB1 to 4, INT (with I/OA1 to 4 and I/OB1 to 4 in input mode) Operating frequency fopg Ta = –20 to +65°C VSS3 = VSS2 –0.4 0 V VSS2 VSS2 + 0.4 V 32 33 kHz Electrical Characteristics at Ta = 25 ± 2°C, VDD = 0 V Parameter Input resistance Symbol Conditions/Pins max Unit 10 200 kΩ Pull-down resistor*, Figure 4 200 2000 kΩ VSS2 = –2.9 V, VIL = VSS2 INT pull-up resistor 200 2000 kΩ RIN2B VSS2 = –2.9 V, VIH = VDD INT pull-down resistor 200 2000 kΩ RIN3 VSS2 = –2.9 V, VIH = VDD RES pull-down resistor 5 50 kΩ RIN1A VSS2 = –2.9 V, VIL = VSS2 + 0.4 V Low-level hold transistor*, Figure 1 RIN1B VSS2 = –2.9 V, RIN2A min typ Note: * S1, S2, S3, S4, M1, M2, M3, M4 Continued on next page. No. 4365-25/29 LC5852N Continued from preceding page. Parameter Symbol Conditions/Pins Output high level voltage VOH (1) VSS2 = –2.4 V, IOH = –250 µA Output low level voltage VOL (1) VSS2 = –2.4 V, IOH = 250 µA Output high level voltage VOH (2) VSS2 = –2.9 V, I/OA1 to 4, I/OB1 to 4, IOH = –40 µA, P1 to 4 (with I/OA1 to 4 and I/OB1 to 4 in output mode) Output low level voltage VOL (2) VSS2 = –2.9 V, I/OA1 to 4, I/OB1 to 4, IOL = 40 µA, P1 to 4 (with I/OA1 to 4 and I/OB1 to 4 in output mode) Output high level voltage VOH (3) VSS2 = –2.9 V, IOH = –150 µA LIGHT Output low level voltage VOL (3) VSS2 = –2.9 V, IOL = 150 µA LIGHT Output high level voltage VOH (4) VSS2 = –2.9 V, IOH = –5 µA Output low level voltage VOL (4) VSS2 = –2.9 V, IOL = 5 µA ALM ALM min typ max Unit –0.65 V VSS2 + 0.65 –0.4 V V VSS2 + 0.4 –1.5 V V VSS2 + 1.5 V Segment driver output impedances • When used as CMOS output ports Segment Pads 38 to 41 and 44 to 61, QIP64 pins 11 to 23 and 25 to 33 –0.3 V VSS2 + 0.3 V –0.3 V • When used as p-channel open-drain output ports Output high level voltage VOH (4) VSS2 = –2.4 V, IOH = –10 µA Output off leakage current IOFF VSS2 = –2.9 V, VOL = VSS2 VOH (4) VSS2 = –2.9 V, IOH = –0.4 µA Segment Pads 62 to 64, QIP64 pins 34 to 36 –1 1 µA • Static drive Output high level voltage Output low level voltage VOL (4) VSS2 = –2.9 V, IOL = 0.4 µA Output high level voltage VOH (5) VSS2 = –2.9 V, IOH = –4 µA Output low level voltage VOL (5) VSS2 = –2.9 V, IOL = 4 µA VOH (4) VSS2 = –2.9 V, IOH = –0.4 µA –0.2 V All SEGOUT pins VSS2 + 0.2 –0.2 V V COM1 VSS2 + 0.2 V • Duplex drive (1/2 bias—1/2 duty) Output high level voltage Output low level voltage VOL (4) VSS2 = –2.9 V, IOL = 0.4 µA Output high level voltage VOH (5) VSS2 = –2.9 V, IOH = –4 µA Output middle level voltage Output low level voltage VOM VOL (5) VSS2 = –2.9 V, IOH = –4 µA, IOL = 4 µA –0.2 V All SEGOUT pins VSS2 + 0.2 –0.2 COM1 to 4 VSS2/2 – 0.2 VSS2 = –2.9 V, IOL = 4 µA V V VSS2/2 +0.2 V VSS2 + 0.2 V • 1/2 bias—1/3 duty and 1/2 bias—1/4 duty methods Output high level voltage VOH (4) VSS2 = –2.9 V, IOH = –0.4 µA Output low level voltage VOL (4) VSS2 = –2.9 V, IOL = 0.4 µA Output high level voltage VOH (5) VSS2 = –2.9 V, IOH = –4 µA Output middle level voltage Output low level voltage VOM VOL (5) VSS2 = –2.9 V, IOH = –4 µA, IOL = 4 µA VSS2 = –2.9 V, IOL = 4 µA –0.2 V All SEGOUT pins VSS2 + 0.2 –0.2 COM1 to 3 (for 1/3 duty methods) COM1 to 4 (for 1/4 duty methods) VSS2/2 – 0.2 V V VSS2/2 +0.2 V VSS2 + 0.2 V Continued on next page. No. 4365-26/29 LC5852N Continued from preceding page. Parameter Symbol Conditions/Pins min typ max Unit • 1/3 bias—1/3 duty and 1/3 bias—1/4 duty methods Output high level voltage VOH (4) VSS2 = –2.9 V, IOH = –0.4 µA –0.2 Output M1 level voltage VOM1-4 VSS2 = –2.9 V, IOH = –0.4 µA, IOL = 0.4 µA VSS2/2 – 0.2 VSS2/2 +0.2 V Output M2 level voltage VOM2-4 VSS2 = –2.9 V, IOH = –0.4 µA, IOL = 0.4 µA VSS2 – 0.2 VSS2 + 0.2 V Output low level voltage VOL (4) VSS2 = –2.9 V, IOL = 0.4 µA VSS3 + 0.2 V Output high level voltage VOH (5) VSS2 = –2.9 V, IOH = –4 µA Output M1 level voltage VOM1-5 VSS2 = –2.9 V, IOH = –4 µA, IOL = 4 µA Output M2 level voltage VOM2-5 VSS2 = –2.9 V, IOH = –4 µA, IOL = 4 µA Output low level voltage VOL (5) VSS2 = –2.9 V, IOL = 4 µA LCD drive: 1/3 bias methods (halver) VSS1 VSS2 = –2.9 V, C1 to 3 = 0.1 µF (tripler) VSS3 LCD drive: 1/2 bias methods (halver) VSS1 V All SEGOUT pins –0.2 V VSS2/2 – 0.2 VSS2/2 +0.2 V VSS2 – 0.2 VSS2 + 0.2 V VSS3 + 0.2 V fopg = 32.768 kHz, Figure 7 –1.35 V VSS2 = –2.9 V, C1 to 3 = 0.1 µF fopg = 32.768 kHz, Figure 7 –4.1 V VSS2 = –2.9 V, C1 = C2 = 0.1 µF fopg = 32.768 kHz, Figure 4 –1.35 V COM1 to 3 (for 1/3 duty methods) COM1 to 4 (for 1/4 duty methods) • Output voltage • Supply current (when the backup flag is cleared to zero) LCD drive: 1/3 bias methods | IDD | VSS2 = –2.9 V, C1 to 3 = 0.1 µF, Cd = Cg = 20 pF In HALT mode, Cl = 25 kΩ, Figure 7, 32.768 kHz Xtal 0.8 3.0 µA LCD drive: methods other than 1/3 bias | IDD | VSS2 = –2.9 V, C1 = C2 = 0.1 µF, Cd = Cg = 20 pF In HALT mode, Cl = 25kΩ, Figure 4, 32.768 kHz Xtal 0.7 3.0 µA Oscillator start voltage VSS2 | Vstt | VBAK = VSS2, Cd = Cg = 20 pF Cl = 25 kΩ, Figure 5, 32.768 kHz Xtal 1.35 V Oscillator hold voltage VSS2 (when the backup flag is cleared to zero) | VHOLD (1) | VBAK = VSS2/2, Cd = Cg = 20 pF Cl = 25kΩ, Figure 4, 32.768 kHz Xtal 2.6 3.6 V (when the backup flag is cleared to zero) | VHOLD (2) | VBAK = VSS2, Cd = Cg = 20 pF Cl = 25kΩ, Figure 4, 32.768 kHz Xtal 1.3 3.6 V Tstt VBAK = VSS2 = –2.9 V, Cd = Cg = 20 pF Cl = 25kΩ, Figure 5, 32.768 kHz Xtal 10 s 10P External connection 20P OSCOUT Oscillator start time Oscillator correction capacitance Figure 1 Ceramic Oscillator Specifications 8 10 12 pF 16 20 24 pF Figure 2 Crystal Oscillator Specifications (32 kHz or 65 kHz) No. 4365-27/29 LC5852N Figure 3 S1 to S4 and M1 to M4 Input Circuits Figure 4 Power Supply Current and Oscillator Hold Voltage Test Circuit Figure 5 Oscillator Start Voltage, Oscillator Start Time and Frequency Stability Test Circuit Figure 6 Oscillator Start Voltage, Oscillator Start Time, Power Supply Current and Oscillator Hold Voltage Test Circuit Figure 7 Power Supply Current and Oscillator Hold Voltage Test Circuit Figure 8 External Input Specifications Figure 9 Power Supply Current and Oscillator Hold Time Test Circuit No. 4365-28/29 LC5852N ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. No. 4365-29/29