FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16202-2E
32-bit Proprietary Microcontroller
CMOS
FR Family MB91191/192 Series
MB91191R/MB91192/MB91F191A/MB91F192
■ DESCRIPTION
The MB91191/192 series is a single-chip microcontroller using a 32-bit RISC-CPU (FR series) as its core. It
contains peripheral I/O resources suitable for software servo control in applications such as VTRs that require
high-speed CPU processing.
■ FEATURES
CPU
• 32-bit RISC (FR series) , load/store architecture, 5-stage pipeline
• General-purpose registers : 16 × 32-bit
• 16-bit fixed-length instructions (basic instructions) , 1 instruction per cycle
• Includes memory-to-memory transfer, bit manipulation, and barrel shift instructions :
Optimized for embedded applications
• Includes function entry/exit instructions and multiple-register load/store instructions :
Instruction set supports high level languages
• Register interlock function : For efficient assembly language coding
• Branch instructions with delay slots : Reduced overhead for branch operations
• Internal multiplier unit is supported at instruction level
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
• Interrupts (PC and PS saving) : 6 cycles, 16 priority levels
(Continued)
■ PACKAGE
Plastic, LQFP, 120-pin
Plastic, FLGA, 144-pin
(FPT-120P-M05)
(LGA-144P-M02)
MB91191/192 Series
Bus Interface
• 16-bit address output, 8/16-bit data input and output
• Basic bus cycle : 2 clock cycles
• Supports interfaces for various types of memory
• Multiplexed data/address input/output
• Automatic wait cycles : Between 0 and 7 wait cycles can be specified independently for each memory area
• Unused data/address pins can be configured as input/output ports
• Supports little endian mode
Bit Search Module
• Searches, starting from the MSB, for the position of the first 1/0 bit transition in a word. The operation is
performed in one cycle.
Serial I/O
• 3 channels with internal buffer RAM (automatic transfer of up to 128 bytes)
• Independent send and receive buffer mode (automatic transfer of up to 64 bytes)
A/D Converter (Successive Approximation Type)
• 10-bit × 16 channels
• Uses successive approximation conversion method (conversion time : 8.4 µs @ 20 MHz)
• Channel scan function
• Hardware and software conversion start functions
• Internal FIFO (Software conversion : 6 stages, Hardware conversion : 6 stages)
Timers
• 16-bit × 4 channels
• 16-bit timer/counter × 1 channel (with square wave output)
• 8/16-bit timer/counter × 1 channel (with square wave output)
FG input unit
• Incorporates capstan, drum, and reel input circuits
Capture unit
• Internal 24-bit free-run counter (Minimum resolution = 50 ns @ 20 MHz)
• Internal FIFO (Data : 21-bit × 8, Detection : 8-bit × 8)
Programmable pattern generator
• Internal RAM buffer (PPG0 : 256 bytes, PPG1 : 64 bytes)
• Output timing resolution : 800 ns @ 20 MHz
• Includes an A/D converter hardware start function
Realtime timing generator
• RTG : 3 circuits
• Output timing resolution : 400 ns or 800 ns selectable
• Timing output ports : 5 ports
PWM
• 12-bit PWM × 6 channels (rate, multi-type)
• Base frequency = 78.1 kHz or 39.0 kHz (@ 20 MHz) selectable
(Continued)
2
MB91191/192 Series
(Continued)
PWC
• 8-bit PWC × 1 channel (with mask input)
• Measurement resolution : 400 ns @ 20 MHz
General-purpose prescaler
• 10-bit prescaler × 1 channel (with square wave and pulse outputs)
• Dedicated internal oscillator circuit
• Includes load function driven by PPG output
Interrupt control
• External interrupts : 3 inputs
• Key input interrupt : 8 inputs
3
MB91191/192 Series
■ PIN ASSIGNMENT
65
70
75
80
85
60
95
55
100
50
105
45
110
40
115
30
25
20
15
10
120
5
35
P93/PPG02
P94/PPG03
P80/PPG04
P81/PPG05
P82/PPG06
P83/PPG07
P84/PPG08
P85/PPG09
P86/PPG10
P87/PPG11
P40/PPG12
P41/PPG13
P42/PPG14
P43/PPG15
P44/PPG16
P45/PPG17
P46/PPG18
P47
A15
P57
P57
A14
P56
P56
A13
P55
P55
A12
P54
P54
A11
P53
P53
A10
P52
P52
A09
P51
P51
A08
P50
P50
VSS
D31/A07 D31/A15
P37
D30/A06 D30/A14
P36
D29/A05 D29/A13
P35
ALE
P62
WR0
RD
P20
P21
P22
P23
P24
P25
P26
P27
A00/D24
A01/D25
A02/D26
A03/D27
A04/D28
ALE
WR1
WR0
RD
A00/D16
A01/D17
A02/D18
A03/D19
A04/D20
A05/D21
A06/D22
A07/D23
A08/D24
A09/D25
A10/D26
A11/D27
A12/D28
X0
X1
VSS
MD2
MD1
MD0
RST
P70/XOUT
P67/T40
P66/T501
P65
P64
P63
P62
P61
P60
P20
P21
P22
P23
P24
P25
P26
P27
VDD
P30
P31
P32
P33
P34
PA0/AN-8/KEY0
PB7/AN-7
PB6/AN-6
PB5/AN-5
PB4/AN-4
PB3/AN-3
PB2/AN-2
PB1/AN-1
PB0/AN-0
AVDD
AVRH
AVSS
VSS
P17/RTG4
P16/RTG3
P15/RTG2
P14/RTG1
P13/RTG0
P12/EC5/INT1
P11/EC4/INT0
P10/PMSK
P07/EXI2/PMI
P06/EXI1
P05/EXI0
P04/CFG
P03/DFG
P02/DPG
P01/RFG0
P00/RFG1
VDD
90
PA1/AN-9/KEY1
PA2/AN-A/KEY2
PA3/AN-B/KEY3
PA4/AN-C/KEY4
PA5/AN-D/KEY5
PA6/AN-E/KEY6
PA7/AN-F/KEY7
PD0/SI2
PD1/SO2
PD2/SCK2
PD3/SI1/INT2
PD4/SO1
PD5/SCK1
PD6/SCS0
PD7/SI0
PC0/SO0
PC1/SCK0
PC2/PWM5/SCS1
PC3/PWM4/SCS2
PC4/PWM3
PC5/PWM2
PC6/PWM1
PC7/PWM0
VSS
OSCI/PCK
OSCO
VDD
P90/P0
P91/PPG00
P92/PPG01
(TOP VIEW)
8-bit MPX mode
16-bit MPX mode
(FPT-120P-M05)
(Continued)
4
MB91191/192 Series
(Continued)
59 56 53 50
47 44 41
38 35 32
P94 P82 P85 P40 P43 P46 P56 P53 P50 P36
58 55 52 49
46 45 42
39 36 33
P80 P83 P86 P41 P44 P45 P57 P54 P51 P37
62
P91
63 61
60 57 54 51
48 43 40
37 34 31
P90 P92 P93 P81 P84 P87 P42 P47 P55 P52 VSS P35
65
66 64
OSCO OSCI VDD
30
P34
28
29
P32 P33
68
PC7
69 67
PC6 VSS
27
P31
25
26
VDD P30
71
PC4
72 70
PC3 PC5
24
P27
22
23
P25 P26
74
PC1
75 73
PC0 PC2
21
P24
19
20
P22 P23
77
PD6
76 78
PD7 PD5
18
P21
16
17
P60 P20
80
PD3
79 81
PD4 PD2
13
P63
15
14
P61 P62
83
PD0
82 84
PD1 PA7
10
P66
12
11
P64 P65
86
PA5
85 87
PA6 PA4
7
9
8
RST P67 P70
89
PA2
88 90
PA3 PA1
4
6
5
MD2 MD0 MD1
Top View
91
94 97 100 103
PA0 PB5 PB2 AVDD VSS
108 111 114 117 120 1
P13 P10 P05 P02 VDD X0
3
2
VSS X1
93
96 99 102 105 106 109 112 115 118
PB6 PB3 PB0 AVSS P16 P15 P12 P07 P04 P01
92
95 98 101 104 107 110 113 116 119
PB7 PB4 PB1 AVRH P17 P14 P11 P06 P03 P00
(LGA-144P-M02)
Note : The FLGA-144 package is not supplied for the MB91191 series.
It is supplied only for the MB91192 series.
5
MB91191/192 Series
■ PIN DESCRIPTIONS
Pin No.
Pin Name
1
X0
(I)
2
X1
(O)
3
VSS
4
MD2
5
MD1
6
MD0
7
Circuit
Type
Function
A
Crystal oscillator pins
VSS pin
B
Operation mode setting pins
CMOS Schmitt inputs
RST
B
Reset input pin. CMOS Schmitt input.
8
P70/XOUT
C
Shared pin with clock output (X0/2, PCK/2) . CMOS input.
9
P67/T40
Shared pin with timer 4 square wave output. CMOS input.
10
P66/T501
Shared pin with timer 5 square wave output. CMOS input.
11
P65
General-purpose I/O port. CMOS input.
12
P64
13
P63/ALE/ALE
14
P62/P62/WR1
Shared pin with write strobe output 1. CMOS input.
15
P61/WR0/WR0
Shared pin with write strobe output 0. CMOS input.
16
P60/RD/RD
Shared pin with read strobe output. CMOS input.
17
P20/P20/D16 : A00
18
P21/P21/D17 : A01
19
P22/P22/D18 : A02
20
P23/P23/D19 : A03
21
P24/P24/D20 : A04
22
P25/P25/D21 : A05
23
P26/P26/D22 : A06
24
P27/P27/D23 : A07
25
VDD
26
P30/D24 : A00/D24 : A08
27
P31/D25 : A01/D25 : A09
28
P32/D26 : A02/D26 : A10
29
P33/D27 : A03/D27 : A11
30
P34/D28 : A04/D28 : A12
31
P35/D29 : A05/D29 : A13
32
P36/D30 : A06/D30 : A14
33
P37/D31 : A07/D31 : A15
34
VSS
C
General-purpose I/O port. CMOS input.
Shared pin with address strobe output. CMOS input.
C
General-purpose I/O ports.
CMOS inputs.
Power supply pin
C
Shared external bus pins and high-current I/O ports.
CMOS inputs.
VSS pin
(Continued)
6
MB91191/192 Series
Pin No.
Pin Name
35
P50/A08/P50
36
P51/A09/P51
37
P52/A10/P52
38
P53/A11/P53
39
P54/A12/P54
40
P55/A13/P55
41
P56/A14/P56
42
P57/A15/P57
43
P47
44
P46/PPG18
45
P45/PPG17
46
P44/PPG16
47
P43/PPG15
48
P42/PPG14
49
P41/PPG13
50
P40/PPG12
51
P87/PPG11
52
P86/PPG10
53
P85/PPG09
54
P84/PPG08
55
P83/PPG07
56
P82/PPG06
57
P81/PPG05
58
P80/PPG04
59
P94/PPG03
60
P93/PPG02
61
P92/PPG01
62
P91/PPG00
63
P90/P0
64
VDD
65
OSCO
66
OSCI/PCK
67
VSS
Circuit
Type
C
Function
Shared external bus pins and high-current I/O ports.
CMOS inputs.
General-purpose I/O port. CMOS input.
C
Shared pins with PPG outputs.
CMOS inputs.
C
Shared pins with PPG outputs.
CMOS inputs.
C
Shared pins with PPG outputs.
CMOS inputs.
C
Shared pins with PPG outputs.
CMOS inputs.
Shared pin with general-purpose prescaler output. CMOS input.
(O)
(I)
Power supply pin
A
Crystal oscillator pins for dedicated general-purpose prescaler
oscillation.
VSS pin
(Continued)
7
MB91191/192 Series
Pin No.
Pin Name
Circuit
Type
Function
68
PC7/PWM0
69
PC6/PWM1
70
PC5/PWM2
71
PC4/PWM3
72
PC3/PWM4/SCS2
73
PC2/PWM5/SCS1
74
PC1/SCK0
75
PC0/SO0
76
PD7/SI0
77
PD6/SCS0
78
PD5/SCK1
79
PD4/SO1
80
PD3/SI1/INT2
81
PD2/SCK2
82
PD1/SO2
C
Shared pin with serial 2 serial output. CMOS input.
83
PD0/SI2
F
Shared pin with serial 2 serial input.
CMOS Schmitt input.
84
PA7/AN-F/KEY7
85
PA6/AN-E/KEY6
86
PA5/AN-D/KEY5
87
PA4/AN-C/KEY4
88
PA3/AN-B/KEY3
E
Shared pins with analog inputs and key inputs.
CMOS Schmitt inputs
89
PA2/AN-A/KEY2
90
PA1/AN-9/KEY1
91
PA0/AN-8/KEY0
C
Shared pins with PWM outputs.
CMOS inputs.
Shared pin with PWM output and serial 2 chip select.
CMOS Schmitt input.
F
Shared pin with PWM output and serial 1 chip select.
CMOS Schmitt input.
Shared pin with serial 0 shift clock.
CMOS Schmitt input.
C
Shared pin with serial 0 serial output. CMOS input.
Shared pin with serial 0 serial input.
CMOS Schmitt input.
F
Shared pin with serial 0 chip select input.
CMOS Schmitt input.
Shared pin with serial 1 shift clock.
CMOS Schmitt input.
C
F
Shared pin with serial 1 serial output. CMOS input.
Shared pin with serial 1 serial input and external interrupt 2.
CMOS Schmitt input.
Shared pin with serial 2 shift clock.
CMOS Schmitt input.
(Continued)
8
MB91191/192 Series
(Continued)
Pin No.
Pin Name
92
PB7/AN-7
93
PB6/AN-6
94
PB5/AN-5
95
PB4/AN-4
96
PB3/AN-3
97
PB2/AN-2
98
PB1/AN-1
99
PB0/AN-0
100
Circuit
Type
Function
D
Shared pins with analog inputs.
CMOS Schmitt inputs.
AVDD
A/D converter power supply pin
101
AVRH
A/D converter reference power supply pin
102
AVSS
A/D converter VSS pin
103
VSS
VSS pin
104
P17/RTG4
105
P16/RTG3
106
P15/RTG2
C
Shared pins with RTG outputs.
CMOS inputs.
107
P14/RTG1
108
P13/RTG0
109
P12/EC5/INT1
110
P11/EC4/INT0
111
P10/PMSK
Shared pin with PWC mask input. CMOS Schmitt input.
112
P07/EXI2/PMI
Shared pin with external capture input and PWC input.
CMOS Schmitt input.
113
P06/EXI1
114
P05/EXI0
115
P04/CFG
116
P03/DFG
Shared pin with drum FG input. CMOS Schmitt input.
117
P02/DPG
Shared pin with drum pulse input. CMOS Schmitt input.
118
P01/RFG0
119
P00/RFG1
Shared pins with reel FG inputs.
CMOS Schmitt inputs.
120
VDD
Shared pin with timer 5 clock input and external interrupt input.
CMOS Schmitt input.
F
Shared pin with timer 4 clock input and external interrupt input.
CMOS Schmitt input.
Shared pin with external capture input.
CMOS Schmitt input.
F
Shared pin with capstan FG input. CMOS Schmitt input.
Power supply pin
9
MB91191/192 Series
■ I/O CIRCUITS
Type
Circuit
Remarks
• Oscillation feedback
resistor : 1 MΩ approx.
X0,OSCI
Clock input
A
Standby control signal
X1,OSCO
• CMOS Schmitt input
B
Input
Output data
DC test
• CMOS level output
• CMOS input
No standby control
DC test
C
Input
Standby control signal = 1 (fixed)
Output data
DC test
• CMOS level output
• CMOS input
with input control
• Analog input
DC test
D
Analog input
CH selection
Digital input
Input control
(Continued)
10
MB91191/192 Series
(Continued)
Type
Circuit
Remarks
Input data
DC test
• CMOS level output
• CMOS Schmitt input
with input control
• Analog input
DC test
E
Analog input
CH selection
Digital input
Input control
Output data
DC test
• CMOS level output
• CMOS Schmitt input
No standby control
DC test
F
Input
Standby control signal = 1 (fixed)
Output data
DC test
H
• CMOS level output
• CMOS Schmitt input
No standby control
DC test
Input
11
MB91191/192 Series
■ BLOCK DIAGRAM
RAM 256 byte PPG0
P37/D31
FR20 CPU core
D-bus
I-bus
D-bus
Bit search
C-bus
RAM 2 KB
D-bus
MB91191R :ROM 254 KB
MB91192 :ROM 384 KB
MB91F191A :FLASH 254 KB
MB91F192 :FLASH 384 KB
Serial
ch 0
RAM
128 byte
Serial
ch 1
RAM
128 byte
Serial
ch 2
12-bit PWM00-02
8/16-bit timer
Interrupt
controller
External interrupts
16-bit timer 4
Port 0
24-bit
FRC
RFG1
OSC
C-unit
OSCI
OSCO
OSC
10-bit programmable
prescaler
PD0/SI2
PD1/SO2
PD2/SCK2
PD3/SI1/INT2
PD4/SO1
PD5/SCK1
PD6/SCS0
PD7/SI0
PC0/S00
PC1/SCK0
PC2/PWM5/SCS1
PC3/PWM4/SCS2
PC4/PWM3
PC5/PWM2
PC6/PWM1
PC7/PWM0
INT2 to INT0 (from port 1, D)
External interrupts
(key inputs)
RFG0
X0
X1
P87/PPG11
P86/PPG10
P85/PPG09
P84/PPG08
P83/PPG07
P82/PPG06
P81/PPG05
P80/PPG04
P94/PPG03
P93/PPG02
P92/PPG01
P91/PPG00
P90/P0
RTG4 to RTG0 (to port 1)
CFG
DFG
P47
P46/PPG18
P45/PPG17
P44/PPG16
P43/PPG15
P42/PPG14
P41/PPG13
P40/PPG12
16-bit RTG0-2
8-bit PWC
P00/RFG1
12
RAM
128 byte
12-bit PWM10-12
P11/EC4/INT0
P10/PMSK
P07/EXI2/PMI
P06/EXI1
P05/EXI0
P04/CFG
P03/DFG
P02/DPG
P01/RFG0
R-bus
16-bit timers 0 to 3
Port 1
P17/RTG4
P16/RTG3
P15/RTG2
P14/RTG1
P13/RTG0
P12/EC5/INT1
Port 7
External bus control
P70/XOUT
MB91191R :RAM 6 KB
MB91192 :RAM 8 KB
MB91F191A :RAM 6 KB
MB91F192 :RAM 8 KB
10-bit A/DC
FIFO
29-bit × 8
FIFO
FIFO
(software) (hardware)
Port A/B
P50/A08
P60/RD
P61/WR0
P62/WR1
P63/ALE
P64
P65
P66/T501
P67/T40
Port 6
Port 5
P20/D16
P57/A15
to
RAM 64 byte PPG1
Port 8/9
to
I-bus
Port C/D
Port 2/3
to
P30/D24
P27/D23
Port 4
Mode control
MD0
MD1
MD2
RST
PA7/AN-F/KEY7
PA6/AN-E/KEY6
PA5/AN-D/KEY5
PA4/AN-C/KEY4
PA3/AN-B/KEY3
PA2/AN-A/KEY2
PA1/AN-9/KEY1
PA0/AN-8/KEY0
PB7/AN-7
PB6/AN-6
PB5/AN-5
PB4/AN-4
PB3/AN-3
PB2/AN-2
PB1/AN-1
PB0/AN-0
MB91191/192 Series
(Bus names)
• I bus : 16-bit bus for internal instructions. As the FR family of CPUs use the Harvard architecture, instructions
and data use separate buses. A bus converter is connected to the I bus.
• D bus : Internal 32-bit data bus. The internal peripherals are connected to the D bus.
• C bus : Internal multiplexed bus. Connected to the I and D buses via a switch. An external interface module
is connected to the C bus. Data and instructions are multiplexed on the external data bus.
• R bus : Internal 16-bit data bus. The R bus connects to the D bus via an adapter. The I/O, clock oscillator, and
interrupt controller are connected to the R bus. As the R bus is only 16 bits wide, address and data
are multiplexed on the bus and therefore multiple cycles are required when the CPU accesses these
resources.
13
MB91191/192 Series
■ MEMORY MAP
00000000H
to
000001FFH
00000200H
to
000002FFH
00000300H
to
0000037FH
00000380H
to
000003BFH
000003C0H
to
00000000H
I/O area
I/O area
PPG0 Data RAM area
256 bytes
PPG0 Data RAM area
256 bytes
SIO0 Data RAM area
128 bytes
Direct
access
area
PPG1 Data RAM area
64 bytes
PPG1 Data RAM area
64 bytes
I/O area
I/O area
000003FFH
00000400H
to
000007FFH
00000800H
to
00000FFFH
00001000H
to
0000107FH
00001080H
to
000010FFH
00001100H
to
0000E7FFH
0000E800H
to
0000FFFFH
00010000H
SIO0 Data RAM area
128 bytes
I/O area
I/O area
Access inhibited
Access inhibited
SIO1 Data RAM area
128 bytes
SIO1 Data RAM area
128 bytes
SIO2 Data RAM area
128 bytes
SIO2 Data RAM area
128 bytes
Access inhibited
Access inhibited
Internal RAM area
8 Kbytes
Internal RAM area
6 Kbytes
Internal RAM area
2 Kbytes
Access inhibited
Access inhibited
000BFFFFH
000C0000H
to
000C07FFH
000C0800H
to
000FFFFBH
000FFFFCH
00100000H
to
FFFFFFFFH
Internal RAM area
2 Kbytes
Internal ROM area
254 Kbytes
Reset vector
External extended area
to
000002FFH
00000300H
to
0000037FH
00000380H
to
000003BFH
000003C0H
to
000003FFH
00000400H
to
000007FFH
00000800H
to
00000FFFH
00001000H
to
0000107FH
00001080H
to
000010FFH
00001100H
to
0000DFFFH
0000E000H
Access inhibited
to
to
000001FFH
00000200H
Internal ROM area
384 Kbytes
1 KB
Initial vector area
Reset vector
External extended area
to
0000FFFFH
00010000H
to
0007FFFFH
00080000H
to
000807FFH
00080800H
to
0009FFFFH
000A0000H
to
000FFFFBH
000FFFFCH
00100000H
to
FFFFFFFFH
MB91191R
MB91192
Note : The single chip mode does not allow access to the external extended area.
For access to the external extended area, use the mode register to select
the internal ROM external bus mode.
14
MB91191/192 Series
■ FLASH MEMORY MAP AND SECTOR CONFIGURATION
Flash memory is address-mapped differently between when accessed from the FR-CPU and when accessed
from the ROM programmer.* Shown below is address mapping at access from the CPU.
* : While the on-board flash memory uses the little endian format, the FR-CPU interface circuit converts data into
big endian. As this conversion function does not work during access from the ROM programmer, address mapping
is different from that in CPU mode.
• MB91F191A
MSB side 16 bit
31
00000000H
000007C0H
LSB side 16 bit
16
000C0800H
15
0
000C0801H 000C0802H
000C0803H
Status resistor
SA5 (63 Kbyte)
SA0 (63 Kbyte)
000C0000H Internal RAM area
000C0800H
Flash Memory
area
000FFFFFH
000E0000H
000E0001H 000E0002H
SA6 (32 Kbyte)
SA1 (32 Kbyte)
000F0001H
000F0002H
000F4001H
000F4000H
SA3 (8 Kbyte)
000F8000H
000F8001H
000F4002H
000F8002H
000F0000H
SA2 (8 Kbyte)
000FFFFCH
• MB91F192
000FFFFDH 000FFFFEH
MSB side 16 bit
31
000007C0H
000FFFFFH
LSB side 16 bit
16
000A0000H
15
000A0001H
0
000A0002H
000A0003H
Status resistor
SA0 (64 Kbyte)
00080000H
000F4003H
000F8003H
SA8 (8 Kbyte)
Sector Configuration (SA = Sector address)
Memory Map
00000000H
000F0003H
SA7 (8 Kbyte)
SA9 (16 Kbyte)
SA4 (16 Kbyte)
FFFFFFFFH
000E0003H
SA6 (64 Kbyte)
Internal RAM area
00080800H
000A0000H
000C0000H
Flash Memory
area
000C0001H
000C0003H
000C0002H
SA1 (64 Kbyte)
SA7 (64 Kbyte)
000FFFFFH
000E0000H
000E0001H
000E0002H
SA2 (32 Kbyte)
SA8 (32 Kbyte)
000F0000H
000F0001H
SA3 (8 Kbyte)
000F4000H
000F4001H
000F0002H
000F8000H
000F8002H
SA4 (8 Kbyte)
000F8001H
000F4002H
SA5 (16 Kbyte)
000FFFFCH
FFFFFFFFH
Memory Map
000E0003H
000F0003H
SA9 (8 Kbyte)
000F4003H
SA10 (8 Kbyte)
000F8003H
SA11 (16 Kbyte)
000FFFFDH 000FFFFEH
Sector Configuration (SA = Sector address)
000FFFFFH
15
MB91191/192 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
(VSS = AVSS = 0 V)
Symbol
Rating
Unit
Remarks
Min
Max
VDD
VSS − 0.3
VSS + 3.5
V
Analog power supply voltage
AVDD
VSS − 0.3
VSS + 3.5
V
*1
Analog reference voltage
AVRH
VSS − 0.3
VSS + 3.5
V
*1
Input voltage
VI
VSS − 0.3
VSS + 3.5
V
*2
Output voltage
VO
VSS − 0.3
VSS + 3.5
V
*2
“L” level maximum output current
IOL
10
mA
*3
“L” level average output current
IOLAV
8
mA
*4
“L” level total maximum output current
ΣIOL
100
mA
ΣIOLAV
50
mA
*5
IOH
−10
mA
*3
“H” level average output current
IOHAV
−4
mA
*4
“H” level total maximum output current
ΣIOH
−50
mA
“H” level total average output current
ΣIOHAV
−20
mA
Power consumption
PD
500
mW
Operating temperature
TA
−20
+70
°C
Tstg
−55
+150
°C
Power supply voltage
“L” level total average output current
“H” level maximum output current
Storage temperature
*5
*1 : Care must be taken that AVDD and AVRH do not exceed VDD + 0.3 V such as when turning on the device.
Also care must be taken that AVRH does not exceed AVDD.
*2 : VI and VO may not exceed VDD + 0.3 V.
*3 : The maximum output current is the peak value for a single pin.
*4 : The average output current is the average current for a single pin over a period of 100 ms.
*5 : The total average output current is the average current for all pins over a period of 100 ms.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
16
MB91191/192 Series
2. Recommended Operating Conditions
Parameter
Power supply voltage
Symbol
VDD
(VSS = AVSS = 0 V)
Value
Min
Max
2.7
3.3
2.0
3.3
Unit
Normal operation
V
Analog power supply voltage
AVDD
VSS − 0.3
VDD + 0.2
V
Analog reference voltage
AVRH
AVSS
AVDD
V
TA
−20
70
°C
Operating temperature
Remarks
Maintaining RAM state in
stop mode
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
17
MB91191/192 Series
3. DC Characteristics
Parameter
VIH
“H” level
input voltage
VIHS
VIHM
VIL
“L” level
input
voltage
“H” level
output
voltage
“L” level
output
voltage
Input leak
current
Pin Name
Symbol
VILS
*3
*1
*2
0.7 VDD
VDD + 0.3
V
VDD − 0.4
VDD + 0.3
V
0.8 VDD
VDD + 0.3
V
MD2 to MD0
VDD
VDD + 0.3
V
*3
VSS − 0.3
0.2 VDD
V
*1
VSS − 0.3
VSS + 0.4
V
VSS − 0.3
0.2 VDD
V
VSS − 0.3
VSS
V
V
*2
VILM
MD2 to MD0
VOH1
*4
VDD = 3.0 V,
IOH = −4.0 mA
2.4
2.4
V
MB91191R
VOH2
*5, *6
VDD = 3.0 V,
IOH = −8.0 mA
2.4
V
MB91F191A
2.4
V
MB91191R
VOL1
*4
0.6
V
VOL2
*5, *6
0.6
V
VOL3
*4, *5, *6
VDD = 3.0 V,
IOL = 4.0 mA
VDD = 3.0 V,
IOL = 8.0 mA
VDD = 3.0 V,
IOL = 1.0 mA
0.3
V
VDD = 3.0 V,
VSS < VI < VDD
±1
±5
µA
±8
±20
µA
50.1
60
mA MB91F191A
16
25
mA MB91191R
24
36
mA MB91F191A
13
18
mA MB91191R
1
240
µA MB91F191A
10
300
µA MB91191R
ILI1
*2
ILIX
X0, OSCI
VDD = 3.0 V, *7
IDD
Power
supply
current
(VDD = 3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Value
Condition
Unit Remarks
Min
Typ
Max
IDDS
IDDH
VDD
VDD = 3.0 V, *8
VDD = 3.0 V,
TA = 25 °C, *9
MB91F191A
MB91191R
Other than VDD, VSS,
Input
10
pF
CIN
AVDD, AVSS, and AVRH
capacitance
*1 : X0, X1, OSCI, OSCO
*2 : RST, PC3 to PC1, PD6, PD5, PD3, PD2, PA7 to PA0, P12 to P10, P07 to P00, PD7, PD0
*3 : Inputs other than *1, *2, MD2 to MD0
*4 : P07 to P00, P17 to P10, P27 to P20, P47 to P40, P67 to P60, P70, P87 to P80, P94 to P90, PA7 to PA0,
PB7 to PB0, PC7 to PC2, PD7, PD6, PD3, PD0
*5 : P37 to P30, P57 to P50
*6 : PD5, PD4, PD2, PD1, PC1, PC0
*7 : Operating current for X0 = 20 MHz, OSCI = VSS (fixed) , all port outputs = low, gear selection : CPU = 10 MHz,
peripherals = 20 MHz
*8 : Operating current in sleep mode for X0 = 20 MHz, OSCI = VSS (fixed), all port outputs = low, gear selection :
CPU = 10 MHz, peripherals = 20 MHz
*9 : Operating current in stop mode for X0 = 20 MHz, OSCI = VSS (fixed) , all port outputs = low, gear selection :
CPU = 10 MHz, peripherals = 20 MHz
18
MB91191/192 Series
4. AC Characteristics
(1) Clock Timings
Parameter
(VDD = 3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Value
Condition
Unit
Remarks
Min
Max
Symbol
Clock frequency
fC
10
20
MHz
Clock cycle time
tC
50
100
ns
Frequency fluctuation* (PLL locked)
∆r
10
%
20
ns
8
ns
5
20
MHz
10
20
MHz
50
200
ns
50
100
ns
PWH
Input clock pulse width
PWL
tCR
Input clock rise/fall time
tCF
Internal operating clock CPU
frequency
Peripherals
Internal operating clock CPU
cycle time
Peripherals
fCP
When wait
controller set to
1 wait cycle
fCPP
tCP
tCPP
* : The frequency fluctuation value is the maximum percentage deviation from the preset center frequency when
using the multiplier (when PLL is locked) .
+α
|α|
∆f =
f0
× 100 (%)
+
Center frequency f0
−α
−
tc
PWH
PWL
Power supply voltage (V)
tcf
3.3
tcr
Guaranteed operation range
fcpp
2.7
fcp
10 M 20 M
Frequency (Hz)
19
MB91191/192 Series
The figure below shows the relationship between the X0 input and the internal clock based on the GCR (Gear
Control Register) , CHC, CCK1, and CCK0 bit settings.
X0 input
Source oscillation × 1
(CHC bit in GCR = 0)
(a) gear × 1
Internal clock
tCYC
CCK1/0:00
(b) gear × 1/2
Internal clock
tCYC
CCK1/0:01
(c) gear × 1/4
tCYC
Internal clock
CCK1/0:10
(d) gear × 1/8
tCYC
Internal clock
CCK1/0:11
Source oscillation × 1/2
(CHC bit in GCR = 1)
(a) gear x 1
Internal clock
tCYC
CCK1/0:00
(b) gear x 1/2
Internal clock
tCYC
CCK1/0:01
(c) gear x 1/4
Internal clock
tCYC
CCK1/0:10
(d) gear x 1/8
Internal clock
tCYC
CCK1/0:11
Where tCYCH is the H level width of the internal clock and tCYCL is the L level width.
For example, when set to source oscillation × 1/2, gear × 1/4 and X0 input frequency = 20 MHz : tCYC = 400 ns,
tCYCH = 350 ns, tCYCL = 50 ns
20
MB91191/192 Series
(2) Multiplex Bus Read/Write Operation
Parameter
Symbol
(VDD = +3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Value
CondiRePin Name
Unit
tion
marks
Min
Typ
Max
ALE pulse width
tEHEL
ALE
Address delay time
tEHAV
Address clear time
tEHAX
A15 to A0,
D31 to D16
Data delay time
tELDV
D31 to D16
RD delay time
tELRL
RD pulse width
tRLRH
WR0, WR1 delay time
tELWL
WR0, WR1 pulse width
tWLWH
Data setup → RD ↑ time
tDSRH
RD ↑→ Data hold time
tRHDX
RD
WR0, WR1
RD,
D31 to D16
tCYC − 10
ns
tCYCH − 15
tCYCH
tCYCH + 15
ns
*2
tCYCL − 2
tCYCL
tCYCL + 10
ns
*2
tCYCL + 26
ns
*2
tCYC − 11
tCYC
tCYC + 11
ns
tCYC − 11
tCYC
tCYC + 11
ns
tCYC − 11
tCYC
tCYC + 11
ns
tCYC − 11
tCYC
tCYC + 11
ns
15
ns
0
ns
*1
*1
*1 : When the bus is delayed by automatic wait insertion, add (tCYC × number of wait cycles) to this value.
*2 : This value is for gear setting = ×1
For the value for gear settings 1/2, 1/4, and 1/8, substitute 1/2, 1/4, and 1/8 respectively for n in the formula below.
Formula : tCYCH = (1 − n / 2) × tCYC
tCYCL = (n / 2) × tCYC
Internal
clock
tEHEL
ALE
tEHAV
tELAX
tDSRH
tRHDX
Read time
D31 to D16
MPX bus
RD
tELRL
Write time
D31 to D16
MPX bus
tRLRH
tWHDX
tELDV
WR0 , WR1
tELWL
tWLWH
A15 to A08
When not
multiplexed
21
MB91191/192 Series
(3) Reset Input Ratings
Parameter
Reset input time
Symbol
Pin Name
tRSTL
RST
(VDD = 3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Value
Unit
Remarks
Min
Max
5 tCP
ns
tRSTL
RST
0.2 VDD
(4) Power-On Reset
Paramete
(VDD = 3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Value
Pin Name
Unit
Remarks
Min
Max
Symbol
Power supply rise time
Power supply cutoff time
tR
VDD
tOFF
20
ms
2
ms
tOFF
tR
2.7 V
VDD
0.2 V
Sudden changes in the power supply voltage may cause a power-on reset.
The recommended practice if you wish to change the power supply voltage while the device is operating
is to raise the voltage smoothly.
3.0 V
VDD
2.0 V
Maintain RAM data
Recommended rate of voltage
rise is 50 mV/ms or less.
VSS
VDD
RST
tRSTL
22
When turning on the power, start with
the RST pin in the "L" level state and
allow a time of tRSTL after reaching
the VDD power supply level before
changing the pin to the "H" level.
MB91191/192 Series
(5) Serial I/O (CH0 to 2)
Symbol
Parameter
(VDD = +3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Value
Condition
Unit
Remarks
Min
Max
8 tCPP
ns
−10
50
ns
50
ns
tSHIX
50
ns
Serial clock “H” pulse width
tSHSL
4 tCPP − 10
ns
Serial clock “L” pulse width
tSLSH
4 tCPP − 10
ns
SCK ↓ → SO delay time
tSLOV
0
50
ns
Valid SI → SCK ↑
tIVSH
50
ns
SCK ↑ → valid SI hold time
tSHIX
50
ns
Serial busy time
tBUSY
6 tCPP
ns
SCS ↓ → SCK, SO delay time
tCLZO
50
ns
SCS ↓ → SCK input mask time
tCLSL
3 tCPP
ns
SCS ↓ → SCK, SO Hi-Z time
tCHOZ
50
ns
Serial clock cycle time
tSCYC
SCK ↓ → SO delay time
tSLOV
Valid SI → SCK ↑
tIVSH
SCK ↑ → valid SI hold time
Internal clock
External clock
• Internal shift clock mode
tSCYC
SCK
tSLOV
SO
SI
tIVSH
tSHIX
• External shift clock mode
tSLSH
tCLZO
tSHSL
tBUSY
tCHOZ
SCK
tSLOV
SO
SI
tIVSH
tSHIX
SCS
tCLSL
23
MB91191/192 Series
(6) FG Pulse Input
Parameter
(VDD = 3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Value
Pin Name
Unit
Remarks
Min
Max
Symbol
Servo input “H” pulse width
tSPWH
Servo input “L” pulse width
tSPWL
CFG, DFG, DPG,
RFG0, RFG1,
EXI0 to EXI2
tC + 50
ns
tC + 50
ns
Note : tC is the clock cycle time of the X0 and X1 pin oscillation.
CFG
DFG, DPG
RFG0, RFG1
EXI0 to EXI2
tSPWH
tSPWL
tf
(7) Timer External Clock Input
Parameter
Symbol
Timer 4 input “H” pulse width
tECWH
Timer 4 input “L” pulse width
tECWL
Timer 5 input “H” pulse width
tECWH
Timer 5 input “L” pulse width
tECWL
EC4,
EC5
(VDD = +3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Value
Pin Name
Unit
Remarks
Min
Max
EC4
EC5
tECWH
4 tC + 50
ns
4 tC + 50
ns
4 tCPP
ns
4 tCPP
ns
tECWL
tf
24
tr
tr
MB91191/192 Series
(8) General-Purpose Prescaler
Parameter
Symbol
PCK input clock frequency
fCP
PCK input “H” pulse width
tSPWH
PCK input “L” pulse width
tSPWL
PCK input
Fall time
tf
Rise time
tr
PO output delay time
(VDD = 3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Value
Pin Name
Unit
Remarks
Min
Max
tPOPI
12
MHz
33
ns
33
ns
PCK
100
ns
PO
80
ns
PCK
tSPWH
tf
tSPWL
tr
PCK
tPOPI
PO
25
MB91191/192 Series
5. Electrical Characteristics for the A/D Converter
(VDD = 3.0 V + 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Value
Condition
Unit Remarks
Min
Typ
Max
Symbol
Pin
Name
Resolution
10
bit
Conversion time
8.4
µs
Total error
±4.0
LSB
Linearity error
±3.5
LSB
Differential linearity error
±2.0
LSB
Zero transition error
VOT
AVSS −
1.5
AVSS +
0.5
AVSS +
2.5
LSB
Full-scale transition error
VFST
AVRH −
5.5
AVRH −
1.5
AVRH +
0.5
LSB
Analog input current
IAIN
AN-0 to
AN-F
0.1
10
µA
Analog input voltage
VAIN
AN-0 to
AN-F
AVSS
AVRH
V
Reference voltage
AVRH
AVRH
AVDD
V
3.0
mA
5.0
µA
100
µA
10
µA
4
LSB
Parameter
Power
supply
current
Reference
voltage
supply
current
During
conversion
IA
Conversion halted
IAH
During
conversion
IR
Conversion halted
IRH
Variation between
channels
AN-0 to
AN-F VDD = AVDD = 3.0 V,
AN-0 to AVRH = 3.0 V
AN-F
AVDD
AVRH
VDD = AVDD = 3.0 V,
AVRH = 3.0 V
AN-0 to
AN-F
VDD = AVDD = 3.0 V
VDD = AVDD = 3.0 V,
AVRH = 3.0 V
Notes : • The relative error increases as |AVRH| becomes smaller.
• Ensure that the output impedance of the external circuit connected to the analog input meets the following
condition :
Output impedance of external circuit < 7 kΩ (approx.)
If the output impedance of the external circuit is too high, the analog voltage sampling time may be too
short. (Sampling time = 6.4 µs for a 20 MHz machine clock)
26
MB91191/192 Series
6. Flash Memory Erase and Programming performance
Parameter
Condition
Sector erase time
Chip erase time
TA = +25 °C,
VCC = 3.0 V
Half word
(16 bit width)
programming time
Value
Min
Typ
Max
1
15
10
Unit
Remarks
s
Excludes 00H programming prior
erasure
s
MB91F191A Excludes 00H
programming prior
MB91F192 erasure
12
16
3,600
µs
Erase/Program
cycle
10,000
cycle
Data holding time
100,000
h
Excludes system-level overhead
27
MB91191/192 Series
7. A/D Converter Glossary
• Resolution : The change in analog voltage that can be recognized by the A/D converter.
• Linearity error
The deviation between the actual conversion characteristics and the line linking the zero transition point
(“00 0000 0000B” ←→ “00 0000 0001B”) and the full scale transition point (“11 1111 1110B” ←→ “11 1111
1111B”) .
• Differential linearity error
The variation from the ideal input voltage required to change the output code by 1 LSB.
• Total error
The total error is the difference between the actual value and the theoretical value.
Includes the zero transition error, full-scale transition error and linearity error.
Total Error
3FF
3FE
Digital Output
3FD
1.5 LSB’
Actual conversion
characteristic
{1 LSB’ × (N − 1) + 0.5 LSB’}
004
VNT
(Measured value)
003
Actual conversion
characteristic
002
Theoretical characteristic
001
0.5 LSB’
AVSS
Analog Input
AVRH − AVSS
[V]
1024
Total error for digital output N = VNT − {1 LSB’ × (N − 1) + 0.5 LSB’}
1 LSB’
1 LSB’ (Theoretical) =
VOT’ (Theoretical) = AVSS + 0.5 LSB’ [V]
VFST’ (Theoretical) = AVRH − 1.5 LSB’ [V]
VNT : Voltage at which digital output changes from (N + 1) to N
28
AVRH
MB91191/192 Series
Differential Linearity Error
Linearity Error
3FF
Actual conversion characteristic
N+1
{1 LSB × (N − 1) + VoT’}
VFST
(Measured
value)
Digital Output
3FD
004
VNT
(Measured
value)
003
Digital Output
3FE
Actual conversion characteristic
Theoretical characteristic
N
N−1
Actual conversion
characteristic
Theoretical characteristic
002
N−2
001
VOT (Measured value)
AVSS
Linearity error for
=
digital output N
Analog Input
AVRH
VNT − {1 LSB × (N − 1) + VOT}
1 LSB’
Differential linearity error V (N+1) T − VNT
=
for digital output N
1 LSB’
AVSS
VFST
(Measured
VNT
value)
(Measured value)
Actual conversion characteristic
Analog Input
AVRH
[LSB]
− 1 LSB [LSB]
VOT’ (Theoretical) = VFST − VOT [V]
1022
VOT : Voltage at which digital output changes from (000) H to (001) H.
VFST : Voltage at which digital output changes from (3FE) H to (3FF) H.
29
MB91191/192 Series
■ ORDERING INFOMATION
Part No.
30
Package
MB91191RPFF
MB91192PFF
MB91F191APFF
MB91F192PFF
Plastic LQFP, 120-pin
(FPT-120P-M05)
MB91192LGA
MB91F192LGA
Plastic FLGA, 144-pin
(LGA-144P-M02)
Remarks
MB91191/192 Series
■ PACKAGE DIMENSION
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
Plastic LQFP, 120-pin
(FPT-120P-M05)
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
90
61
91
60
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
120
31
"A"
0~8˚
LEAD No.
1
0.40(.016)
30
0.16±0.03
(.006±.001)
0.07(.003)
M
0.145±0.055
(.006±.002)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
C
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
2003 FUJITSU LIMITED F120006S-c-4-5
Dimensions in mm (inches).
(Continued)
31
MB91191/192 Series
(Continued)
Plastic FLGA, 144-pin
(LGA-144P-M02)
11.00±0.10(.433±.004)SQ
0.65(.026)TYP
11.00±0.10
(.433±.004)
5.175(.204)
15
14
13
5.175
12
(.204)
11
10
9
8
7
6
5
4
3
0.45(.018)
2
1
9.10±0.10
(.358±.004)
REF
INDEX AREA
R P N M L K J H G F E D C B A
1.40(.055)
Max.
0.45(.018)
144-ø0.35
(144-ø.014)
0.08(.003)
C
0.08(.003)
M
3-ø0.45
(3-ø.018)
2001 FUJITSU LIMITED L144002S-c-1-1
Dimensions in mm (inches).
32
MB91191/192 Series
FUJITSU LIMITED
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FUJITSU LIMITED Printed in Japan