Ordering number : ENA0121A LC86F3G64A CMOS IC 96K-byte Flash Memory (ROM 64K-byte+CGROM 16K-byte +Extended ROM 16K-byte) on-chip 768-byte RAM and 352×9-bit Display RAM 8-bit 1-chip Microcontroller Overview The LC86F3G64A is a CMOS 8-bit single chip microcontroller with Flash Memory for the LC863G00 series. This microcontroller contains the following on-chip functional blocks: • CPU: Operable at a minimum bus cycle time of 0.424µs • On-chip ROM capacity: 96K bytes Flash Memory (Program ROM: 64K bytes, CGROM: 16K bytes, Extended ROM: 16K bytes ) • On-chip RAM capacity: 768 bytes • Display RAM: 352 × 9 bits • Closed-Caption TV controller and the on-screen display controller • Closed-Caption data slicer • Five channels × 8-bit AD Converter • Three channels × 7-bit PWM • Two 16-bit timer/counters, 14-bit base timer • 8-bit synchronous serial interface circuit • IIC-bus compliant serial interface circuit (Multi-master type) • UART interface circuit (full duplex) • ROM correct function • 16-source 10-vectored interrupt system Continued on next page. Note : This product includes the IIC bus interface circuit. If you intend to use the IIC bus interface, please notify us of this in advance of our receiving your program ROM code order. Purchase of SANYO IIC components conveys a license under the Philips IIC Patents Rights to use these components in an IIC system, provided that the system conforms to the IIC Standard Specification as defined by Philips. Trademarks IIC is a trademark of Philips Corporation. * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.1.00 N0106HKIM 20060830-S00008 No.A0121-1/25 LC86F3G64A Continued from preceding page. • Integrated system clock generator and display clock generator Only one X’tal oscillator (32.768kHz) for PLL reference is used for both generators All of the above functions are fabricated on a single chip. The program is rewritable by using the on-board writing system after the LSI has been installed on the application board. The LC86F3G64A change to LC863200/ LC863300/ LC863800 series by writing program data of LC863200/ LC863300/ LC863800 series into the Flash Memory. Features Built-in Flash Memory 96K bytes • Program ROM • Character ROM • Extended ROM • Rewritable in page units • Page erase / program cycle 64K bytes 16K bytes 16K bytes 128 bytes / page 100 cycle per page Random Access Memory (RAM) 768 × 8 bits (including 128 bytes for ROM correction function) 352 × 9 bits (for CRT display) The LC86F3G64A consists of 64K of ROM space and 768 bytes of RAM space. For this microcontroller, the usable program ROM capacity and RAM capacity are the same size for the mask ROM version. Mask ROM versions compatible Program ROM limit set for the RAM limit set for the LC86F3G64A with the LC86F3G64A LC86F3G64A (including 128 bytes for the ROM correction function) LC863G64/LC863864 65536 bytes LC863264/LC863364 65536 bytes 768 bytes 640 bytes LC863G56/LC863856 57344 bytes 768 bytes LC863256/LC863356 57344 bytes 640 bytes LC863G48/LC863848 49152 bytes 768 bytes LC863248/LC863348 49152 bytes 640 bytes LC863G40/LC863840 40960 bytes 768 bytes LC863240/LC863340 40960 bytes 640 bytes LC863G32/LC863832 32768 bytes 768 bytes LC863232/LC863332 32768 bytes 512 bytes LC863G28/LC863828 28672 bytes 768 bytes LC863228/LC863328 28672 bytes 512 bytes LC863G24/LC863824 24576 bytes 768 bytes LC863224/LC863324 24576 bytes 512 bytes LC863820 20480 bytes 768 bytes LC863220/LC863320 20480 bytes 512 bytes LC863816 16384 bytes 768 bytes LC863216/LC863316 16384 bytes 512 bytes OSD Functions • Screen display : 36 characters × 16 lines (by software) • RAM : 352 words (9 bits per word) Display area : 36 words × 8 lines Control area : 8 words × 8 lines • Characters Up to 252 kinds of 16 × 32 dot characters (4 characters including 1 test character are not programmable) Each font can be divided into two parts and used as two fonts (Ex. 16 × 16 dot character font × 2) At least 111 characters need to be divide between a 16×17 dot and 8 × 9 dot character font to display the caption fonts. No.A0121-2/25 LC86F3G64A • Various character attributes Character colors Character background colors Fringe / shadow colors Full screen colors Rounding Underline Italic character (slanting) : 16 colors : 16 colors : 16 colors : 16 colors • Attribute can be changed without spacing • Vertical display start line number can be set for each row independently (Rows can be overlapped) • Horizontal display start position can be set for each row independently • Horizontal pitch (9 to 16 dot)*1 and vertical pitch (1 to 32 dot) can be set for each row independently • Different display modes can be set for each row independently Caption • Text mode / OSD mode 1 / OSD mode 2 (Quarter size) / Simplified graphic mode • Ten character sizes*1 Horiz. × Vert. = (1 × 1), (1 × 2), (2 × 2), (2 × 4) (1.5 × 1), (1.5 × 2), (3 × 2), (3 × 4), (0.5 × 0.5), (0.75 × 0.5) • Shuttering and scrolling on each row • Simplified Graphic Display • External OSD clock input enable (LC863G00 series only) Note *1: range depends on display mode : refer to manual for details. Data Slicer : closed caption format (LC863200/LC863800/LC863G00 series only) • Closed caption data and XDS data extraction • NTSC/PAL, and extracted line can be specified (LC863800/LC863G00 series) • NTSC, and fixed line 21 (LC863200 series) Bus Cycle Time / Instruction-Cycle Time Bus Cycle Time Instruction Cycle Time Clock Divider 0.424µs 0.848µs 1/2 7.5µs 15.0µs 1/2 91.55µs 183.1µs 183.1µs 366.2µs System Clock Oscillation Internal VCO Oscillation Frequency Voltage 14.156MHz 4.5V to 5.5V Internal RC 800kHz 4.5V to 5.5V 1/1 Crystal 32.768kHz 4.5V to 5.5V 1/2 Crystal 32.768kHz 4.5V to 5.5V (Ref: X’tal 32.768kHz) Ports • Input / Output Ports : 5 ports (28 terminals) Data direction programmable in nibble units : 1 port (8 terminals) (If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.) Data direction programmable for each bit individually : 4 ports (20 terminals) • Input port (LC863300 series only) : 1 port (1 terminal) AD converter • 4-channels × 8-bit AD converters (LC863200/LC863800/LC863G00 series ) • 5-channels × 8-bit AD converters (LC863300 series) Serial interfaces • IIC-bus compatible serial interface (Multi-master type) Consists of a single built-in circuit with two I/O channels the two data lines and two clock lines can be short circuited internally. • Synchronous 8-bit serial interface No.A0121-3/25 LC86F3G64A UART (LC863G00 series only) • Full duplex • 7/8/9 bit data bits selectable • 1 stop bit • Built-in baudrate generator PWM Output • 3 channels×7-bit PWM Timer - Timer 0: 16-bit timer/counter With 2-bit prescaler + 8-bit built-in programmable prescaler Mode 0: Two 8-bit timers with a programmable prescaler Mode 1: 8-bit timer with a programmable prescaler + 8-bit counter Mode 2: 16-bit timer with a programmable prescaler Mode 3: 16-bit counter The resolution of timer is 1 tCYC. - Timer 1: 16-bit timer/PWM Mode 0: Two 8-bit timers Mode 1: 8-bit timer + 8-bit PWM Mode 2: 16-bit timer Mode 3: Variable bit PWM (9 to 16 bits) In mode 0/1, the resolution of Timer1/PWM is 1 tCYC In mode 2/3, the resolution is selectable by program; tCYC or 1/2 tCYC - Base timer Generate every 500ms overflow for a clock application (using 32.768kHz crystal oscillation for the base timer clock) Generate every 976µs, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768kHz crystal oscillation for the base timer clock) Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler output of Timer 0 Remote Control Receiver Circuit (connected to the P73/INT3/T0IN terminal) • Noise rejection function • Polarity switching Watchdog Timer External RC circuit is required Interrupt or system reset is activated when the timer overflows ROM Correction Function Max 128 bytes / 2 addresses Interrupts • 18 source 10 vectored interrupts: (LC863G00 series) • 16 source 10 vectored interrupts: (LC863200/LC863800 series) • 15 source 9 vectored interrupts: (LC863300 series) 1. External Interrupt INT0 2. External Interrupt INT1 3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits) 4. External Interrupt INT3, base timer 5. Timer/counter T0H (Upper 8 bits) 6. Timer T1H, T1L 7. SIO0, UART receive(LC863G00 series only) 8. Data slicer (LC863200/LC863800/LC863G00 series only), UART transmit (LC863G00 series only) 9. Vertical synchronous signal interrupt (VS), scanning line, AD 10. IIC, Port 0 No.A0121-4/25 LC86F3G64A • Interrupt priority control Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high priority can be assigned to the interrupts from 3 to 10 listed above. For the external interrupt INT0 and INT1, low or highest priority can be set. Sub-routine Stack Level • A maximum of 128 levels (stack area is assigned on the internal RAM) Multiplication/Division Instruction • 16 bits×8 bits (7 instruction cycle times) • 16 bits÷8 bits (7 instruction cycle times) 3 Oscillation Circuits • Built-in RC oscillation circuit used for the system clock • Built-in VCO circuit used for the system clock and OSD clock • On-chip X’tal oscillation circuit used for PLL reference and the system clock and base timer clock Standby Function • HALT mode The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped. This mode can be released by the interrupt request or the system reset. • HOLD mode The HOLD mode is used to stop the oscillations; RC (internal), VCO, and X’tal oscillations. This mode can be released by the following conditions. - Pull the reset terminal (RES) to low level. - Feed the selected level to either P70/INT0 or P71/INT1. - Feed the Port 0 interrupt condition Applicable Mask ROM Version • LC863G64/LC863G56/LC863G48/LC863G40/LC863G32/LC863G28/LC863G24 • LC863864/LC863856/LC863848/LC863840/LC863832/LC863828/LC863824/LC863820/LC863816 • LC863364/LC863356/LC863348/LC863340/LC863332/LC863328/LC863324/LC863320/LC863316 • LC863264/LC863256/LC863248/LC863240/LC863232/LC863228/LC863224/LC863220/LC863216 Package • DIP42S (Lead-free type) • QIP48E (Lead-free type) Development Tools • Evaluation chip: LC863096 • Emulator: LC863G00 series: Special ROM monitor tool (When debugging it, one terminal in the I/O port is used as a pin only for the tool) LC863800 series:EVA86000(main) + ECB863200A (evaluation chip board) + POD863200 (pod:DIP42S) [Shared with LC8632 Series] or POD863201 (QIP48E) [Shared with LC8632 Series] LC863300 series:EVA86000(main) + ECB863200*1 or ECB863200A (evaluation chip board) + POD863300 (pod:DIP42S) or POD863301 (QIP48E) LC863200 series: EVA86000(main) + ECB863200*1 or ECB863200A (evaluation chip board) + POD863200 (pod:DIP42S) or POD863201 (QIP48E) *1 This product is no longer available Write Flash Memory SANYO provides special services including writing data to Flash Memory and stamping. There is a charge for these services. Please feel free to ask our sales persons for details. No.A0121-5/25 LC86F3G64A Package Dimensions unit : mm (typ) 3025C 22 1 21 0.25 13.8 42 15.24 37.7 (4.25) 0.51min 3.8 5.1max 0.95 0.48 1.78 SANYO : DIP42S(600mil) (1.05) Package Dimensions unit : mm (typ) 3156A 17.2 0.8 14.0 24 48 13 14.0 37 1 17.2 25 36 12 1.0 0.35 0.15 0.1 3.0max (2.7) (1.5) SANYO : QIP48E(14X14) No.A0121-6/25 LC86F3G64A Pin Assignments P10/SO0 1 42 P07 P11/SI0 2 41 P06 P12/SCK0 3 40 P05 P13/PWM1 4 39 P04 P14/PWM2/TX 5 38 P03 P15/PWM3/RX 6 37 P02 P16/OSDCK 7 36 P01 P17/PWM 8 35 P00 VSS 9 34 P73/INT3/T0IN XT1 10 33 P72/INT2/T0IN XT2 11 32 P71/INT1 VDD 12 31 P70/INT0 P84/AN4 13 30 P63/SCLK1 P85/AN5 14 29 P62/SDA1 P86/AN6 15 28 P61/SCLK0 P87/AN7 16 27 P60/SDA0 RES 17 26 I LC86F3G64A FILT 18 25 BL CVIN/P83/AN3 19 24 B VS 20 23 G HS 21 22 R NC P14/PWM2/TX P13/PWM1 P12/SCK0 P11/SI0 P10/SO0 NC P07 P06 P05 P04 P03 48 47 46 45 44 43 42 41 40 39 38 37 Top view P15/PWM3/RX 1 36 P02 P16/OSDCK 2 35 P01 P17/PWM 3 34 P00 VSS 4 33 NC XT1 5 32 P73/INT3/T0IN XT2 6 31 P72/INT2/T0IN VDD 7 30 P71/INT1 NC 8 29 P70/INT0 P84/AN4 9 28 P63/SCLK1 P85/AN5 10 27 P62/SDA1 P86/AN6 11 26 P61/SCLK0 P87/AN7 12 25 P60/SDA0 23 24 I 22 BL NC 21 18 HS B 17 VS 20 16 NC 19 15 CVIN/P83/AN3 R 14 FILT G 13 RES LC86F3G64A Top view No.A0121-7/25 LC86F3G64A System Block Diagram Interrupt Control IR Flash Memory (96KB) VCO Clock RC Generator Stanby Control X’tal PLA Flash Memory Control PLL A0-A16 D0-D7 CE OE WE PC ACC IIC ROM Correct Control B Register XRAM SIO0 C Register Timer 0 Bus Interface Timer 1 Port 1 Base Timer Port 6 ADC Port 7 INT0-3 Noise Rejection Filter Port 8 ALU PSW RAR RAM PWM Data Slicer LC863200/LC863800/ LC863G00 only CGROM OSD Control Circuit VRAM Stack Pointer Port 0 UART LC863G00only Watchdog Timer No.A0121-8/25 LC86F3G64A Pin Description Pin Description Table Flash memory mode Terminal I/O Function Description Option (Parallel input/ output mode) VSS - Negative power supply XT1 I Input terminal for crystal oscillator XT2 O Output terminal for crystal oscillator VDD - Positive power supply RES I Reset terminal Input to set up mode FILT O Filter terminal for PLL Address input A16 CVIN I Video signal input terminal (LC863200/LC863800/LC863G00 only ) VS I Vertical synchronization signal input terminal HS I Horizontal synchronization signal input terminal R O Red (R) output terminal of RGB image output G O Green (G) output terminal of RGB image output B O Blue (B) output terminal of RGB image output I O Intensity ( I ) output terminal of RGB image output Address input A13 BL O Fast blanking control signal Address input A14 Port 0 I/O •8-bit input/output port, Pull-up register Address input Input/output can be specified in nibble unit Present/ A0 to A7 •Other functions not present HOLD release input Output Format Interrupt input CMOS/Nch-OD •8-bit input/output port Output Format Data input/output Input/output can be specified in a bit CMOS/Nch-OD D0 to D7 Input to set up mode Address input A15 Switch TV image signal and caption/OSD image signal P00 - P07 Port 1 I/O P10 - P17 •Other functions Port 6 P60 - P63 I/O P10 SIO0 data output P11 SIO0 data input/bus input/output P12 SIO0 clock input/output P13 PWM1 output P14 PWM2 output / UART transmit (LC863G00 only) P15 PWM3 output / UART receive (LC863G00 only) P16 External OSD clock input (LC863G00 only) P17 Timer1 (PWM) output •4-bit input/output port Input/output can be specified for each bit •Other functions control signal CE control signal OE P60 IIC0 data I/O P61 IIC0 clock output P62 IIC1 data I/O control signal WE P63 IIC1 clock output Address input A12 Continued on next page. No.A0121-9/25 LC86F3G64A Continued from preceding page. Flash memory mode Terminal I/O Function Description Option (Parallel input/ output mode) I/O Port 7 •4-bit input/output port Address input P70 Input or output can be specified for each bit A8 to A11 P71 - P73 •Other function INT0 input/HOLD release input/ P70 Nch-Tr. output for watchdog timer P71 INT1 input/HOLD release input P72 INT2 input/Timer 0 event input P73 INT3 input (noise rejection filter attached)/ Timer 0 event input Interrupt receiver format, vector addresses rising falling rising/ H level L level vector enable enable 03H 0BH falling INT0 enable enable disable INT1 enable enable disable enable enable INT2 enable enable enable disable disable 13H INT3 enable enable enable disable disable 1BH Port 8 P83 I •1-bit input port (LC863300 only) •Other function AD converter input port (1 lines) P84 - P87 I/O •4-bit input/output port Input or output can be specified for each bit •Other function AD converter input port (4 lines) NC - unused terminal Leave open • Output form and existence of pull-up resistor for every port can be specified for each bit. • Programmable pull-up resister is always connected regardless of port option, CMOS or N-ch open drain output in port 1. User Options User options can be changed using Flash Memory data. A kind of option Pin, Circuits Input/output form of Port 0 input/output ports (Specified in a bit) 1. Input: Without pull-up MOS Tr. Output: N-channel open drain 2. Input: With pull-up MOS Tr. Output: CMOS Port 1 (Specified in a bit) 1. Input: With programmable pull-up MOS Tr. Output: N-channel open drain 2. Input: With programmable pull-up MOS Tr. Output: CMOS No.A0121-10/25 LC86F3G64A Notice for Use • Input level of terminal RES at power on Terminal RES must be held low for at least 200µs after the supply voltage exceeds the power supply lower limit. Power supply VDD limit 0V 200µs or more RES • Difference between the Mask version and Flash version 1. The operation after release of reset: The mask version operates the program from the address 0 in the program counter as soon as detecting the H level on the reset port. The flash version operates the program from the address 0 in the program counter after setting the option. 2. Current dissipation : Please refer to the latest semiconductor news. • Conditions during reset and after release of reset Port options are set using Flash Memory data. Port options are set internally within approximately 3ms after logic HIGH is applied to the RESET terminal. The configuration of the port outputs change over the duration of this period. Then the Program Counter is set to 0 and program execution begins. During reset, and in the few hundred milliseconds after reset is released, the port options on certain of the ports will not yet have been set. The conditions of the various ports during reset or on release of reset have been collected in the following table. Please refer to it when analyzing circuits where these conditions apply. Pins P0 Options Condition during and on release of reset Input: Without pull up MOS transistor Output -off Output: N-channel open drain Input mode: High impedance Input: With pull up MOS transistor Output-off Output: CMOS During reset and in the first few hundred µs after reset is released, the pull-up MOS transistor is OFF. Thereafter, set to input mode with pull-up MOS Tr. ON P1 Input: With programmable pull up MOS transistor Output-off Output: N-channel open drain Input mode: High impedance Input: With programmable pull up MOS transistor Output: CMOS P6 P7 No options Output -off Output: N-channel open drain Input mode: High impedance No options Output-off Input: With programmable pull up MOS transistor Input mode: Pull up MOS transistor off Output: N-channel open drain (P70) CMOS (P71 - P73) P8 No options Output-off Input: With programmable pull up MOS Input mode: Pull up MOS transistor off Transistor (P83: without it) Output: CMOS (P83: input only) No.A0121-11/25 LC86F3G64A On-board writing system The LC86F3G64A has the On-board writing system. The program is renewable by using SANYO Flash On-board System after the LSI has been installed on the application board. This system is composed of 4 types divided by the combination of the mode setting pin and communication pin. Each type system has to connect the 6 pins (VDD, VSS, RES, communication pins) with the interface board of SANYO Flash On-board System. It is necessary that the pins to be used for the rewriting system should be able to be separated from the application board properly. The system type is selected by the option setting program (Su86K.exe). types mode setting pin communication pins type1 RES pin (high voltage(12V) applied) P00(DATA1), P01(DATA0), P02(CLK) type2 RES pin (high voltage(12V) applied) P00(DATA1), P60(DATA0), P61(CLK) type3 P00 pin (High level voltage applied) P00(ENA/DATA1), P01(DATA0), P02(CLK) type4 P00 pin (High level voltage applied) P00(ENA/DATA1), P60(DATA0), P61(CLK) • Type 3 or 4 is selected: P00 is exclusive for the on-board system. This pin must always be pulled-down, so this pin can’t be used for other applications. Please set P00 pin N-channel open drain output.(option setting) In the user program, “0” is always set to the P00 latch (bit 0 in the Port 0 latch (140h)) because the P0 interrupt must not be requested on the P00 pin . • The loader program must be written into the ROM to use On-board writing system. The loader program should be written into the ROM before the LSI has been installed on the board by the general purpose PROM programs. When the option setting selects the this system to use, the loader program automatically links to the extended ROM field (14000h-147FFh) on the user program linking. Please ask to our sales persons before using On-board writing system. No.A0121-12/25 LC86F3G64A Method of how to rewrite it in FLASH programmer / SANYO FLASH writing tool (SFWS) When reading or writing data to the LC86F3G64A, FLASH programmer of our recommendation or SANYO FLASH writing tool (SFWS) is used. In both cases, exclusive conversion board (W86F3264D, W86F3264Q) is needed. (1) FLASH programmer of our recommendation Single Word Write Manufacture Name of device Flash Support Group co. (the former Ando Electric) version AF9708 Rev2.43 Name of device version applicable device (code) Data protection setting after write operation SANYO Protected LC86F3G64A (3B225) Write Multiple Words Manufacture Flash Support Group co. AF9723 + (the former Ando Electric) AF9833 applicable device (code) Rev2.04 +Rev01.85 *1 Data protection setting after write operation SANYO Protected LC86F3G64A (3B225) *1: Registration is being requested. The LC86F3G64A does not support a silicon signature feature. Do not use the feature (automatic device type selection) when programming this device. To avoid erasing the program, confirm the setting of the protection for activating the written program before using. It can’t be written with device code 29EE010 (2) SANYO FLASH writing tool (SFWS) PC is connected with writer unit (SKK) by USB cable and it uses it. (3) Exclusive writing conversion board • W86F3264D • • • DIP42S purpose (It is common with production discontinuance model (LC86F3264A/LC86F3364A/LC86F3864A) ) • W86F3264Q • • • QIP48E purpose (It is common with production discontinuance model (LC86F3264A/LC86F3364A/ LC86F3864A) ) When using the conversion board, all of the jumper SW must be set to the OFF position. If set to the ON position, read/write operations will not perform correctly. Pin 1 of the conversion board should be located as indicated below. W86F3264D: when viewing from the edge closest to jumper SW, pin 1 is located on the lower right of both the chip and conversion board. W86F3264Q: when viewing from the edge closest to jumper SW, pin 1 of the chip is located on the upper right while pin 1 of the conversion board is located on the lower right. Chip: pin 1 Pin 1 Pin 1 Set jumper SW to OFF W86F3264D Set jumper SW to OFF W86F3264Q No.A0121-13/25 LC86F3G64A Absolute Maximum Ratings at Ta = 25°C, VSS = 0V Parameter Symbol Pins Specification Conditions VDD[V] Maximum supply VDD max VDD VI(1) •RES, HS, VS, voltage Input voltage CVIN/P83 Output voltage VO(1) R, G, B, I, BL, Input/output voltage VIO(1) •Ports 0, 1, 6, 7, FILT 84-87 High Peak level output output current IOPH(1) •Ports 0, 1, 7, 84-87 •CMOS output •For each pin. IOPH(2) R, G, B, I, BL current •CMOS output •For each pin. min typ max unit -0.3 +6.5 -0.3 VDD+0. 3 -0.3 VDD+0.3 -0.3 VDD+0.3 -4 -5 Total ΣIOAH(1) •Ports 0, 1 The total of all pins. -20 output ΣIOAH(2) Ports 7, 84-87 The total of all pins. -10 -15 current ΣIOAH(3) R, G, B, I, BL The total of all pins. Low Peak IOPL(1) Ports 0, 1, 6, 84-87 For each pin. 15 level output IOPL(2) Port 7 For each pin. 15 output current IOPL(3) R, G, B, I, BL For each pin. Total ΣIOAL(1) Ports 0, 1 The total of all pins. 40 output ΣIOAL(2) Ports 6, 7, 84-87 The total of all pins. 35 current ΣIOAL(3) R, G, B, I, BL The total of all pins. Pd max DIP42S Ta=-30 to +85°C current Maximum power dissipation Operating mA 5 15 500 QIP48E -30 +85 range temperature mW 280 Topr temperature Storage V °C Tstg -55 +125 range No.A0121-14/25 LC86F3G64A Recommended Operating Range at Ta = -30°C to +85°C, VSS = 0V Parameter Symbol Pins Specification Conditions VDD[V] Operating VDD(1) supply voltage VDD(2) VDD VHD VDD typ max unit 0.844µs ≤ tCYC ≤ 0.852µs 4.5 5.5 4µs ≤ tCYC ≤ 400µs 4.5 5.5 2.0 5.5 range Hold voltage min RAMs and the registers data are kept in HOLD mode. High level VIH(1) Port 0 (Schumitt) Output disable VIH(2) •Ports 1,6 Output disable input voltage VDD 4.5 to 5.5 0.6VDD 4.5 to 5.5 0.75VDD 4.5 to 5.5 VDD-0.5 4.5 to 5.5 0.7VDD 4.5 to 5.5 0.45VDD 4.5 to 5.5 VSS 0.2VDD 4.5 to 5.5 VSS 0.25VDD 4.5 to 5.5 VSS 0.6VDD 4.5 to 5.5 VSS 0.3VDD 4.5 to 5.5 VSS 0.18VDD (Schumitt CMOS) •Port 7 (Schumitt) port input/interrupt •HS, VS, RES, VDD (Schumitt CMOS) VIH(3) Port 70 Output disable Watchdog timer input VIH(4) •Port 8 Output disable port input VIH(5) •Port 16 (TTL) •Port 6, HS, VS VDD VDD V Output disable (Schumitt TTL) VDD LC863G00 only Low level VIL(1) Port 0 (Schumitt) Output disable input voltage VIL(2) •Ports 1,6 Output disable (Schumitt CMOS) •Port 7 (Schumitt) port input/interrupt •HS, VS, RES, (Schumitt CMOS) VIL(3) Port 70 Output disable Watchdog timer input VIL(4) Port 8 Output disable port input VIL(5) •Port 16 (TTL) •Port 6, HS, VS Output disable (Schumitt TTL) LC863G00 only CVIN VCVIN CVIN 5.0 Operation tCYC(1) •All functions operating cycle time tCYC(2) •AD converter operating •OSD and Data slicer 1Vp-p -3dB 4.5 to 5.5 0.844 4.5 to 5.5 0.844 1Vp-p 0.848 1Vp-p +3dB 0.852 30 µs are not operating tCYC(3) Vp-p* •OSD, AD converter and Data slicer are 4.5 to 5.5 0.844 400 4.5 to 5.5 0.4 0.8 3.0 MHz 4.5 to 5.5 13 14 15 MHz not operating Oscillation FmRC Internal RC oscillation frequency range External FmICK OSD clock input P16/OSDCK DUTY50±5% of external (LC863G00 only) OSD clock frequency range * Vp-p: Peak-to-peak voltage No.A0121-15/25 LC86F3G64A Electrical Characteristics at Ta = -30°C to +85°C, VSS = 0V Parameter Symbol Pins Specification Conditions VDD[V] High level IIH(1) Ports 0, 1, 6, 7, 8 input current min typ max unit •Output disable •Pull-up MOS Tr. OFF •VIN=VDD 4.5 to 5.5 1 4.5 to 5.5 1 (including the off- leak current of the output Tr.) Low level IIH(2) •RES •HS, VS •VIN=VDD IIL(1) Ports 0, 1, 6, 7, 8 •Output disable input current µA •Pull-up MOS Tr. OFF •VIN=VSS 4.5 to 5.5 -1 4.5 to 5.5 -1 4.5 to 5.5 VDD-1 4.5 to 5.5 VDD-0.5 (including the off- leak current of the output Tr.) High level IIL(2) •RES •HS, VS VIN=VSS VOH(1) •CMOS output of IOH=-1.0mA output voltage ports 0,1,71-73, 84-87 Low level VOH(2) R, G, B, I, BL IOH=-0.1mA VOL(1) Ports 0,1,71-73, IOL=10mA output voltage 84-87 VOL(2) Ports 0,1,71-73, VOL(3) •R, G, B, I, BL IOL=1.6mA 84-87 IOL=3.0mA •Port 6 Pull-up MOS 1.5 4.5 to 5.5 0.4 4.5 to 5.5 0.4 V VOL(4) Port 6 IOL=6.0mA 4.5 to 5.5 0.6 VOL(5) Port 70 IOL=1mA 4.5 to 5.5 0.4 Rpu •Ports 0, 1, 7, VOH=0.9VDD Tr. resistance Bus terminal 4.5 to 5.5 84-87 RBS short circuit 4.5 to 5.5 13 38 80 kΩ 4.5 to 5.5 130 300 Ω 4.5 to 5.5 0.1VDD •P60-P62 •P61-P63 resistance (SCL0-SCL1, SDA0-SDA1) Hysteresis VHYS Input clump •Ports 0, 1, 6, 7 Output disable •RES •HS, VS voltage VCLMP CVIN CP All pins V 5.0 voltage Pin capacitance 2.3 2.5 2.7 •f=1MHz •Every other terminals are connected to VSS. 4.5 to 5.5 10 pF •Ta=25°C No.A0121-16/25 LC86F3G64A Serial input/output characteristics at Ta = -30°C to +85°C, VSS = 0V Parameter Symbol Pins Specification Conditions VDD[V] Input clock tCKCY(1) •SCK0 Refer to figure 4. Low Level tCKL(1) 4.5 to 5.5 pulse width High Level tCKCY(2) Low Level tCKL(2) •SCK0 tCYC •Use pull-up resistor (1kΩ) 2 when Nch open-drain output. •Refer to figure 4. 4.5 to 5.5 pulse width 1/2tCKCY tCKH(2) 1/2tCKCY pulse width Serial input Data set up time SI0 •Data set-up to SCK0. 0.1 •Data hold from SCK0. •Refer to figure 4. Data hold time 4.5 to 5.5 tCKI 0.1 Output delay time Serial output tICK unit 1 •SCLK0 High Level max 1 tCKH(1) Cycle typ 2 •SCLK0 pulse width Output clock Serial clock Cycle min tCKO(1) SO0 µs •Data hold from SCK0. 4.5 to 5.5 (Using external •Use pull-up resistor (1kΩ) clock) when Nch open-drain output. Output delay time tCKO(2) SO0 7/12tCYC +0.2 •Refer to figure 4. (Using internal 1/3tCYC 4.5 to 5.5 +0.2 clock) IIC Input/Output Conditions at Ta = -30°C to +85°C, VSS = 0V Parameter Standard Symbol min High speed max SCL Frequency fSCL 0 BUS free time between stop - start tBUF 4.7 HOLD time of start, restart condition tHD;STA L time of SCL tLOW H time of SCL tHIGH Set-up time of restart condition min 100 unit max 0 400 kHz 1.3 µs 4.0 0.6 µs 4.7 1.3 µs 4.0 0.6 µs tSU;STA 4.7 0.6 HOLD time of SDA tHD;DAT 0 0 Set-up time of SDA tSU;DAT 250 100 Rising time of SDA, SCL tR 1000 20+0.1Cb 300 ns Falling time of SDA, SCL tF 300 20+0.1Cb 300 ns Set-up time of stop condition tSU;STO 4.0 0.6 µs 0.9 µs ns µs Refer to figure 10 Note Cb: Total capacitance of all BUS (unit: pF) No.A0121-17/25 LC86F3G64A UART (Full Duplex) Operating Conditions at Ta = -30°C to +85°C, VSS = 0V (LC863G00 only) Parameter Symbol Pin/Remarks Specification Condition VDD[V] Transfer rate* UBR(1) P14, 15 0.844µs ≤ tCYC ≤ 400µs 4.5 to 5.5 UBR(2) * High speed mode: UBR= (n+1) × (8/6)tCYC Low speed mode: UBR= (n+1) × (32/6)tCYC min 16/6 typ max 8192/6 unit tCYC n=1 to 255 Data length: 7/8/9 bits(LSB First) Stop bits: 1 bit Parity bits: None Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data = 55H) Start bit Start of transmission Stop bit Transmit data (LSB First) End of transmission UBR Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data = 55H) Start bit Stop bit Receive data (LSB First) Start of reception End of reception UBR No.A0121-18/25 LC86F3G64A Pulse Input Conditions at Ta = -30°C to +85°C, VSS = 0V Parameter Symbol Pins Specification Conditions VDD[V] High/low level tPIH(1) •INT0, INT1 •Interrupt acceptable pulse width tPIL(1) •INT2/T0IN •Timer0-countable tPIH(2) INT3/T0IN •Interrupt acceptable tPIL(2) (The noise rejection clock is •Timer0-countable min 4.5 to 5.5 1 4.5 to 5.5 2 4.5 to 5.5 32 typ max unit selected to 1tCYC.) tPIH(3) INT3/T0IN •Interrupt acceptable tPIL(3) (The noise rejection clock is •Timer0-countable tCYC selected to 16tCYC.) tPIH(4) INT3/T0IN •Interrupt acceptable tPIL(4) (The noise rejection clock is •Timer0-countable 4.5 to 5.5 128 4.5 to 5.5 200 4.5 to 5.5 3 selected to 64tCYC.) tPIL(5) RES Reset acceptable tPIH(6) HS, VS •Display position controllable •The active edge of HS and tPIL(6) VS must be apart at least µs 1 tCYC. •Refer to figure 6. Rising/falling tTHL time tTLH External tOSCK HS Refer to figure 6. OSDCK (P16) Refer to figure 7. 4.5 to 5.5 4.5 to 5.5 OSD clock 500 10 ns ns input AD Converter Characteristics at Ta = -30°C to +85°C, VSS = 0V Parameter Symbol Pins Limits Conditions VDD[V] Resolution N Absolute ET (Note 3) tCAD ADCR2=0 (Note 4) min typ 8 ADCR2=1 (Note 4) Analog input VAIN AN4 - AN7 Analog port IAINH VAIN=VDD input current IAINL VAIN=VSS LSB tCYC 32 VSS (LC863300: AN3-AN7) voltage range 16 4.5 to 5.5 unit bit ±1.5 precision Conversion time max VDD 1 V µA -1 Note 3: Absolute precision does not include quantizing error (1/2LSB). Note 4: Conversion time is the time till the complete digital conversion value for analog input value is set to a register after the instruction to start conversion is sent. No.A0121-19/25 LC86F3G64A Sample Current Dissipation Characteristics at Ta = -30°C to +85°C, VSS = 0V The sample current dissipation characteristics is the measurement result of Sanyo provided evaluation board when the recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. The currents through the output transistors and the pull-up MOS transistors are ignored. Parameter Symbol Pins Specification Conditions VDD[V] Current dissipation IDDOP(1) VDD typ max unit •FmX’tal=32.768kHz X’tal oscillation during basic •System clock: VCO for system operation •VCO for OSD operating (Note 3) min 4.5 to 5.5 12 24 mA 4.5 to 5.5 60 300 µA 4.5 to 5.5 3 9 mA 4.5 to 5.5 350 1000 •Internal RC oscillation stops IDDOP(2) •FmX’tal=32.768kHz X’tal oscillation •System clock: X'tal (Instruction cycle time: 366.2µs) •VCO for system, VCO for OSD, Internal RC oscillation stop •Data slicer, AD converters stop Current dissipation IDDHALT(1) •HALT mode in HALT mode •FmX’tal=32.768kHz X’tal oscillation (Note 3) •VCO for system stops •System clock: VCO for system • Internal RC stops IDDHALT(2) •HALT mode •FmX’tal=32.768kHz X’tal oscillation •VCO for system stops •VCO for OSD stops •System clock: Internal RC IDDHALT(3) µA •HALT mode •FmX’tal=32.768kHz X’tal oscillation •VCO for system stops •VCO for OSD stops 4.5 to 5.5 40 200 4.5 to 5.5 0.05 20 •System clock: X’tal (Instruction cycle time: 366.2µs) Current dissipation in HOLD mode IDDHOLD •HOLD mode •All oscillation stops. µA (Note 3) Note 3: The currents of the output transistors and the pull-up MOS transistors are ignored. No.A0121-20/25 LC86F3G64A Recommended Oscillation Circuit and Sample Characteristics The sample oscillation circuit characteristics in the table below is based on the following conditions: Recommended circuit parameters are verified by an oscillator manufacturer using a Sanyo provided oscillation evaluation board. Sample characteristics are the result of the evaluation with the recommended circuit parameters connected externally. Recommended oscillation circuit and sample characteristics (Ta = -30°C to +85°C) Frequency 32.768kHz Manufacturer SEIKO EPSON Recommended circuit parameters Oscillator C-002RX Operating Oscillation supply stabilizing time C1 C2 Rf Rd voltage range typ max 18pF 18pF OPEN 680kΩ 4.5 to 5.5V 1.0s 1.5s Notes Notes: The oscillation stabilizing time period is the time until the VCO oscillation for the internal system becomes stable after the following conditions. (Refer to Figure 2.) 1. The VDD becomes higher than the minimum operating voltage after the power is supplied. 2. The HOLD mode is released. The sample oscillation circuit characteristics may differ applications. For further assistance, please contact with oscillator manufacturer with the following notes in your mind. • Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the oscillation frequency on the production board. • The above oscillation frequency and the operating supply voltage range are based on the operating temperature of -30°C to +85°C. For the use with the temperature outside of the range herein, or in the applications requiring high reliability such as car products, please consult with oscillator manufacturer. • When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with Sanyo sales personnel. Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low gain in order to reduce the power dissipation, refer to the following notices. • The distance between the clock I/O terminal (XT1 terminal XT2 terminal) and external parts should be as short as possible. • The capacitors’ VSS should be allocated close to the microcontroller’s GND terminal and be away from other GND. • The signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit. XT1 XT2 Rf Rd C1 C2 X’tal Figure 1 Recommended Oscillation Circuit No.A0121-21/25 LC86F3G64A VDD VDD limit 0V Power supply Reset time RES Internal RC resonator oscillation XT1,XT2 tmsVCO VCO for system Operation mode stable Unfixed Reset Instruction execution mode Reset Time and Oscillation Stabilizing Time HOLD release signal Valid Internal RC resonator oscillation XT1, XT2 tmsVCO VCO for system Operation mode stable HOLD Instruction execution mode Hold release signal and oscillation stabilizing time. Figure 2 Oscillation Stabilizing Time No.A0121-22/25 LC86F3G64A VDD RRES (Note) Determine the CRES, RRES value to get more than 200µs reset time. RES CRES Figure 3 Reset Circuit 0.5VDD < AC timing measurement point > VDD tCKCY tCKL tCKH SCK0 tICK tCKI SI0 tCKO 50pF SO0 SB0 < Timing > < Test load > Figure 4 Serial Input/Output Test Condition tPIL tPIH Figure 5 Pulse Input Timing Condition-1 No.A0121-23/25 LC86F3G64A tPIL(6) HS 0.75VDD 0.25VDD tTLH VS tPIL(6) Figure 6 Pulse Input Timing Condition - 2 HS OSDCK tOSCK tOSCK Note: tOSCK must be saving constant Figure 7 Pulse Input Timing Condition - 3 LC86F3G64A 10kΩ HS C536 HS Figure 8 Recommended Interface Circuit Noise filter 1µF C-Video CVIN 200Ω 1000pF Coupling capacitor Output impedance of C-Video before Noise filter should be less then 100Ω. Figure 9 CVIN Recommended Circuit No.A0121-24/25 LC86F3G64A 100Ω 33000pF 1MΩ 2.2µF FILT + - Figure 10 FILT Recommended Circuit Note: Place FILT parts on board as close to the microcontroller as possible. P S P Sr SDA tBUF tHD;STA tHD;STA tF tR tsp SCL tHIGH tLOW tHD;DAT S : start condition P : stop condition Sr : restart condition tSU;DAT tsp : spike suppression tSU;STA tSU;STO Standard mode : not exist High speed mode : less than 50ns Figure 11 IIC Timing SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of November, 2006. Specifications and information herein are subject to change without notice. PS No.A0121-25/25