SANYO LC877440A

LC877448A/40A/32A/24A
Features
(1) Read-Only Memory (ROM)
• 49152 × 8 bits (LC877448A)
• 40960 × 8 bits (LC877440A)
• 32768 × 8 bits (LC877432A)
• 24576 × 8 bits (LC877424A)
(2) Random Access Memory (RAM): 1536 × 9 bits (LC877448A, LC877440A, LC877432A, LC877424A)
(3) Minimum Bus Cycle Time: 100 ns (10MHz)
Note: The bus cycle time indicates ROM read time.
(4) Minimum Instruction Cycle Time: 300 ns (10MHz)
(5) Ports
• Input / output ports
Data direction programmable for each bit individually:
26 (P1n, P30 to P35, P70 to P73, P8n)
Data direction programmable in nibble units:
8 (P0n)
(When N-channel open drain output is selected, data can be input in bit units.)
• Input ports:
2 (XT1, XT2)
• LCD ports
Segment output:
48 (S00 to S47)
Common output:
4 (COM0 to COM3)
Bias terminals for LCD driver:
3 (V1 to V3)
Other functions
Input / output ports:
48 (PAn, PBn, PCn, PDn, PEn, PFn)
Input ports:
7 (PLn)
• Oscillator pins:
2 (CF1, CF2)
• Reset pin:
1 (RES)
• Power supply:
6 (VSS1 to 3, VDD1 to 3)
(6) LCD controller
• Seven display modes are available (static, 1/2, 1/3, 1/4 duty × 1/2, 1/3 bias)
• Segment output and common output can be switched to general purpose input / output ports.
(7) Small signal detection (MIC signals etc)
• Counts pulses with the level which is greater than a preset value
• 2 bit counter
(8) Timers
• Timer 0: 16 bit timer / counter with capture register
Mode 0: 2 channel 8 bit timer with programmable 8 bit prescaler and 8 bit capture register
Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit
counter with 8 bit capture register
Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register
Mode 3: 16 bit counter with 16 bit capture register
• Timer 1: PWM / 16 bit timer / counter with toggle output function
Mode 0: 8 bit timer (with toggle output) + 8 bit timer / counter (with toggle output)
Mode 1: 2 channel 8 bit PWM
Mode 2: 16 bit timer / counter (with toggle output) Toggle output from lower 8 bits is also possible.
Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM.
• Timer 4: 8 bit timer with 6 bit prescaler
• Timer 5: 8 bit timer with 6 bit prescaler
• Timer 6: 8 bit timer with 6 bit prescaler
• Timer 7: 8 bit timer with 6 bit prescaler
Continued on next page.
No.7776-2/22
LC877448A/40A/32A/24A
Continued from preceding page.
• Base Timer
1) The clock signal can be selected from any of the following:
Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0
2) Interrupts of five different time intervals are possible.
(9) High-speed clock counter
• Countable up to 20MHz clock (when using 10MHz main clock)
• Real time output
(10) Serial-interface
• SIO 0: 8 bit synchronous serial interface
1) LSB first / MSB first is selectable
2) Internal 8 bit baud-rate generator (fastest clock period 4 / 3 tCYC)
3) Consecutive automatic data communication (1 to 256 bits)
• SIO 1: 8 bit asynchronous / synchronous serial interface
Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2 to 512 tCYC)
Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tCYC)
Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
(11) AD converter
• 8 bits × 15 channels
(12) Remote control receiver circuit (connected to P73 / INT3 / T0IN terminal)
• Noise rejection function (noise rejection filter’s time constant can be selected from 1 / 32 / 128 tCYC)
(13) Watchdog timer
• The watching time period is determined by an external RC.
• Watchdog timer can produce interrupt or system reset
(14) Interrupts: 20 sources, 10 vectors
1) Three priority (low, high and highest) multiple interrupts are supported.
During interrupt handling, an equal or lower priority interrupt request is postponed.
2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence.
In the case of equal priority levels, the vector with the lowest address takes precedence.
No.
Vector
Selectable level
Interrupt signal
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2 / T0L / INT4
4
0001BH
H or L
INT3 / Base timer / INT5
5
00023H
H or L
T0H
6
0002BH
H or L
T1L / T1H
7
00033H
H or L
SIO0
8
0003BH
H or L
SIO1
9
00043H
H or L
ADC / MIC / T6 / T7
10
0004BH
H or L
Port 0 / T4 / T5
• Priority Level: X > H > L
• For equal priority levels, vector with lowest address takes precedence.
(15) Subroutine stack levels: 768 levels max. Stack is located in RAM.
(16) Multiplication and division
• 16 bit × 8 bit (executed in 5 cycles)
• 24 bit × 16 bit (12 cycles)
• 16 bit ÷ 8 bit (8 cycles)
• 24 bit ÷ 16 bit (12 cycles)
No.7776-3/22
LC877448A/40A/32A/24A
(17) Oscillation circuits
• On-chip RC oscillation for system clock use.
• CF oscillation for system clock use. (Rf built in, Rd external)
• Crystal oscillation low speed system clock use. (Rf built in, Rd external)
• On-chip frequency variable RC oscillation circuit for system clock use.
(18) System clock divider
• Low power consumption operation is available
• Minimum instruction cycle time (300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, 76.8µs can be
switched by program (when using 10MHz main clock)
(19) Standby function
• HALT mode
HALT mode is used to reduce power consumption. During the HALT mode, program execution is stopped but
peripheral circuits keep operating (some parts of serial transfer operation stop.)
1) Oscillation circuits are not stopped automatically.
2) Released by the system reset or interrupts.
• HOLD mode
HOLD mode is used to reduce power consumption. Program execution and peripheral circuits are stopped.
1) CF, RC and crystal oscillation circuits stop automatically.
2) Released by any of the following conditions.
(1) Low level input to the reset pin
(2) Specified level input to one of INT0, INT1, INT2, INT4, INT5
(3) Port 0 interrupt
• X’tal HOLD mode
X’tal HOLD mode is used to reduce power consumption. Program execution is stopped.
All peripheral circuits except the base timer are stopped.
1) CF and RC oscillation circuits stop automatically.
2) Crystal oscillator operation is kept in its state at HOLD mode inception.
3) Released by any of the following conditions
(1) Low level input to the reset pin
(2) Specified level input to one of INT0, INT1, INT2, INT4, INT5
(3) Port 0 interrupt
(4) Base-timer interrupt
(20) Package
• QIP100E
• TQFP100
(21) Development tools
• Evaluation chip: LC876093
• Emulator: EVA62S + ECB876600 (Evaluation chip board) + SUB877400 + POD100QFP or
POD100SQFP (Type B)
: ICE-B877300 + SUB877400 + POD100QFP or POD100SQFP (Type B)
• Flash ROM version: LC87F74C8A
No.7776-4/22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V2/PL5/AN13
V1/PL4/AN12
COM0/PL0
COM1/PL1
COM2/PL2
COM3/PL3
P30/INT4/T1IN
P31/INT4/T1IN
VSS3
VDD3
P32/INT4/T1IN
P33/INT4/T1IN
P34/INT5/T1IN
P35/INT5/T1IN
P00
P01
P02
P03
P04
P05
P06
P07
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/T1PWML
P17/T1PWMH/BUZ
RES
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7/MICIN
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
P73/INT3/T0IN
S0/PA0
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V3/PL6/AN14
S47/PF7
S46/PF6
S45/PF5
S44/PF4
S43/PF3
S42/PF2
S41/PF1
S40/PF0
S39/PE7
S38/PE6
S37/PE5
S36/PE4
S35/PE3
S34/PE2
S33/PE1
S32/PE0
S31/PD7
S30/PD6
S29/PD5
S28/PD4
S27/PD3
S26/PD2
S25/PD1
S24/PD0
VSS2
VDD2
S23/PC7
S22/PC6
S21/PC5
LC877448A/40A/32A/24A
Pin Assignment
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
LC877448A
LC877440A
LC877432A
LC877424A
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
S15/PB7
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1PA1
Top view
SANYO : QIP100E
No.7776-5/22
LC877448A/40A/32A/24A
LC877448A
LC877440A
LC877432A
LC877424A
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
S23/PC7
S22/PC6
S21/PC5
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
S15/PB7
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1PA1
S0/PA0
P73/INT3/T0IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/T1PWML
P17/T1PWMH/BUZ
RES
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7/MICIN
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
S47/PF7
V3/PL6/AN14
V2/PL5/AN13
V1/PL4/AN12
COM0/PL0
COM1/PL1
COM2/PL2
COM3/PL3
P30/INT4/T1IN
P31/INT4/T1IN
VSS3
VDD3
P32/INT4/T1IN
P33/INT4/T1IN
P34/INT5/T1IN
P35/INT5/T1IN
P00
P01
P02
P03
P04
P05
P06
P07
P10/SO0
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
S46/PF6
S45/PF5
S44/PF4
S43/PF3
S42/PF2
S41/PF1
S40/PF0
S39/PE7
S38/PE6
S37/PE5
S36/PE4
S35/PE3
S34/PE2
S33/PE1
S32/PE0
S31/PD7
S30/PD6
S29/PD5
S28/PD4
S27/PD3
S26/PD2
S25/PD1
S24/PD0
VSS2
VDD2
Pin Assignment
Top view
SANYO : TQFP100
No.7776-6/22
LC877448A/40A/32A/24A
System Block Diagram
Interrupt Control
IR
Stand-by Control
PLA
ROM
RC
MRC
Clock
Generator
CF
PC
X’tal
Bus Interface
ACC
SIO0
Port 0
B Register
SIO1
Port 1
C Register
Timer 0
(high-speed clock counter)
Port 3
Timer 1
Port 7
Base Timer
Port 8
PSW
LCD Controller
ADC
RAR
INT0 to 5
Noise Rejection Filter
Weak Signal
Detector
RAM
Timer 4
Timer 6
Stack Pointer
Timer 5
Timer 7
ALU
Watchdog Timer
No.7776-7/22
LC877448A/40A/32A/24A
Pin Description
Pin name
VSS1,
VSS2,
I/O
Function
Option
-
• Power supply (-)
No
-
• Power supply (+)
No
• 8 bit input / output port
Yes
VSS3
VDD1,
VDD2,
VDD3
PORT 0
I/O
P00 to P07
• Data direction programmable in nibble units
• Use of pull-up resistor can be specified in nibble units
• Input for HOLD release
• Input for port 0 interrupt
PORT 1
I/O
P10 to P17
• 8 bit input / output port
Yes
• Data direction programmable for each bit
• Use of pull-up resistor can be specified for each bit individually
• Other pin functions
P10: SIO0 data output
P11: SIO0 data input or bus input / output
P12: SIO0 clock input / output
P13: SIO1 data output
P14: SIO1 data input or bus input / output
P15: SIO1 clock input / output
P16: Timer 1 PWML output
P17: Timer 1 PWMH output / Buzzer output
PORT 3
I/O
P30 to P35
• 6 bit input / output port
Yes
• Data direction can be specified for each bit
• Use of pull-up resistor can be specified for each bit individually
• Other functions
P30 to P33: INT4 input / HOLD release input / Timer 1 event input /
Timer 0L capture input / Timer 0H capture input
P34 to P35: INT5 input / HOLD release input / Timer 1 event input /
Timer 0L capture input / Timer 0H capture input
• Interrupt detection selection
PORT 7
I/O
P70 to P73
Rising
Falling
Rising and falling
H level
L level
INT4
Yes
Yes
Yes
No
No
INT5
Yes
Yes
Yes
No
No
• 4 bit input / output port
No
• Data direction can be specified for each bit
• Use of pull-up resistor can be specified for each bit individually
• Other functions
P70: INT0 input / HOLD release input / Timer 0L capture input / output for watchdog
timer
P71: INT1 input / HOLD release input / Timer 0H capture input
P72: INT2 input / HOLD release input / Timer 0 event input / Timer 0L capture input
P73: INT3 input (noise rejection filter attached) / Timer 0 event input / Timer 0H
capture input
AD input port: AN8 (P70), AN9 (P71)
• Interrupt detection selection
PORT 8
P80 to P87
I/O
Rising
Falling
Rising and falling
H level
L level
INT0
Yes
Yes
No
Yes
Yes
INT1
Yes
Yes
No
Yes
Yes
INT2
Yes
Yes
Yes
No
No
INT3
Yes
Yes
Yes
No
No
• 8 bit input / output port
No
• Input / output can be specified for each bit individually
• Other functions:
AD input ports: AN0 to AN7
Small signal detector input port: MICIN (P87)
Continued on next page.
No.7776-8/22
LC877448A/40A/32A/24A
Continued from preceding page.
Pin name
I/O
S0 / PA0 to
I/O
• Segment output for LCD
I/O
• Segment output for LCD
S7 / PA7
S8 / PB0 to
I/O
I/O
I/O
I/O
No
• Segment output for LCD
No
• Segment output for LCD
No
• Can be used as general purpose input / output port (PF)
I/O
COM3 / PL3
V1 / PL4 to
• Segment output for LCD
• Can be used as general purpose input / output port (PE)
S47 / PF7
COM0 / PL0 to
No
• Can be used as general purpose input / output port (PD)
S39 / PE7
S40 / PF0 to
• Segment output for LCD
• Can be used as general purpose input / output port (PC)
S31 / PD7
S32 / PE0 to
No
• Can be used as general purpose input / output port (PB)
S23 / PC7
S24 / PD0 to
Option
No
• Can be used as general purpose input / output port (PA)
S15 / PB7
S16 / PC0 to
Function
• Common output for LCD
No
• Can be used as general purpose input port (PL)
I/O
V3 / PL6
• LCD output bias power supply
No
• Can be used as general purpose input port (PL)
• Other functions:
AD input ports: AN12 to AN14
RES
I
Reset terminal
No
XT1
I
• Input for 32.768kHz crystal oscillation
No
• Other functions:
General purpose input port
AD input port: AN10
• When not in use, connect to VDD1
XT2
I/O
• Output for 32.768kHz crystal oscillation
No
• Other functions:
General purpose input port
AD input port: AN11
• When not in use, set to oscillation mode and leave open
CF1
I
Input terminal for ceramic oscillator
No
CF2
O
Output terminal for ceramic oscillator
No
Port Configuration
Port form and pull-up resistor options are shown in the following table.
Port status can be read even when port is set to output mode.
Option applies to:
Options
P00 to P07
Terminal
each bit
1
P10 to P17
each bit
Output form
Pull-up resistor
CMOS
Programmable (Note 1)
2
Nch-open drain
None
1
CMOS
Programmable
2
Nch-open drain
Programmable
each bit
1
CMOS
Programmable
2
Nch-open drain
None
P70
-
None
Nch-open drain
Programmable
P71 to P73
-
None
CMOS
Programmable
P80 to P87
-
None
Nch-open drain
None
S0 / PA0 to
-
None
CMOS
Programmable
-
None
Input only
None
-
None
Input only
None
XT1
-
None
Input only
None
XT2
-
None
Output for 32.768kHz crystal oscillation
None
P30 to P35
S47 / PF7
COM0 / PL0 to
COM3 / PL3
V1 / PL4 to
V3 / PL6
Note 1 Attachment of Port 0 programmable pull-up resistors is controllable in nibble units (P00 to 03, P04 to 07).
No.7776-9/22
LC877448A/40A/32A/24A
*Note 1: Connect as follows to reduce noise on VDD.
VSS1, VSS2 and VSS3 must be connected together and grounded.
*Note 2: The power supply for the internal memory is VDD1 but it uses the VDD3 as the power supply for ports.
When the VDD3 is not backed up, the port level does not become “H” even if the port latch is in the “H” level.
Therefore, when the VDD3 is not backed up and the port latch is “H” level, the port level is unstable in the
HOLD mode, and the back up time becomes shorter because the through current runs from VDD to GND in
the input buffer.
If VDD3 is not backed up, output “L” by the program or pull the port to “L” by the external circuit in the
HOLD mode so that the port level becomes “L” level and unnecessary current consumption is prevented.
LSI
VDD1
Power
supply
Back-up capacitors *2
VDD2
VDD3
VSS1 VSS2 VSS3
Absolute Maximum Ratings / Ta=25°C, VSS1=VSS2=VSS3=0V
Parameter
Symbol
Pins
Conditions
VDD [V]
min
typ
max
unit
Supply voltage
VDD max
VDD1, VDD2, VDD3
VDD1=VDD2=VDD3
-0.3
+7.0
Supply voltage
VLCD
V1 / PL4, V2 / PL5,
VDD1=VDD2=VDD3
-0.3
VDD
-0.3
VDD
+0.3
-0.3
VDD
+0.3
for LCD
Input voltage
V3 / PL6
VI
Port L
XT1, XT2, CF1, RES
Input / Output
VIO1
voltage
•Port 0, 1, 3, 7, 8
•Port A, B, C, D, E, F
V
[High level output current]
Peak output current
IOPH1
Port 0, 1, 3
•CMOS output selected
•Current at each pin
Total output current
-10
IOPH2
Port 71, 72, 73
Current at each pin
-3
IOPH3
Port A, B, C, D, E, F
Current at each pin
-5
∑IOAH1
Port 0, 1, 32, 33, 34, 35
Total of all pins
-40
∑IOAH2
Port 30, 31
Total of all pins
-10
∑IOAH3
Port 7
Total of all pins
-5
∑IOAH4
Port A, B, C
Total of all pins
-25
∑IOAH5
Port D, E, F
Total of all pins
-25
mA
[Low level output current]
Peak output current
Total output current
Maximum power
IOPL1
Port 0, 1, 32 to 35
Current at each pin
20
IOPL2
Port 30, 31
Current at each pin
30
IOPL3
Port 7, 8
Current at each pin
5
IOPL4
Port A, B, C, D, E, F
Current at each pin
15
∑IOAL1
Port 0, 1, 32, 33, 34, 35
Total of all pins
60
∑IOAL2
Port 30, 31
Total of all pins
60
∑IOAL3
Port 7, 8
Total of all pins
20
∑IOAL4
Port A, B, C
Total of all pins
40
∑IOAL5
Port D, E, F
Total of all pins
40
QIP100E
Ta = -30 to +70°C
Pd max
consumption
Operating
Topr
temperature range
Storage
temperature range
471
TQFP100
Tstg
362
-30
+70
-55
+125
mA
mW
°C
No.7776-10/22
LC877448A/40A/32A/24A
Recommended Operating Range / Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V
Parameter
Symbol
Operating supply
VDD1
voltage range
VDD2
Supply voltage
VHD
Pins
VDD1=VDD2=VDD3
VDD1
range in Hold mode
Input high voltage
Conditions
VDD [V]
•Port 0, 3, 8
•Port 1
2.5
6.0
2.0
6.0
Keep RAM and register
Output disable
2.5 to 6.0
Output disable
2.5 to 6.0
•P70 port input / interrupt
Port 87 small signal
Output disable
input
VIH4
Port 70
Output disable
Watchdog timer
Input low voltage
VIH5
XT1, XT2, CF1, RES
VIL1
•Port 0, 3, 8
•Port 1
0.3VDD
VDD
+0.7
0.3VDD
VDD
+0.7
2.5 to 6.0
0.75VD
2.5 to 6.0
0.9VDD
2.5 to 6.0
0.75VD
2.5 to 6.0
VSS
2.5 to 6.0
VSS
2.5 to 6.0
VSS
2.5 to 6.0
VSS
VDD
D
VDD
V
VDD
D
Output disable
•Port A, B, C, D, E, F, L
VIL2
0.15VD
D
+0.4
Output disable
•Port 71, 72, 73
0.1VDD
+0.4
•P70 port input / interrupt
VIL3
Port 87 small signal
Output disable
input
VIL4
Port 70
Output disable
Watchdog timer
VIL5
Operation
XT1, XT2, CF1, RES
tCYC
cycle time
External system
FEXCF1
CF1
clock frequency
unit
0.735µs ≤ tCYC ≤ 200µs
•Port 71, 72, 73
VIH3
max
6.0
•Port A, B, C, D, E, F, L
VIH2
typ
4.5
data in HOLD mode
VIH1
min
0.294µs ≤ tCYC ≤ 200µs
0.25VD
D
0.8VDD
-1.0
0.25VD
2.5 to 6.0
VSS
4.5 to 6.0
0.294
D
200
2.5 to 6.0
0.735
200
4.5 to 6.0
0.1
10
2.5 to 6.0
0.1
4
4.5 to 6.0
0.2
20
2.5 to 6.0
0.2
8
µs
•CF2 open
•system clock divider :
1/1
•external clock DUTY =
50±5%
•CF2 opent
•system clock divider :
1/2
Oscillation
FmCF1
CF1, CF2
frequency range
10MHz ceramic
resonator oscillation
(Note 1)
4.5 to 6.0
10
2.5 to 6.0
4
MHz
Refer to figure 1
FmCF2
CF1, CF2
4MHz ceramic resonator
oscillation
Refer to figure 1
FmRC
RC oscillation
FmMRC
Frequency variable RC
oscillation source
2.5 to 6.0
0.3
1.0
2.5 to 6.0
50
2.5 to 6.0
32.768
2.0
oscillation
FsX’tal
XT1, XT2
32.768kHz crystal
resonator oscillation
kHz
Refer to figure 2
(Note 1) The port value of oscillation circuit is shown in table 1 and table 2.
No.7776-11/22
LC877448A/40A/32A/24A
Electrical Characteristics / Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V
Parameter
High level
Symbol
IIH1
input current
Pins
Conditions
•Port 0, 1, 3, 7, 8
•Output disabled
•Port A, B, C, D, E, F, L
•Pull-up resister OFF
•VIN=VDD
(including OFF state
VDD [V]
min
typ
max
unit
2.5 to 6.0
1
2.5 to 6.0
1
2.5 to 6.0
1
15
leak
current of the output Tr.)
IIH2
RES
VIN=VDD
IIH3
XT1, XT2
When configured as an
input port
VIN=VDD
Low level
IIH4
CF1
VIN=VDD
2.5 to 6.0
IIH5
P87 / AN7 / MICIN
small signal input
VIN=VBIS + 0.5V
(VBIS : Bias voltage)
2.5 to 6.0
•Port 0, 1, 3, 7, 8
•Output disabled
•Port A, B, C, D, E, F, L
•Pull-up resister OFF
IIL1
input current
•VIN=VSS
(including OFF state
4.2
8.5
15
µA
2.5 to 6.0
-1
2.5 to 6.0
-1
2.5 to 6.0
-1
leak current of the output
Tr.)
IIL2
RES
VIN=VSS
IIL3
XT1, XT2
When configured as an
input port
VIN=VSS
High level
output voltage
IIL4
CF1
VIN=VSS
2.5 to 6.0
-15
IIL5
P87 / AN7 / MICIN
small signal input
VIN=VBIS - 0.5V
(VBIS : Bias voltage)
2.5 to 6.0
-15
VOH1
Port 0, 1, 3 : CMOS
IOH=-1.0mA
4.5 to 6.0
VDD-1
VOH2
output option
IOH=-0.1mA
2.5 to 6.0
VDD-0.5
VOH3
Port 7
IOH=-0.4mA
2.5 to 6.0
VDD-1
VOH4
Port A, B, C, D, E, F
IOH=-1.0mA
4.5 to 6.0
VDD-1
IOH=-0.1mA
2.5 to 6.0
VDD-0.5
IOL=10mA
4.5 to 6.0
1.5
IOL=1.6mA
2.5 to 6.0
0.4
VOH5
Low level
VOL1
output voltage
VOL2
Port 0, 1, 3
-4.2
VOL3
Port 30, 31
IOL=30mA
4.5 to 6.0
1.5
VOL4
Port 7, 8
IOL=1mA
4.5 to 6.0
0.4
IOL=0.5mA
2.5 to 6.0
0.4
IOL=8mA
4.5 to 6.0
1.5
IOL=1.4mA
2.5 to 6.0
0.4
VOL5
VOL6
Port A, B, C, D, E, F
VOL7
LCD output voltage
-8.5
VODLS
S0 to S47
regulation
IO=0mA
VLCD, 2/3VLCD,
1/3VLCD level output
2.5 to 6.0
0
±0.2
2.5 to 6.0
0
±0.2
V
Refer to figure 8
VODLC
COM0 to COM3
IO=0mA
VLCD, 2/3VLCD,
1/2VLCD, 1/3VLCD
level output
Refer to figure 8
LCD bias resistor
RLCD1
Resistance per one bias
Refer to figure 8
resistor
RLCD2
•Resistance per one
2.5 to 6.0
60
2.5 to 6.0
30
Refer to figure 8
bias resistor
kΩ
•1/2R mode
Resistance of
Rpu
pull-up MOS Tr.
Hysterisis voltage
•Port 0, 1, 3, 7
•Port A, B, C, D, E, F
VHIS1
•Port 1, 7
• RES
VHIS2
Port 87 small signal
input
VOH=0.9VDD
4.5 to 6.0
15
40
70
2.5 to 4.5
25
70
150
2.5 to 6.0
0.1VDD
2.5 to 6.0
0.1VDD
V
Continued on next page.
No.7776-12/22
LC877448A/40A/32A/24A
Continued from preceding page.
Parameter
Pin capacitance
Symbol
CP
Pins
All pins
Conditions
VDD [V]
min
typ
max
unit
•All other terminals
connected to VSS.
•f=1MHz
2.5 to 6.0
10
pF
•Ta=25°C
Input sensitivity
Vsen
Port 87 small signal
2.5 to 6.0
input
0.12VD
Vp-p
D
Serial Input / Output Characteristics / Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V
Parameter
Symbol
Pins
Conditions
VDD [V]
min
typ
max
unit
[Serial clock]
[Input clock]
Cycle time
tSCK1
Low level pulse
tSCKL1
width
tSCKLA1
High level pulse
tSCKH1
width
tSCKHA1
Cycle time
tSCK2
Low level pulse
tSCKL2
SCK0(P12)
Refer to figure 6
2/3
2.5 to 6.0
2/3
2/3
5
SCK1(P15)
Refer to figure 6
tCYC
2
2.5 to 6.0
width
High level pulse
4/3
tSCKH2
1
1
width
[Output clock]
Cycle time
tSCK3
Low level pulse
tSCKL3
width
tSCKLA2
High level pulse
tSCKH3
width
tSCKHA2
Cycle time
tSCK4
Low level pulse
tSCKL4
SCK0(P12)
•CMOS output
tCYC
1/2
2.5 to 6.0
3/4
tSCK
1/2
2
SCK1(P15)
•CMOS output
2
•Refer to figure 6
tCYC
1/2
2.5 to 6.0
width
High level pulse
4/3
•Refer to figure 6
tSCK
tSCKH4
1/2
width
[Serial input]
Data set-up time
tsDI
SI0(P11), SI1(P14),
SB0(P11), SB1(P14)
Data hold time
thDI
•Measured with respect
4.5 to 6.0
0.03
to SIOCLK leading
2.5 to 6.0
0.1
edge
4.5 to 6.0
0.03
2.5 to 6.0
0.1
•Refer to figure 6
µs
[Serial output]
Output delay time
tdDO
SO0(P10), SO1(P13),
•When port is open
SB0(P11), SB1(P14)
drain: Time delay
1/3tCY
4.5 to 6.0
C
from SIOCLK trailing
+0.05
edge to the SO data
1/3tCY
change
•Refer to figure 6
2.5 to 6.0
µs
C
+0.25
No.7776-13/22
LC877448A/40A/32A/24A
Pulse Input Conditions / Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V
Parameter
Symbol
Pins
High / low level
tPIH1
INT0(P70),
pulse width
tPIL1
INT1(P71),
INT2(P72),
INT4(P30 to P33),
INT5(P34 to P35)
tPIH2
INT3(P73)
tPIL2
(Noise rejection ratio is
1/1.)
Conditions
VDD [V]
min
typ
max
unit
•Condition that interrupt
is accepted
•Condition that event
2.5 to 6.0
1
2.5 to 6.0
2
2.5 to 6.0
64
2.5 to 6.0
256
2.5 to 6.0
1
2.5 to 6.0
200
input to timer 0 or 1 is
accepted
•Condition that interrupt
is accepted
•Condition that event
input to timer 0 is
accepted
tPIH3
INT3(P73)
tPIL3
(Noise rejection ratio is
1/32.)
•Condition that interrupt
tCYC
is accepted
•Condition that event
input to timer 0 is
accepted
tPIH4
INT3(P73)
tPIL4
(Noise rejection ratio is
1/128.)
•Condition that interrupt
is accepted
•Condition that event
input to timer 0 is
accepted
tPIH5
MICIN(P87)
tPIL5
•Condition that signal is
accepted to small signal
detection counter
tPIL6
•Condition that reset is
RES
accepted
µs
AD Converter Characteristics / Ta=-30°C to + 70°C, VSS1=VSS2=VSS3=0V
Parameter
Symbol
Pins
Resolution
N
AN0(P80) to AN7(P87),
Absolute precision
ET
AN8(P70), AN9(P71),
Conversion time
TCAD
AN10(XT1), AN11(XT2),
AN12(V1), AN13(V2),
AN14(V3)
Conditions
VDD [V]
typ
3.0 to 6.0
(Note 2)
AD conversion time =
32 × tCYC
4.0 to 6.0
(ADCR2=0)
3.0 to 6.0
AD conversion time =
64 × tCYC
4.5 to 6.0
(ADCR2=1)
(Note 3)
3.0 to 6.0
VAIN
3.0 to 6.0
voltage range
Analog port input
IAINH
VAIN=VDD
3.0 to 6.0
current
IAINL
VAIN=VSS
3.0 to 6.0
max
unit
8
bit
±1.5
3.0 to 6.0
(Note 3)
Analog input
min
15.62
97.92
(tCYC=
(tCYC=
0.488µs)
3.06µs)
23.52
97.92
(tCYC=
(tCYC=
0.735µs)
3.06µs)
18.82
97.92
(tCYC=
(tCYC=
0.294µs)
1.53µs)
47.04
97.92
(tCYC=
(tCYC=
0.735µs)
1.53µs)
VSS
VDD
1
-1
LSB
µs
V
µA
(Note 2) Absolute precision does not include quantizing error (±1/2 LSB).
(Note 3) Conversion time means time from executing AD conversion instruction to loading complete digital value to
register.
No.7776-14/22
LC877448A/40A/32A/24A
Current Consumption Characteristics / Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V
Parameter
Current
Symbol
IDDOP1
consumption
Pins
VDD1=VDD2=VDD3
Conditions
VDD [V]
min
typ
max
unit
•FmCF=10MHz Ceramic
resonator oscillation
during normal
•FsX’tal=32.768kHz
operation
crystal oscillation
(Note 4)
•System clock: CF
10MHz oscillation
4.5 to 6.0
8.4
30
4.5 to 6.0
9.2
31
4.5 to 6.0
4.1
17
•Internal RC oscillation
stopped
•Frequency variable RC
oscillation stopped
•Divider : 1/1
IDDOP2
•CF1=20MHz external
clock
•FsX’tal=32.768kHz
crystal oscillation
•System clock: CF1
oscillation
•Internal RC oscillation
stopped
•Frequency variable RC
oscillation stopped
•Divider : 1/2
IDDOP3
•FmCF=4MHz Ceramic
resonator oscillation
•FsX’tal=32.768kHz
crystal oscillation
mA
•System clock: CF 4MHz
IDDOP4
oscillation
•Internal RC oscillation
stopped
•Frequency variable RC
2.5 to 4.5
2.0
11
4.5 to 6.0
0.9
10
2.5 to 4.5
0.4
6
4.5 to 6.0
1.9
12
2.5 to 4.5
1.4
8
oscillation stopped
•Divider : 1/1
IDDOP5
•FmCF=0Hz
(No oscillation)
•FsX’tal=32.768kHz
crystal oscillation
IDDOP6
•Frequency variable RC
oscillation stopped
•System clock: RC
oscillation
•Divider : 1/2
IDDOP7
•FmCF=0Hz
(No oscillation)
•FsX’tal=32.768kHz
crystal oscillation
•Internal RC oscillation
IDDOP8
stopped
•System clock: 1MHz
with frequency variable
RC oscillation
•Divider : 1/2
Continued on next page.
No.7776-15/22
LC877448A/40A/32A/24A
Continued from preceding page.
Parameter
Current
Symbol
IDDOP9
Pins
VDD1=VDD2=VDD3
consumption
Conditions
VDD [V]
min
typ
max
unit
•FmCF=0Hz
(No oscillation)
during normal
•FsX’tal=32.768kHz
operation
4.5 to 6.0
40
140
crystal oscillation
(Note 4)
•System clock:
µA
32.768kHz
IDDOP10
•Internal RC oscillation
stopped
•Frequency variable RC
2.5 to 4.5
16
60
4.5 to 6.0
3.7
12
4.5 to 6.0
4.1
13
4.5 to 6.0
1.8
6
2.5 to 4.5
1.0
5
4.5 to 6.0
500
1600
oscillation stopped
•Divider : 1/2
Current
IDDHALT1
consumption during
VDD1=VDD2=VDD3
HALT mode
•FmCF=10MHz Ceramic
HALT mode
resonator oscillation
(Note 4)
•FsX’tal=32.768kHz
crystal oscillation
•System clock: CF
10MHz oscillation
•Internal RC oscillation
stopped
•Frequency variable RC
oscillation stopped
•Divider : 1/1
IDDHALT2
HALT mode
•CF1=20MHz for
external clock
•FsX’tal=32.768kHz
crystal oscillation
•System clock: CF1
oscillation
mA
•Internal RC oscillation
stopped
•Frequency variable RC
oscillation stopped
•Divider : 1/2
IDDHALT3
HALT mode
•FmCF=4MHz Ceramic
resonator oscillation
•FsX’tal=32.768kHz
crystal oscillation
•System clock: CF 4MHz
IDDHALT4
oscillation
•Internal RC oscillation
stopped
•Frequency variable RC
oscillation stopped
•Divider : 1/1
IDDHALT5
HALT mode
•FmCF=0Hz
(Oscillation stop)
•FsX’tal=32.768kHz
crystal oscillation
IDDHALT6
µA
•Internal RC oscillation
stopped
•Frequency variable RC
2.5 to 4.5
250
1300
oscillation stopped
•Divider : 1/2
Continued on next page.
No.7776-16/22
LC877448A/40A/32A/24A
Continued from preceding page.
Parameter
Symbol
Current
IDDHALT7
Pins
Conditions
VDD [V]
min
typ
max
unit
HALT mode
VDD1=VDD2=VDD3
•FmCF=0Hz
consumption during
(No oscillation)
HALT mode
4.5 to 6.0
1500
3600
2.5 to 4.5
1250
3300
•FsX’tal=32.768kHz
(Note 4)
crystal oscillation
•Internal RC oscillation
IDDHALT8
stopped
•System clock: 1MHz
with frequency variable
RC oscillation
•Divider : 1/2
IDDHALT9
µA
HALT mode
•FmCF=0Hz
(Oscillation stop)
•FsX’tal=32.768kHz
4.5 to 6.0
25
100
2.5 to 4.5
12
60
4.5 to 6.0
0.05
25
2.5 to 4.5
0.015
20
4.5 to 6.0
20
90
2.5 to 4.5
8
50
crystal oscillation
•System clock:
32.768kHz
IDDHALT10
•Internal RC oscillation
stopped
• Frequency variable RC
oscillation stopped
•Divider : 1/2
Current
IDDHOLD1
VDD1
HOLD mode
consumption during
HOLD mode
•CF1=VDD or open
(when using external
IDDHOLD2
clock)
Current
IDDHOLD3
VDD1
Date / time clock HOLD
consumption during
mode
Date / time clock
•CF1=VDD or open
HOLD mode
µA
(when using external
IDDHOLD4
clock)
•FmX’tal=32.768kHz
crystal oscillation
(Note 4) The currents through the output transistors and the pull-up MOS transistors are ignored.
Main system clock oscillation circuit characteristics
The characteristics in the table bellow is based on the following conditions:
1. Use the standard evaluation board SANYO has provided.
2. Use the peripheral parts with indicated value externally.
3. The peripheral parts value is a recommended value of oscillator manufacturer.
Table 1. Main system clock oscillation circuit characteristics using ceramic resonator
Frequency
10MHz
4MHz
Manufacturer
Murata
Murata
Circuit parameters
Operating supply
C1
C2
Rd1
voltage range
typ
max
[pF]
[pF]
[Ω]
[V]
[mS]
[mS]
CSTLS10M0G53-B0
(15)
(15)
220
4.5 to 6.0
0.04
0.2
Built-in C1, C2
CSTCE10M0G52-R0
(10)
(10)
330
4.5 to 6.0
0.04
0.2
Built-in C1, C2
CSTLS4M00G53-B0
(15)
(15)
820
2.5 to 6.0
0.04
0.2
Built-in C1, C2
CSTCR4M00G53-R0
(15)
(15)
820
2.5 to 6.0
0.6
0.3
Built-in C1, C2
Oscillator
Oscillation stabilizing time
Notes
The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than
minimum operating voltage. (Refer to Figure 4)
No.7776-17/22
LC877448A/40A/32A/24A
Subsystem clock oscillation circuit characteristics
The characteristics in the table bellow is based on the following conditions:
1. Use the standard evaluation board SANYO has provided.
2. Use the peripheral parts with indicated value externally.
3. The peripheral parts value is a recommended value of oscillator manufacturer.
Table 2. Subsystem clock oscillation circuit characteristics using crystal oscillator
Circuit parameters
Frequency
32.768kHz
Manufacturer
SEIKO EPSON
Oscillator
MC-306
Operating supply
C3
C4
Rf
Rd2
[pF]
[pF]
[Ω]
[kΩ]
18
18
OPEN
390
voltage range
[V]
2.5 to 6.0
Oscillation
stabilizing time
typ
max
[S]
[S]
1.1
3.0
Notes
Applicable
CL value = 12.5pF
The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which
starts the sub-clock oscillation or after releasing the HOLD mode. (Refer to Figure 4)
(Notes) • Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the
oscillation pins as possible with the shortest possible pattern length.
CF1
CF2
XT1
Rd1
XT2
Rf
Rd2
C1
CF
C2
C3
C4
X’tal
Figure 1 Ceramic oscillation circuit
Figure 2 Crystal oscillation circuit
0.5VDD
Figure 3 AC timing measurement point
No.7776-18/22
LC877448A/40A/32A/24A
VDD
Power Supply
VDD limit
0V
Reset time
RES
Internal RC
oscillation
tmsCF
CF1, CF2
tmsXtal
XT1, XT2
Operation mode
Reset
Unfixed
Instruction execution mode
Reset time and oscillation stable time
HOLD release
signal
Without HOLD
Release signal
HOLD release signal VALID
Internal RC
oscillation
tmsCF
CF1, CF2
tmsXtal
XT1, XT2
Operation mode
HOLD
HALT
HOLD release signal and oscillation stable time
Figure 4 Oscillation stabilizing time
No.7776-19/22
LC877448A/40A/32A/24A
VDD
(Note)
Select CRES and RRES value to assure that at
least 200µs reset time is generated after the
VDD becomes higher than the minimum
operating voltage.
RRES
RES
CRES
Figure 5 Reset circuit
SIOCLK
DATAIN
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM
transmission period
(only SIO0)
tSCK
tSCKL
tSCKH
SIOCLK
tsDI
thDI
DATAIN
tdDO
DATAOUT
Data RAM
transmission period
(only SIO0)
tSCKLA
tSCKHA
SIOCLK
tsDI
thDI
DATAIN
tdDO
DATAOUT
Figure 6 Serial input / output wave form
No.7776-20/22
LC877448A/40A/32A/24A
tPIL
tPIH
Figure 7 Pulse input timing
VDD
SW : ON / OFF (programmable)
RLCD
RLCD
SW : ON (VLCD=VDD)
RLCD
RLCD
VLCD
RLCD
RLCD
2/3VLCD
RLCD
1/2VLCD
RLCD
1/3VLCD
RLCD
RLCD
GND
Figure 8 LCD bias resistor
No.7776-21/22
LC877448A/40A/32A/24A
PS No.7776-22/22