SANYO LC877C64C

Ordering number : ENA0135
LC877C64C,LC877C56C
LC877C48C,LC877C40C
LC877C32C,LC877C24C
CMOS IC
Internal 64K/56K/48K/40K/32K/24K-byte ROM
and 2048/1536-byte RAM
8-bit 1-chip Microcontroller
Overview
The LC877C00 series are an 8-bit single chip microcontroller with the following on-chip functional blocks. :
• CPU: operable at a minimum bus cycle time of 83.3ns
• On-chip 64K-24K bytes ROM
• On-chip RAM: 2048/1536 bytes
• LCD controller / driver
• 16 bit timer/counters (can be divided into 8-bit units)
• 16 bit timer / PWM (can be divided into two 8-bit timers)
• Four 8-bit timer with prescalers
• Timer for use as date / time clock
• Synchronous serial I/O port (with automatic block transmit / receive function)
• Asynchronous / synchronous serial I/O port
• 2 channel 12bit PWM
• 12-channel × 8-bit AD converter
• High-speed clock counter
• System clock divider
• Small signal detector
• 20 source 10-vectored interrupt system
All of the above functions are fabricated on a single chip.
Features
„ROM
• 65536 × 8 bits
• 57344 × 8 bits
• 49152 × 8 bits
• 40960 × 8 bits
• 32768 × 8 bits
• 24576 × 8 bits
(LC877C64C)
(LC877C56C)
(LC877C48C)
(LC877C40C)
(LC877C32C)
(LC877C24C)
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before usingany SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
Ver.1.42
83006HKIM B8-9266 No.A0135-1/21
LC877C64C/56C/48C/40C/32C/24C
„RAM
• 2048 × 9 bits (LC877C64C/56C)
• 1536 × 9 bits (LC877C48C/40C/32C/24C)
„Minimum Instruction Cycle Time
• 250 ns (12MHz)
VDD=4.5 to 5.5V
• 300 ns (10MHz)
VDD=2.8 to 5.5V
• 750 ns (4MHz)
VDD=2.2 to 5.5V
„Ports
• Input/output ports
Data direction programmable for each bit individually:
20 (P1n, P70 to P73, P8n)
Data direction programmable in nibble units:
8 (P0n)
(When N-channel open drain output is selected, data can be input in bit units.)
• Input ports:
2 (XT1, XT2)
• Output ports:
2 (PWM2, PWM3)
• LCD ports
Segment output:
32 (S00 to S15, S24 to S39)
Common output:
4 (COM0 to COM3)
Bias terminals for LCD driver:
3 (V1 to V3)
Other functions
Input/output ports:
32 (PAn, PBn, PDn, PEn)
Input ports:
7 (PLn)
• Oscillator pins:
2 (CF1, CF2)
• Reset pin:
1 (RES)
• Power supply:
6 (VSS1-3, VDD1-3)
„LCD Controller
• Seven display modes are available (static, 1/2, 1/3, 1/4 duty × 1/2, 1/3 bias)
• Segment output and common output can be switched to general purpose input/output ports.
„Small Signal Detection (MIC signals etc)
• Counts pulses with the level which is greater than a preset value
• 2 bit counter
„Timers
• Timer 0: 16 bit timer / counter with capture register
Mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register
Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register
+ 8 bit Counter with 8-bit capture register
Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register
Mode 3: 16 bit counter with 16 bit capture register
• Timer 1: PWM / 16 bit timer/ counter with toggle output function
Mode 0: 8-bit timer with 8-bit prescaler (and toggle output) + 8-bit timer / counter with 8-bit prescaler
(and toggle output)
Mode 1: 2 channel 8-bit PWM with 8-bit prescaler
Mode 2: 16-bit timer / counter with 8-bit prescaler (and toggle output)
(Toggle output also possible using the lower order 8 bits)
Mode 3: 16-bit timer with 8-bit prescaler (and toggle output)
(The lower order 8 bits can be used as PWM output)
• Timer 4: 8-bit timer with 6-bit prescaler
• Timer 5: 8-bit timer with 6-bit prescaler
• Timer 6: 8-bit timer with 6-bit prescaler (and toggle output)
• Timer 7: 8-bit timer with 6-bit prescaler (and toggle output)
• Base Timer
1) The clock signal can be selected from any of the following :
Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0
2) Interrupts of five different time intervals are possible.
No.A0135-2/21
LC877C64C/56C/48C/40C/32C/24C
„High-speed Clock Counter
• Countable up to 20MHz clock (when using 10MHz main clock)
• Real time output
„SIO
• SIO 0: 8 bit synchronous serial interface
1) LSB first / MSB first is selectable
2) Internal 8 bit baud-rate generator (fastest clock period 4 / 3 tCYC)
3) Consecutive automatic data communication (1 to 256 bits)
• SIO 1: 8 bit asynchronous / synchronous serial interface
Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2 to 512 tCYC)
Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tCYC)
Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
„AD Converter: 8 bits × 12 channels
„PWM: 2 Channels Multi-frequency 12-bit PWM
„Remote Control Receiver Circuit (connected to P73 / INT3 / T0IN terminal)
• Noise rejection function (noise rejection filter’s time constant can be selected from 1 / 32 / 128 tCYC)
„Watchdog Timer
• The watching time period is determined by an external RC.
• Watchdog timer can produce interrupt or system reset
„Interrupts: 20 sources, 10 vectors
1) Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal
or lower priority interrupt request is postponed.
2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence.
In the case of equal priority levels, the vector with the lowest address takes precedence.
No.
Vector Address
Level
1
00003H
X or L
INT0
Interrupt Source
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L
4
0001BH
H or L
INT3/Base timer0 /Base timer1
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
SIO0
8
0003BH
H or L
SIO1
9
00043H
H or L
ADC/MIC/T6/T7
10
0004BH
H or L
Port 0/T4/T5/PWM2, PWM3
• Priority level: X > H > L
• For equal priority levels, vector with lowest address takes precedence.
„Subroutine Stack Levels: 1024 levels max (LC877C64C/56C)
768 levels max (LC877C48C/40C/32C/24C)
Stack is located in RAM.
No.A0135-3/21
LC877C64C/56C/48C/40C/32C/24C
„High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits
(12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits
(12 tCYC execution time)
„Oscillation Circuits
• On-chip RC oscillation for system clock use.
• CF oscillation for system clock use. (Rf built in, Rd external)
• Crystal oscillation low speed system clock use. (Rf built in, Rd external)
• On-chip frequency variable RC oscillation circuit for system clock use.
„System Clock Divider
• Low power consumption operation is available
• Minimum instruction cycle time (300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, 76.8µs can be switched
by program (when using 10MHz main clock)
„Standby Function
• HALT mode
HALT mode is used to reduce power consumption. During the HALT mode, program execution is stopped but
peripheral circuits keep operating (some parts of serial transfer operation stop).
1) Oscillation circuits are not stopped automatically.
2) Released by the system reset or interrupts.
• HOLD mode
HOLD mode is used to reduce power consumption. Program execution and peripheral circuits are stopped.
1) CF, RC, X’tal and multi-frequency RC oscillation circuits stop automatically.
2) Released by any of the following conditions.
(1) Low level input to the reset pin
(2) Specified level input to one of INT0, INT1, INT2
(3) Port 0 interrupt
• X’tal HOLD made
X’tal HOLD mode is used to reduce power consumption. Program execution is stopped.
All peripheral circuits except the base timer are stopped.
1) CF, RC and multi-frequency RC oscillation circuits stop automatically.
2) Crystal oscillator operation is kept in its state at HOLD mode inception.
3) Released by any of the following conditions
(1) Low level input to the reset pin
(2) Specified level input to one of INT0, INT1, INT2
(3) Port 0 interrupt
(4) Base-timer interrupt
„Package Form
• QFP80 (14 × 14):
• TQFP80J (12 × 12):
Lead-free type
Lead-free type
„Development Tools
• Evaluation chip:
• Emulator:
LC87EV690
EVA62S + ECB876600D + SUB877100 + POD80QFP(14 × 14) or POD80SQFP
ICE-B877300 + SUB877100 + POD80QFP(14 × 14) or POD80SQFP
• Flash ROM Version: LC87F7CC8A
No.A0135-4/21
LC877C64C/56C/48C/40C/32C/24C
Package Dimensions
Package Dimensions
unit : mm (typ)
3255
unit : mm (typ)
3290
17.2
14.0
12.0
60
40
80
21
41
61
40
80
21
0.65
0.25
20
1
(0.83)
0.125
(1.0)
1.2max
(2.7)
(1.25)
0.1
3.0max
20
0.2
0.5
0.15
0.1
1
12.0
14.0
17.2
61
0.5
41
14.0
60
0.8
14.0
SANYO : QFP80(14X14)
SANYO : TQFP80J(12X12)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
V1/PL4
V2/PL5
V3/PL6
S39/PE7
S38/PE6
S37/PE5
S36/PE4
S35/PE3
S34/PE2
S33/PE1
S32/PE0
S31/PD7
S30/PD6
S29/PD5
S28/PD4
S27/PD3
S26/PD2
S25/PD1
S24/PD0
S15/PB7
Pin Assignment
LC877C64C/
LC877C56C/
LC877C48C/
LC877C40C/
LC877C32C/
LC877C24C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P14/SI1/SB1
P15/SCK1
P16/T1PWML
P17/T1PWMH/BUZ
RES
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7/MICIN
P70/INT0/T0LCP/AN8
COM0/PL0
COM1/PL1
COM2/PL2
COM3/PL3
PWM2
VSS3
VDD3
PWM3
P00
P01
P02
P03
P04
P05
P06
P07
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VSS2
VDD2
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1/PA1
S0/PA0
P73/INT3/T0IN
P72/INT2/T0IN
P71/INT1/T0HCP/AN9
Top view
SANYO : QFP80 (14 × 14)
“Lead-free Type”
SANYO : TQFP80J (12 × 12) “Lead-free Type”
No.A0135-5/21
LC877C64C/56C/48C/40C/32C/24C
System Block Diagram
Interrupt control
IR
CF
RC
MRC
X’tal
ROM
Clock Generator
Stanby control
PLA
PC
SIO0
Bus interface
ACC
SIO1
Port 0
B register
Timer 0
(High speed clock counter)
Port 1
C register
Timer 1
Port 3
ALU
Base Timer
Port 8
LCD Controller
PWM
PSW
INT0 to 3
Noise Rejection Filter
ADC
RAR
Timer 4
Weak Signal
Detector
RAM
Timer 5
Timer 6
Stack pointer
Timer 7
Watchdog timer
No.A0135-6/21
LC877C64C/56C/48C/40C/32C/24C
Pin Description
Pin name
I/O
Function
Option
VSS1, VSS2,
VSS3
-
• Power supply (-)
No
VDD1, VDD2
VDD3
-
• Power supply (+)
No
• 8bit input/output port
Yes
PORT0
I/O
P00 to P07
• Data direction programmable in nibble units
• Use of pull-up resistor can be specified in nibble units
• Input for HOLD release
• Input for port 0 interrupt
• Other functions
P05: clock output (system clock / can selected from sub clock)
P06: timer 6 toggle output
P07: timer 7 toggle output
PORT1
I/O
P10 to P17
Yes
• 8bit input/output port
• Data direction programmable for each bit
• Use of pull-up resistor can be specified for each bit individually
• Other pin functions
P10 SIO0 data output
P11 SIO0 data input or bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input or bus input/output
P15 SIO1 clock input/output
P16: Timer 1 PWML output
P17: Timer 1 PWMH output/Buzzer output
PORT7
P70 to P73
I/O
• 4bit Input/output port
No
• Data direction can be specified for each bit
• Use of pull-up resistor can be specified for each bit individually
• Other functions
P70: INT0 input/HOLD release input/Timer0L capture input/output for watchdog timer
P71: INT1 input/HOLD release input/Timer0H capture input
P72: INT2 input/HOLD release input/timer 0 event input/Timer0L capture input
P73: INT3 input(noise rejection filter attached)/timer 0 event input/Timer0H capture input
AD input port: AN8(P70), AN9(P71)
• Interrupt detection selection
Rising
Falling
INT0
enable
enable
INT1
enable
enable
INT2
enable
INT3
enable
Rising and
H level
L level
disable
enable
enable
disable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
falling
Continued on next page.
No.A0135-7/21
LC877C64C/56C/48C/40C/32C/24C
Continued from preceding page.
Pin name
PORT8
I/O
I/O
P80 to P87
Function description
• 8bit Input/output port
Option
No
• Input/output can be specified for each bit individually
• Other functions:
AD input port: AN0 to AN7
Small signal detector input port: MICIN(P87)
S0/PA0 to
I/O
S7/PA7
S8/PB0 to
I/O
I/O
I/O
• Segment output for LCD
No
• Segment output for LCD
No
• Can be used as general purpose input/output port (PE)
I/O
COM3/PL3
V1/PL4 to
No
• Can be used as general purpose input/output port (PD)
S39/PE7
COM0/PL0 to
• Segment output for LCD
• Can be used as general purpose input/output port (PB)
S31/PD7
S32/PE0 to
No
• Can be used as general purpose input/output port (PA)
S15/PB7
S24 /PD0 to
• Segment output for LCD
• Common output for LCD
No
• Can be used as general purpose input port (PL)
I/O
V3/PL6
• LCD output bias power supply
No
• Can be used as general purpose input port (PL)
PWM2
O
PWM2 output port
No
PWM3
RES
O
PWM3 output port
No
I
Reset terminal
XT1
No
I
• Input for 32.768kHz crystal oscillation
No
• Other functions:
General-purpose input port
AD input port: AN10
• When not in use, connect to VDD1
XT2
I/O
• Output for 32.768kHz crystal oscillation
No
• Other functions:
General purpose input port
AD input port: AN11
• When not in use, set to oscillation mode and leave open
CF1
I
Input terminal for ceramic oscillator
No
CF2
O
Output terminal for ceramic oscillator
No
No.A0135-8/21
LC877C64C/56C/48C/40C/32C/24C
Port Output Types
Port form and pull-up resistor options are shown in the following table.
Port status can be read even when port is set to output mode.
Port Name
Option Selected
in Units of
Option Type
P00 to P07
each bit
1
P10 to P17
each bit
2
Output Type
Pull-up Resistor
CMOS
Programmable (Note 1)
2
Nch-open drain
None
1
CMOS
Programmable
Nch-open drain
Programmable
Programmable
P70
-
None
Nch-open drain
P71 to P73
-
None
CMOS
Programmable
P80 to P87
-
None
Nch-open drain
None
S0/PA0 to S15/PB7
-
None
CMOS
Programmable
-
None
Input only
None
None
S24/PD7 to S39/PE7
COM0/PL0 to
COM3/PL3
V1/PL4 to V3/PL6
-
None
Input only
PWM2, PWM3
-
None
CMOS
None
XT1
-
None
Input only
None
XT2
-
None
Output for 32.768kHz crystal oscillation
None
Note 1: Attachment of Port0 programmable pull-up resistors is controllable in nibble units (P00 to 03, P04 to 07).
*1: Connect as follows to reduce noise on VDD.
VSS1, VSS2 and VSS3 must be connected together and grounded.
*2: The power supply for the internal memory is VDD1 but it uses the VDD2 as the power supply for ports.
When the VDD2 is not backed up, the port level does not become “H” even if the port latch is in the “H” level.
Therefore, when the VDD2 is not backed up and the port latch is “H” level, the port level is unstable in the HOLD
mode, and the back up time becomes shorter because the through current runs from VDD to GND in the input buffer.
If VDD2 is not backed up, output “L” by the program or pull the port to “L” by the external circuit in the HOLD
mode so that the port level becomes “L” level and unnecessary current consumption is prevented.
LSI
VDD1
Power
supply
Back-up capacitors *2
VDD2
VDD3
VSS1
VSS2 VSS3
No.A0135-9/21
LC877C64C/56C/48C/40C/32C/24C
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Supply voltage
VDD max
Supply voltage
VLCD
for LCD
Input voltage
Pin/Remarks
Conditions
VDD1, VDD2, VDD3
VDD1=VDD2=VDD3
V1/PL4, V2/PL5,
VDD1=VDD2=VDD3
V3/PL6
VI
Port L
XT1, XT2, CF1, RES
Input/Output
VIO(1)
voltage
Specification
VDD [V]
min
typ
max
-0.3
+6.5
-0.3
VDD
-0.3
VDD+0.3
-0.3
VDD+0.3
unit
V
• Ports 0, 1, 7, 8
• Ports A, B, D, E
• PWM2, PWM3
Peak
IOPH(1)
Ports 0,1
output
current
• CMOS output selected
• Current at each pin
IOPH(2)
Ports 71,72,73
Current at each pin
IOPH(3)
• Ports A, B, D, E
Current at each pin
High level output current
• PWM2, PWM3
Average
IOMH(1)
Ports 0,1
output
• CMOS output selected
• Current at each pin
current
IOMH(2)
Ports 71, 72, 73
Current at each pin
(Note 1-1)
IOMH(3)
• Ports A, B, D, E
Current at each pin
• PWM2, PWM3
Total
∑IOAH(1)
output
current
• Ports 0, 1
Total of all pins
• PWM2, PWM3
-10
-5
-5
-7.5
-3
-3
-25
∑IOAH(2)
Port 7
Total of all pins
-10
∑IOAH(3)
Ports A, B,
Total of all pins
-25
∑IOAH(4)
Ports D, E
Total of all pins
-25
∑IOAH(5)
Ports A, B, D, E
Total of all pins
-45
Peak
IOPL(1)
Ports 0, 1
Current at each pin
20
output
IOPL(2)
Ports 7,8
Current at each pin
10
IOPL(3)
• Ports A, B, D, E
Current at each pin
current
10
• PWM2, PWM3
Low level output current
mA
Average
IOML(1)
Ports 0, 1
Current at each pin
15
output
IOML(2)
Ports 7, 8
Current at each pin
7.5
IOML(3)
• Ports A, B, D, E
Current at each pin
current
(Note 1-1)
Total
∑IOAL(1)
output
current
Maximum power
• Ports 0, 1
Total of all pins
45
• PWM2, PWM3
∑IOAL(2)
Ports 7, 8
∑IOAL(3)
∑IOAL(4)
Total of all pins
15
Ports A, B
Total of all pins
45
Ports D, E
Total of all pins
45
∑IOAL(5)
Ports A, B, D, E
Total of all pins
80
Pd max
QFP80(14×14)
Ta = -30 to +70°C
consumption
Operating
7.5
• PWM2, PWM3
381
TQFP80J(12×12)
325
Topr
temperature
-30
+70
range
Storage
mW
°C
Tstg
temperature
-55
+125
range
Note 1-1: Average output current indicates average value for 100ms term.
No.A0135-10/21
LC877C64C/56C/48C/40C/32C/24C
Allowable Operating Range at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Specification
VDD [V]
typ
max
unit
VDD(1)
supply voltage
VDD(2)
0.294µs≤ tCYC≤ 200µs
2.8
5.5
VDD(3)
0.735µs≤ tCYC≤ 200µs
2.2
5.5
2.0
5.5
Supply
VHD
VDD1
0.245µs≤ tCYC≤ 200µs
min
Operating
range
VDD1=VDD2=VDD3
Conditions
4.5
Keep RAM and register data in
HOLD mode.
voltage range
5.5
in Hold mode
Input high
VIH(1)
voltage
• Ports 0, 8
Output disable
• Ports A, B, D, E, L
VIH(2)
• Port 1
2.2 to 5.5
0.3VDD
VDD
+0.7
Output disable
• Ports 71, 72, 73
2.2 to 5.5
• P70
0.3VDD
VDD
+0.7
port input/interrupt
VIH(3)
P87 small signal input
Output disable
VIH(4)
Port 70
Output disable
Watchdog timer
Input low
VIH(5)
XT1, XT2, CF1, RES
VIL(1)
• Ports 0, 8
voltage
Output disable
• Ports A, B, D, E, L
VIL(2)
VIL(3)
• Port 1
Output disable
• Ports 71, 72, 73
VIL(4)
• P70 port
input/interrupt
VIL(5)
Port 87 small signal
Output disable
Input
VIL(6)
Port 70
Output disable
Watchdog timer
VIL(7)
Operation
XT1, XT2, CF1, RES
tCYC
cycle time
(Note 2-1)
External
VDD
2.2 to 5.5
0.9VDD
VDD
2.2 to 5.5
0.75VDD
4.0 to 5.5
VSS
VDD
0.15VDD
2.2 to 4.0
VSS
4.0 to 5.5
VSS
2.2 to 4.0
VSS
0.2VDD
2.2 to 5.5
VSS
0.25VDD
2.2 to 5.5
VSS
2.8 to 5.5
VSS
0.25VDD
4.5 to 5.5
0.245
200
+0.4
0.1VDD
+0.4
0.8VDD
-1.0
2.8 to 5.5
0.294
200
2.2 to 5.5
0.735
200
4.5 to 5.5
0.1
12
• system clock divider :1/1
2.8 to 5.5
0.1
10
frequency
• external clock DUTY = 50 ± 5%
2.2 to 5.5
0.1
4
• CF2 open
4.5 to 5.5
0.2
24.4
• system clock divider :1/2
2.8 to 5.5
0.2
20
2.2 to 5.5
0.2
8
CF1, CF2
oscillation
range
See Fig. 1.
FmCF(2)
µs
MHz
12MHz ceramic resonator
frequency
(Note 2-2)
V
0.2VDD
• CF2 open
FmCF(1)
CF1
0.75VDD
system clock
Oscillation
FEXCF(1)
2.2 to 5.5
4.5 to 5.5
12
2.8 to 5.5
10
10MHz ceramic resonator
oscillation
See Fig. 1.
FmCF(3)
MHz
4MHz ceramic resonator
oscillation
2.2 to 5.5
4
See Fig. 1.
FmRC
RC oscillation
FmMRC
Frequency variable RC
oscillation source oscillation
FsX’tal
XT1, XT2
2.2 to 5.5
0.3
1.0
2.2 to 5.5
16
2.2 to 5.5
32.768
2.0
32.768kHz crystal resonator
oscillation
kHz
See Fig. 2.
Note 2-1: Oscillation frequency and Operation cycle time (tCYC) rerationship: 1/1divide-3/FmCF, 1/2divide-6/FmCF
Note 2-2: The parts value of oscillation circuit is shown in Table 1 and Table 2.
No.A0135-11/21
LC877C64C/56C/48C/40C/32C/24C
Electrical Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
High level input
Symbol
IIH(1)
current
Pin/Remarks
Conditions
• Ports 0, 1, 7, 8
• Output disabled
• Ports A, B, D,
• Pull-up resister OFF.
E, L
• PWM2, PWM3
• VIN=VDD
Specification
VDD [V]
min
typ
max
unit
2.2 to 5.5
1
2.2 to 5.5
1
2.2 to 5.5
1
2.2 to 5.5
15
(including OFF state leak current
of the output Tr.)
Low level input
IIH(2)
RES
VIN=VDD
IIH(3)
XT1, XT2
When configured as an
IIH(4)
CF1
input port. VIN=VDD
VIN=VDD
IIH(5)
P87/AN7/MICIN
IIL(1)
current
small signal input
VIN=VBIS+0.5V
(VBIS: Bias voltage)
• Ports 0, 1, 7, 8
• Output disabled
• Ports A, B, D,
• Pull-up resister OFF.
E, L
• PWM2, PWM3
• VIN=VSS
4.5 to 5.5
5
10
20
µA
2.2 to 5.5
-1
2.2 to 5.5
-1
2.2 to 5.5
-1
(including OFF state leak current
of the output Tr.)
IIL(2)
RES
VIN=VSS
IIL(3)
XT1,XT2
When configured as an
input port. VIN=VSS
High level output
voltage
IIL(4)
CF1
VIN=VSS
2.2 to 5.5
-15
IIL(5)
P87/AN7/MICIN
small signal input
VIN=VBIS-0.5V
(VBIS: Bias voltage)
4.5 to 5.5
-20
VOH(1)
Ports 0, 1: CMOS
IOH=-1.0mA
4.5 to 5.5
VDD-1
VOH(2)
output option
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
IOH=-0.2mA
2.2 to 5.5
VDD-0.4
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
IOH=-0.2mA
2.2 to 5.5
VDD-0.4
VOH(3)
VOH(4)
Port 7
VOH(5)
-10
-5
VOH(6)
• Ports A, B, D, E,
IOH=-1.0mA
4.5 to 5.5
VDD-1
VOH(7)
• PWM2, PWM3
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
IOH=-0.2mA
2.2 to 5.5
VDD-0.4
IOL=10mA
4.5 to 5.5
1.5
VOH(8)
Ports 0, 1
Low level output
VOL(1)
voltage
VOL(2)
IOL=1.6mA
3.0 to 5.5
0.4
VOL(3)
IOL=1.0mA
2.2 to 5.5
0.4
IOL=1.6mA
3.0 to 5.5
0.4
VOL(4)
Ports 7, 8
VOL(5)
LCD output voltage
IOL=1.0mA
2.2 to 5.5
0.4
VOL(6)
• Ports A, B, D, E,
IOL=1.6mA
3.0 to 5.5
0.4
VOL(7)
• PWM2, PWM3
IOL=1.0mA
2.2 to 5.5
0.4
VODLS
S0 to S15,
IO=0mA
S24 to S39
VLCD, 2/3VLCD, 1/3VLCD
regulation
level output
2.2 to 5.5
0
±0.2
2.2 to 5.5
0
±0.2
V
See Fig. 8.
VODLC
COM0 to COM3
IO=0mA
VLCD, 2/3VLCD, 1/2VLCD
1/3VLCD level output
See Fig. 8.
LCD bias resistor
RLCD(1)
Resistance per
See Fig. 8.
one bias resistor
RLCD(2)
• Resistance per
one bias resistor
2.2 to 5.5
60
2.2 to 5.5
30
kΩ
See Fig. 8.
• 1/2R mode
Continued on next page.
No.A0135-12/21
LC877C64C/56C/48C/40C/32C/24C
Continued from preceding page.
Parameter
Resistance of
Symbol
Rpu
• Ports 0, 1, 7
pull-up MOS Tr.
Hysterisis voltage
Pin/Remarks
Conditions
VOH=0.9VDD
• Ports A, B, D, E
VHYS(1)
• Ports 1, 7
• RES
VHYS(2)
Port 87 small
CP
All pins
VDD [V]
min
typ
max
4.5 to 5.5
15
35
80
2.2 to 4.5
18
50
150
2.2 to 5.5
0.1VDD
2.2 to 5.5
0.1VDD
2.2 to 5.5
10
unit
kΩ
V
signal input
Pin capacitance
Specification
• All Other Terminals Connected
To VSS.
• F=1MHz
pF
• Ta=25°C
Input sensitivity
Vsen
Port 87 small
2.2 to 5.5
signal input
0.12VDD
Vp-p
Serial Input/Output Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Input clock
Parameter
Symbol
Frequency
tSCK(1)
Low level
tSCKL(1)
Pin/Remarks
SCK0(P12)
Conditions
Specification
VDD [V]
See Fig. 6.
tSCKH(1)
pulse width
tSCKHA(1)
2.2 to 5.5
transmission/reception mode
tCYC
4
Output clock
• (Note 4-1-2)
Frequency
tSCK(2)
Low level
tSCKL(2)
SCK0(P12)
• CMOS output selected
4/3
• See Fig. 6.
1/2
pulse width
High level
tSCK
tSCKH(2)
1/2
2.2 to 5.5
pulse width
tSCKHA(2)
• Continuous data
tSCKH(2)
• CMOS output selected
+2tCYC
• See Fig. 6.
Data setup time
Serial input
unit
1
• Continuous data
transmission/reception mode
tsDI(1)
SB0(P11),
SI0(P11)
tSCKH(2)
+(10/3)
tCYC
tCYC
• Must be specified with respect
to rising edge of SIOCLK.
2.2 to 5.5
0.03
2.2 to 5.5
0.03
• See Fig. 6.
Data hold time
Output clock
Input clock
Output delay
Serial output
max
1
• See Fig. 6.
Serial clock
typ
2
pulse width
High level
min
thDI(1)
tdD0(1)
SO0(P10),
SB0(P11)
time
• Continuous data
transmission/reception mode
2.2 to 5.5
• (Note 4-1-3)
tdD0(2)
• Synchronous 8-bit mode
• (Note 4-1-3)
tdD0(3)
2.2 to 5.5
(1/3)tCYC
+0.05
µs
1tCYC
+0.05
(Note 4-1-3)
2.2 to 5.5
(1/3)tCYC
+0.15
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock
is "H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning
of output state change in open drain output mode. See Fig. 6.
No.A0135-13/21
LC877C64C/56C/48C/40C/32C/24C
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Input clock
Symbol
Frequency
tSCK(3)
Low level
tSCKL(3)
Pin/Remarks
SCK1(P15)
Conditions
min
See Fig. 6.
Frequency
SCK1(P15)
• CMOS output selected
tSCKL(4)
1
2
2.2 to 5.5
pulse width
High level
1/2
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
SB1(P14),
SI1(P14)
• Must be specified with respect
to rising edge of SIOCLK.
2.2 to 5.5
0.03
2.2 to 5.5
0.03
• See Fig. 6.
Data hold time
Output delay time
Serial output
tsDI(2)
unit
1
• See Fig. 6.
Low level
max
tCYC
tSCKH(3)
tSCK(4)
typ
2
2.2 to 5.5
pulse width
High level
Specification
VDD [V]
pulse width
Output clock
Serial clock
Parameter
thDI(2)
tdD0(4)
SO1(P13),
SB1(P14)
µs
• Must be specified with respect
to falling edge of SIOCLK.
• Must be specified as the
time to the beginning of
2.2 to 5.5
output state change in
(1/3)tCYC
+0.05
open drain output mode.
• See Fig. 6.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A0135-14/21
LC877C64C/56C/48C/40C/32C/24C
Pulse Input Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Conditions
High/low level
tPIH(1)
INT0(P70),
• Condition that interrupt is accepted
pulse width
tPIL(1)
INT1(P71),
• Condition that event input to
INT2(P72)
timer 0 is accepted
Specification
VDD [V]
min
typ
2.2 to 5.5
1
2.2 to 5.5
2
max
unit
INT4(P30 to P33)
INT5(P34 to P35)
tPIH(2)
INT3(P73)
• Condition that interrupt is accepted
tPIL(2)
(Noise rejection
• Condition that event input to
ratio is 1/1.)
timer 0 is accepted
tPIH(3)
INT3(P73)
• Condition that interrupt is accepted
tPIL(3)
(Noise rejection
• Condition that event input to
ratio is 1/32.)
INT3(P73)
• Condition that interrupt is accepted
tPIL(4)
(Noise rejection
• Condition that event input to
tPIL(5)
MICIN(P87)
tPIL(5)
tPIL(6)
64
2.2 to 5.5
256
2.2 to 5.5
1
2.2 to 5.5
200
timer 0 is accepted
• Condition that signal is accepted to
small signal detection counter.
RES
2.2 to 5.5
timer 0 is accepted
tPIH(4)
ratio is 1/128.)
tCYC
• Condition that reset is accepted
µs
AD Converter Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Resolution
N
AN0(P80) to
Absolute
ET
AN7(P87),
TCAD
AN9(P71),
AN10(XT1),
time
Specification
VDD [V]
typ
AD conversion time=32 × tCYC
(when ADCR2=0) (Note 6-2)
4.5 to 5.5
3.0 to 5.5
AD conversion time=64 × tCYC
(when ADCR2=1) (Note 6-2)
4.5 to 5.5
3.0 to 5.5
VAIN
3.0 to 5.5
voltage range
Analog port
IAINH
VAIN=VDD
3.0 to 5.5
input current
IAINL
VAIN=VSS
3.0 to 5.5
max
unit
8
bit
±1.5
3.0 to 5.5
AN11(XT2)
Analog input
min
3.0 to 5.5
(Note 6-1)
AN8(P70),
accuracy
Conversion
Conditions
15.62
97.92
(tCYC=
(tCYC=
0.488µs)
3.06µs)
23.52
97.92
(tCYC=
(tCYC=
0.735µs)
3.06µs)
18.82
97.92
(tCYC=
(tCYC=
0.294µs)
1.53µs)
47.04
97.92
(tCYC=
(tCYC=
0.735µs)
1.53µs)
VSS
VDD
LSB
1
-1
µs
V
µA
Note 6-1: Absolute precision does not include quantizing error (±1/2 LSB).
Note 6-2: Conversion time means time from executing AD conversion instruction to loading complete digital value
to register.
No.A0135-15/21
LC877C64C/56C/48C/40C/32C/24C
Consumption Current Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Current
Symbol
IDDOP(1)
Pin/
Conditions
Remarks
Specification
VDD [V]
min
typ
max
unit
• FmCF=12MHz Ceramic resonator oscillation
consumption
VDD1
=VDD2
• FsX’tal=32.768kHz crystal oscillation
during normal
=VDD3
• System clock: CF 12MHz oscillation
operation
• Frequency variable RC oscillation stopped
(Note 7-1)
• Internal RC oscillation stopped.
4.5 to 5.5
7
12
4.5 to 5.5
5.5
9
3.0 to 3.6
3.1
5.6
2.8 to 3.0
2.2
3.8
4.5 to 5.5
2.5
4
3.0 to 3.6
1.2
2.5
2.2 to 3.0
0.9
1.8
4.5 to 5.5
0.55
2.1
3.0 to 3.6
0.3
1.4
2.2 to 3.0
0.2
1
4.5 to 5.5
1.2
3.5
3.0 to 3.6
0.65
2.2
2.2 to 3.0
0.4
1.6
4.5 to 5.5
27
65
3.0 to 3.6
11
45
2.2 to 3.0
7
32
4.5 to 5.5
2.5
5.3
4.5 to 5.5
2
4.2
3.0 to 3.6
1.1
2.3
2.8 to 3.0
0.7
1.5
4.5 to 5.5
1.2
2.6
3.0 to 3.6
0.65
1.4
2.2 to 3.0
0.38
0.88
• Divider: 1/1
IDDOP(2)
• FmCF=10MHz Ceramic resonator oscillation
• FsX’tal=32.768kHz crystal oscillation
IDDOP(3)
• System clock: CF 10MHz oscillation
• Frequency variable RC oscillation stopped
IDDOP(4)
• Internal RC oscillation stopped.
• Divider: 1/1
IDDOP(5)
• FmCF=4MHz Ceramic resonator oscillation
• FsX’tal=32.768kHz crystal oscillation
IDDOP(6)
• System clock: CF 4MHz oscillation
• Internal RC oscillation stopped.
IDDOP(7)
• Frequency variable RC oscillation stopped
• Divider:1/1
IDDOP(8)
IDDOP(9)
IDDOP(10)
IDDOP(11)
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• Frequency variable RC oscillation stopped
• System clock: RC oscillation
• Divider:1/2
•FmCF=0Hz (No oscillation)
•FsX’tal=32.768kHz crystal oscillation
IDDOP(12)
•Internal RC oscillation stopped.
•System clock: 1MHz with frequency variable
IDDOP(13)
RC oscillation
•Divider:1/2
IDDOP(14)
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
IDDOP(15)
• System clock: 32.768kHz
• Internal RC oscillation stopped.
IDDOP(16)
• Frequency variable RC oscillation stopped
• Divider:1/2
Current
IDDHALT(1)
mA
µA
HALT mode
consumption
• FmCF=12MHz Ceramic resonator oscillation
during HALT
• FsX’tal=32.768kHz crystal oscillation
mode
• System clock: CF 12MHz oscillation
(Note 7-1)
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped
• Divider: 1/1
IDDHALT(2)
HALT mode
• FmCF=10MHz Ceramic resonator oscillation
IDDHALT(3)
• FsX’tal=32.768kHz crystal oscillation
• System clock: CF 10MHz oscillation
mA
• Internal RC oscillation stopped.
IDDHALT(4)
• Frequency variable RC oscillation stopped
• Divider: 1/1
IDDHALT(5)
HALT mode
• FmCF=4MHz Ceramic resonator oscillation
IDDHALT(6)
IDDHALT(7)
• FsX’tal=32.768kHz crystal oscillation
• System clock: CF 4MHz oscillation
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped
• Divider: 1/1
Note 7-1: The currents through the output transistors and the pull-up MOS transistors are ignored.
Continued on next page.
No.A0135-16/21
LC877C64C/56C/48C/40C/32C/24C
Continued from preceding page.
Parameter
Current
Symbol
IDDHALT(8)
consumption
during HALT
IDDHALT(9)
Pin/
VDD1
=VDD2
HALT mode
=VDD3
• FsX’tal=32.768kHz crystal oscillation
typ
max
3.0 to 3.6
0.15
0.7
2.2 to 3.0
0.1
0.5
4.5 to 5.5
1
2.9
3.0 to 3.6
0.55
1.8
2.2 to 3.0
0.35
1.4
4.5 to 5.5
19
50
3.0 to 3.6
6.2
30
2.2 to 3.0
3.6
20
HOLD mode
4.5 to 5.5
0.025
10
• CF1=VDD or open
3.0 to 3.6
0.015
7
2.2 to 3.0
0.009
6
4.5 to 5.5
16
45
3.0 to 3.6
5.5
25
2.2 to 3.0
3
15
HALT mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
IDDHALT(12)
min
1
• Divider: 1/2
IDDHALT(11)
VDD [V]
0.28
• Frequency variable RC oscillation stopped
IDDHALT(10)
Specification
4.5 to 5.5
• FmCF=0Hz (Oscillation stop)
• System clock: RC oscillation
mode
(Note 7-1)
Conditions
Remarks
• Internal RC oscillation stopped.
unit
mA
• System clock: 1MHz with frequency variable
IDDHALT(13)
RC oscillation
• Divider :1/2
HALT mode
IDDHALT(14)
• FmCF=0Hz (Oscillation stop)
• FsX’tal=32.768kHz crystal oscillation
IDDHALT(15)
• System clock: 32.768kHz
• Internal RC oscillation stopped.
IDDHALT(16)
• Frequency variable RC oscillation stopped
• Divider: 1/2
Current
IDDHOLD(1)
consumption
IDDHOLD(2)
during HOLD
mode
Current
IDDHOLD(3)
IDDHOLD(4)
consumption
during
(when using external clock)
Date/time clock HOLD mode
• CF1=VDD or open
IDDHOLD(5)
Date/time clock
HOLD mode
VDD1
(when using external clock)
• FmX’tal=32.768kHz crystal oscillation
IDDHOLD(6)
µA
Note 7-1: The currents through the output transistors and the pull-up MOS transistors are ignored.
No.A0135-17/21
LC877C64C/56C/48C/40C/32C/24C
Characteristics of a Sample Main System Clock Oscillation Circuit
The characteristics in the table bellow is based on the following conditions:
(1) Use the standard evaluation board SANYO has provided.
(2) Use the peripheral parts with indicated value externally.
(3) The peripheral parts value is a recommended value of oscillator manufacturer
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Nominal
Vendor
Frequency
Name
12MHz
MURATA
10MHz
MURATA
4MHz
MURATA
Circuit Constant
Oscillator Name
Operating
Oscillation
Voltage
Stabilization Time
Remarks
C1
C2
Rf1
Rd1
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[ms]
[ms]
CSTCE12M0G52-R0
(10)
(10)
Open
470
4.5 to 5.5
0.05
0.15
CSTCE10M0G52-R0
(10)
(10)
Open
1.0k
2.8 to 5.5
0.05
0.15
Internal
CSTLS10M0G53-B0
(15)
(15)
Open
680
2.8 to 5.5
0.05
0.15
C1, C2
Internal
C1, C2
CSTCR4M00G53-R0
(15)
(15)
Open
3.3k
2.2 to 5.5
0.05
0.15
Internal
CSTLS4M00G53-B0
(15)
(15)
Open
3.3k
2.2 to 5.5
0.05
0.15
C1, C2
The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than
minimum operating voltage (See Figure 4).
Characteristics of a Sample Subsystem Clock Oscillator Circuit
The characteristics in the table bellow is based on the following conditions:
(1) Use the standard evaluation board SANYO has provided.
(2) Use the peripheral parts with indicated value externally.
(3) The peripheral parts value is a recommended value of oscillator manufacturer
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal
Vendor Name
Frequency
Circuit Constant
Oscillator
Name
Operating
Oscillation
Voltage
Stabilization Time
C3
C4
Rf2
Rd2
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[s]
[s]
18
18
Open
560k
2.2 to 5.5
1.3
3.0
Remarks
Applicable
32.768kHz
SEIKO EPSON
MC-306
CL value
=12.5pF
The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which
starts the sub-clock oscillation or after releasing the HOLD mode (See Figure 4).
Note : Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to
the oscillation pins as possible with the shortest possible pattern length.
CF1
XT1
CF2
Rf1
C1
Rf2
Rd1
C2
XT2
C3
Rd2
C4
X’tal
CF
Figure 1 Ceramic Oscillator Circuit
Figure 2 Crystal Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A0135-18/21
LC877C64C/56C/48C/40C/32C/24C
VDD
Operating VDD
lower limit
0V
Power supply
Reset time
RES
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating mode
Reset
Unpredictable
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset signal
HOLD reset signal
absent
HOLD reset signal valid
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
No.A0135-19/21
LC877C64C/56C/48C/40C/32C/24C
VDD
RRES
Note :
Determine the value of CRES and RRES so that the
reset signal is present for a period of 200µs after the
supply voltage goes beyond the lower limit of the IC’s
operating voltage.
RES
CRES
Figure 5 Reset Circuit
SIOCLK :
DATAIN :
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DATAOUT :
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DI7
DI8
DO7
DO8
Data RAM
transfer period
(SIO0 only)
tSCK
tSCKH
tSCKL
SIOCLK :
tsDI
thDI
DATAIN :
tdDO
DATAOUT :
Data RAM
transfer period
(SIO0 only)
tSCKL
tSCKHA
SIOCLK :
tsDI
thDI
DATAIN :
tdDO
DATAOUT :
Figure 6 Serial I/O Output Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A0135-20/21
LC877C64C/56C/48C/40C/32C/24C
VDD
SW : ON/OFF (programmable)
RLCD
RLCD
SW : ON (VLCD=VDD)
RLCD
RLCD
VLCD
RLCD
RLCD
2/3VLCD
RLCD
1/2VLCD
RLCD
1/3VLCD
RLCD
RLCD
GND
Figure 8 LCD bias resistor
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PS No.A0135-21/21