SM5921A
8-channel Lip Sync Delay
OVERVIEW
The SM5921A is an SDRAM controller LSI for audio applications. It stores 64-fs slot 3-wire serial format
audio data input at sampling frequency fs in SDRAM, and can access data at an arbitrary address to add a delay
to each channel data. It also has a direct mute function to mute the audio data.
■
■
■
DQ5
DQ6
DQ7
WEN
CASN
RASN
CSN
BA
A10
A0
A1
A2
A3
VDD
45
44
43
42
41
40
39
38
37
36
35
34
33
24
A5
DQ11
58
23
A4
DQ10
59
22
DOD
DQ9
60
21
DOC
DQ8
61
20
DOB
WPOLN
62
19
DOA
OEN
63
18
TEST
VSS
64
17
VDD
VSS 16
57
RSTN 15
A6
DQ12
DMUTEN 14
25
TEST3 13
56
TEST2 12
A7
DQ13
SIO 11
26
SI 10
55
9
A8
DQ14
SCLK
27
8
54
XCS
A9
DQ15
7
28
DID
53
6
CKE
DQ0
DIC
29
5
52
DIB
CLKO
DQ1
4
30
DIA
51
PACKAGE DIMENSIONS
(Unit: mm)
Weight: 0.35g
Structure
■
DQ4
DQM
DQ2
3
VSS
31
BCKI
■
32
50
2
■
49
DQ3
1
■
VDD
VDD
■
■
System clock input
64fs (fs = 32 to 192kHz) bit clock
Sampling frequency: fs = 32 to 192kHz support
Data input/output
3-wire serial, 8-channel PCM
64 clock/slot, word clock polarity inversion
Direct mute function
MCU interface: 3-wire serial
Delay settings: sum of intrinsic delay and individual delay
• Intrinsic delay (common to all channels,
default = 0 samples, 16-sample units)
• Individual delay (independent for each channel,
default = 0 samples, 1-sample units)
Maximum delay values
1365.3ms @ fs = 48kHz
682.7ms @ fs = 96kHz
341.3ms @ fs = 192kHz
Address shift function: ×1, ×2, ×4 support
Delay time can be multiplied between ×1, ×2, or
×4 times without changing the delay set value.
SDRAM interface: 16M/64M/128M (×16 devices
supported)
Package: 64-pin QFP
WCKI
■
46
(Top view)
VSS
Functions
47
PINOUT
48
FEATURES
12 ± 0.4
10 ± 0.1
Silicon-gate CMOS
+ 0.075
0.125 − 0.
025
0.5 ± 0.2
Audio delay for multi-channel PCM signals
12 ± 0.4
■
10 ± 0.1
Applications
ORDERING INFORMATION
64-pin QFP
0 to 10
S
0.5
0.08 S
+ 0.09
0.18 − 0.05
1.7 MAX
SM5921AF
0.1
Package
1.4 ± 0.1
Device
Note. Dimensions without tolerance are reference values.
SEIKO NPC CORPORATION —1
SM5921A
BLOCK DIAGRAM
WPOLN WCKI BCKI DIA
DIB
DIC
DID
Input data interface
TEST
TEST2
Sequencer block
TEST3
CKE
Arithmetic
operation block
CLKO
DQM
RSTN
Address controller
A0 to A10
BA
DQ0 to DQ15
CSN
CASN
SDRAM interface
RASN
XCS
WEN
SCLK
MCU interface
SI
SIO
Output data interface
DOA
DOB
DOC
OEN
DMUTEN
DOD
PIN DESCRIPTION
Number
Name
I/O*1
1
VDD
–
Supply pin
2
WCKI
I
Word clock input
3
BCKI
I
Bit clock input (64fs)
4
DIA
I
Serial data input A
5
DIB
I
Serial data input B
6
DIC
I
Serial data input C
7
DID
I
Serial data input D
8
XCS
I
MCU latch enable input
Function
Setting
HIGH
LOW
9
SCLK
I
MCU clock input
10
SI
I
MCU data input
11
SIO
Ot
MCU data output
12
TEST2
Id
Test input pin
Test
13
TEST3
Id
Test input pin
Test
14
DMUTEN
Ip
Direct mute control
Mute
15
RSTN
Ip
Reset input pin
Reset
16
VSS
–
Ground pin
17
VDD
–
Supply pin
18
TEST
Id
Test input pin
19
DOA
Ot
Serial data output A
20
DOB
Ot
Serial data output B
21
DOC
Ot
Serial data output C
22
DOD
Ot
Serial data output D
Test
SEIKO NPC CORPORATION —2
SM5921A
Number
Name
I/O*1
23
A4
O
Address output A4
24
A5
O
Address output A5
25
A6
O
Address output A6
26
A7
O
Address output A7
27
A8
O
Address output A8
28
A9
O
Address output A9
29
CKE
O
SDRAM clock enable output
30
CLKO
O
SDRAM clock output (64fs)
31
DQM
O
DQM output
32
VSS
–
Ground pin
33
VDD
–
Supply pin
34
A3
O
Address output A3
35
A2
O
Address output A2
36
A1
O
Address output A1
37
A0
O
Address output A0
38
A10
O
Address output A10
Setting
Function
39
BA
O
Bank address output BA
40
CSN
O
CS output
41
RASN
O
RAS output
42
CASN
O
CAS output
43
WEN
O
WE output
44
DQ7
I/O
Data input/output DQ7
45
DQ6
I/O
Data input/output DQ6
46
DQ5
I/O
Data input/output DQ5
47
DQ4
I/O
Data input/output DQ4
48
VSS
–
Ground pin
49
VDD
–
Supply pin
50
DQ3
I/O
Data input/output DQ3
51
DQ2
I/O
Data input/output DQ2
52
DQ1
I/O
Data input/output DQ1
53
DQ0
I/O
Data input/output DQ0
54
DQ15
I/O
Data input/output DQ15
55
DQ14
I/O
Data input/output DQ14
56
DQ13
I/O
Data input/output DQ13
57
DQ12
I/O
Data input/output DQ12
58
DQ11
I/O
Data input/output DQ11
59
DQ10
I/O
Data input/output DQ10
60
DQ9
I/O
Data input/output DQ9
61
DQ8
I/O
Data input/output DQ8
62
WPOLEN
Ip
Word clock polarity control
63
OEN
Id
Data output enable control
64
VSS
–
Ground pin
HIGH
LOW
Inverted
Hi-Z
Output
*1. I: Input, I/O: Input/Output, O: Output, Ip: Input with pull-up resistor, Id: Input with pull-down resistor, Ot: Three-state output
SEIKO NPC CORPORATION —3
SM5921A
ABSOLUTE MAXIMUM RATINGS
VSS = 0V, VDD pin voltage = VDD
Parameter
Symbol
Supply voltage
Input voltage
Output voltage
Storage temperature
Power dissipation
Conditions
Rating
Unit
VDD
−0.3 to 4.6
V
VI
−0.3 to 5.5
V
VO
−0.3 to VDD + 0.3
V
TSTG
−55 to 125
°C
PW
120
mW
Note. Supply ratings apply both when switching power ON or OFF.
RECOMMENDED OPERATING CONDITIONS
VSS = 0V, VDD pin voltage = VDD
Rating
Parameter
Symbol
Conditions
Unit
min
typ
max
Supply voltage
VDD
3.0
3.3
3.6
V
Operating temperature
TOPR
−40
25
85
°C
ELECTRICAL CHARACTERISTICS
DC Characteristics
VSS = 0V, VDD = 3.0 to 3.6V, Ta = −40 to 85°C
Rating
Parameter
Pins
Symbol
Conditions
Unit
min
Current consumption
Input voltage
Output voltage
Input leakage current
max
18
30
VDD
IDD
(*1) (*2)
(*3) (*5)
VIH
2.0
VDD
VIL
0
0.8
VDD − 0.4
VDD
0
0.4
(*4) (*5)
(*1) (*5)
(*2)
Input current
(*3)
(*A)
typ
VOH
IOH = −2.0mA
VOL
IOL = 2.0mA
ILH
VIN = VDD
−1.0
1.0
ILL
VIN = 0V
−1.0
1.0
IIH1
VIN = VDD
−1.0
1.0
IIL1
VIN = 0V
−90.0
−33.0
−12.5
IIH2
VIN = VDD
12.5
33.0
90.0
IIL2
VIN = 0V
−1.0
mA
V
V
µA
µA
1.0
(*A) All output pins no load, system clock frequency fBCKI = 12.288MHz, input sampling frequency fs = 192kHz, supply voltage VDD = 3.6V
Note. See “Pin Classification” below for description of pins.
Pin classification
Symbol
Pin type
(*1)
Inputs
WCKI, BCKI, DIA, DIB, DIC, DID, XCS, SCLK, SI
Pin name
(*2)
Inputs
DMUTEN, WPOLN, RSTN
(*3)
Inputs
OEN, TEST, TEST2, TEST3
(*4)
Outputs
(*5)
Input/Outputs
DOA, DOB, DOC, DOD, RASN, CASN, CSN, A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, BA, WEN,
CLKO, CKE, DQM, SIO
DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7, DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, DQ15
SEIKO NPC CORPORATION —4
SM5921A
AC Characteristics
Serial inputs (WCKI, BCKI, DI* pins)
Rating
Parameter
Symbol
Conditions
Unit
min
typ
max
WCKI cycle time
tWCCY
5.2
20.8
32
µs
BCKI pulse cycle time
tBICY
81.25
325.5
500
ns
BCKI HIGH-level pulsewidth
tBICWH
32.5
130.2
320
ns
BCKI LOW-level pulsewidth
tBICWL
32.5
130.2
320
ns
DI* setup time
tDIS
20.0
ns
DI* hold time
tDIH
20.0
ns
Last BCKI rising edge → WCKI edge
tBWI
32.5
ns
WCKI edge → first BCKI rising edge
tWBI
32.5
ns
VIH
0.5VDD
WCKI
tBWI
tWBI
VIL
VIH
0.5VDD
BCKI
tBICWH
tBICWL
VIL
tBICY
VIH
0.5VDD
DI*
tDIS
tDIH
VIL
Note. DI*: DIA, DIB, DIC, DID pins
SEIKO NPC CORPORATION —5
SM5921A
Serial outputs (DO* pins)
Rating
Parameter
Symbol
Conditions
Unit
min
BCKI to output delay
typ
max
tBDL
CL = 15pF
0
20
ns
DI* to output delay
tDDL
Data-through (THROU = 1),
CL = 15pF
0
20
ns
Word boundary to enable time
tODL
OEN = H → L, CL = 15pF
0
30
ns
Word boundary to disable time
tOEZ
OEN = L → H, CL = 15pF
0
30
ns
VIH
0.5VDD
BCKI
VIL
VIH
0.5VDD
DI*
VIL
tDDL
VOH
0.5VDD
DO*
VOL
tBDL
VIH
0.5VDD
WCKI
VIL
VOH
0.5VDD
DO*
tODL
tOEZ
VOL
Note. DI*: DIA, DIB, DIC, DID pins
DO*: DOA, DOB, DOC, DOD pins
SEIKO NPC CORPORATION —6
SM5921A
SDRAM interface (CLKO, RASN, CASN, WEN, CSN, A0 to A10, DQ0 to DQ15 pins)
Rating
Parameter
Symbol
Conditions
Unit
min
typ
max
CLKO pulse cycle time
tCLKCY
CL = 15pF
1
tBICY
CLKO HIGH-level pulsewidth
tCLKOH
CL = 15pF
1/2
tBICY
CLKO LOW-level pulsewidth
tCLKOL
CL = 15pF
1/2
tBICY
tRASNH
CL = 15pF
RASN pulsewidth
CASN pulsewidth
WEN pulsewidth
CLKO ↑ – CSN
CLKO ↑ – RASN
CLKO ↑ – CASN
CLKO ↑ – WEN
CLKO ↑ – A0 to A10
CLKO ↑ – DQ0 to DQ15
1
tBICY
tRASNL
CL = 15pF
1
tBICY
tCASNH
CL = 15pF
1
tBICY
tCASNL
CL = 15pF
1
tBICY
tWENH
CL = 15pF
1
tBICY
1
tWENL
CL = 15pF
Setup time
tCSNS
CL = 15pF
1/2
tBICY
tBICY
Hold time
tCSNH
CL = 15pF
1/2
tBICY
Setup time
tRASNS
CL = 15pF
1/2
tBICY
Hold time
tRASNHO
CL = 15pF
1/2
tBICY
Setup time
tCASNS
CL = 15pF
1/2
tBICY
Hold time
tCASNHO
CL = 15pF
1/2
tBICY
Setup time
tWENS
CL = 15pF
1/2
tBICY
Hold time
tWENHO
CL = 15pF
1/2
tBICY
Setup time
tADS
CL = 15pF
1/2
tBICY
Hold time
tADH
CL = 15pF
1/2
tBICY
Setup time
tDQS
CL = 15pF
1/2
tBICY
Hold time
tDQH
CL = 15pF
1/2
tBICY
Refresh command interval
tREF
CL = 15pF
3
times/fs
CLKO propagation delay
tDLY
CL = 15pF
0
15
ns
SEIKO NPC CORPORATION —7
SM5921A
VOH
1.5V
CLKO
tCLKOH
tCLKOL
tCLKCY
VOL
VOH
1.5V
CSN
tDLY
VOL
tDLY
VOH
1.5V
RASN
tRASNL
tRASNH
VOL
tDLY
VOH
1.5V
CASN
tCASNH
tCASNL
VOL
tDLY
VOH
1.5V
WEN
tWENH
tWENL
VOL
tDLY
VOH
1.5V
A0 to A10
tDLY
VOL
VOH
1.5V
DQ0 to DQ15
tDLY
VOL
SEIKO NPC CORPORATION —8
SM5921A
MCU interface input/outputs (SCLK, SI, XCS, SIO pins)
Rating
Parameter
Symbol
Conditions
Unit
min
typ
max
XCS HIGH-level pulsewidth
tXCSWH
30 + tBICY
ns
XCS LOW-level pulsewidth
tXCSWL
30 + 17tBICY
ns
SCLK setup time
tXCSS
30 + tBICY/2
ns
SCLK hold time
tXCSH
30 + tBICY/2
ns
SCLK pulse cycle time
tSCLKCY
60 + tBICY
ns
SCLK HIGH-level pulsewidth
tSCLKH
30 + tBICY
ns
SCLK LOW-level pulsewidth
tSCLKL
30 + tBICY
ns
tSIS
30 + tBICY/2
ns
SI setup time
SI hold time
tSIH
SCLK to output propagation delay
tDSIO
30 + tBICY/2
CL = 15pF
0
tXCSWL
ns
20
ns
tXCSWH
VIH
0.5VDD
XCS
VIL
tXCSS
tXCSH
VIH
0.5VDD
SCLK
tSCLKH
tSCLKL
tSCLKCY
VIL
VIH
0.5VDD
SI
tSIS
tSIH
VIL
VIH
0.5VDD
SIO
tDSIO
VIL
SEIKO NPC CORPORATION —9
SM5921A
FUNCTIONAL DESCRIPTION
Delay Settings
The SM5921A sets the delay value set using an MCU interface and adds that delay to the input data. The total
delay value for each channel data is given by the following equation.
( nSample-system + ( nSample-intrinsic + nSample-individual ) × nMp )
t Delay ( sec ) = ------------------------------------------------------------------------------------------------------------------------------------------------------------------------fs
nSample-system:
Number of system delay samples (fixed 2 samples)
nSample-intrinsic:
Number of intrinsic delay samples (16-sample units)
nSample-individual:
Number of individual delay samples (1-sample units)
nMp:
Address shift coefficient
fs:
Sampling frequency
Note that even when the intrinsic delay and individual delay are both set to 0 samples, a 2-sample delay is
applied.
Address shift coefficient
The address shift coefficient is determined by the settings of the MP0N and MP1N flags. These enable the time
delay to be multiplied by ×1, ×2, or ×4 without changing the delay value setting. For example, if the sampling
frequency fs is switched from 48kHz to 192kHz and the address shift is set to ×4, then the same delay time is
added.
■
■
MP0N
MP1N
nMp
LOW
LOW
1
LOW
HIGH
2
HIGH
LOW
4
HIGH
HIGH
1
Data setting values cannot exceed the upper limit.
Calculation examples
• If fs = 48kHz, REG 0/H = 200/H, REG 2/H = 800/H, nMp = 1, then the delay value is:
tDelay = (nSample-system + (nSample-intrinsic + nSample-individual) × nMp) ÷ fs [sec]
= (2 + (8192 + 2048) × 1) ÷ 48000 = 213.3ms
• If fs = 192kHz, REG 0/H = 200/H, REG 2/H = 800/H, nMp = 1, then the delay value is:
tDelay = (nSample-system + (nSample-intrinsic + nSample-individual) × nMp) ÷ fs [sec]
= (2 + (8192 + 2048) × 1) ÷ 192000 = 53.3ms
• If fs = 192kHz, REG 0/H = 200/H, REG 2/H = 800/H, nMp = 2, then the delay value is:
tDelay = (nSample-system + (nSample-intrinsic + nSample-individual) × nMp) ÷ fs [sec]
= (2 + (8192 + 2048) × 2) ÷ 192000 = 106.6ms
• If fs = 192kHz, REG 0/H = 200/H, REG 2/H = 800/H, nMp = 4, then the delay value is:
tDelay = (nSample-system + (nSample-intrinsic + nSample-individual) × nMp) ÷ fs [sec]
= (2 + (8192 + 2048) × 4) ÷ 192000 = 213.3ms
From the examples, it can be seen that switching the sampling frequency from 48kHz to 192kHz and changing
nMp from 1 to 4 results in an identical time delay. Note, however, that the memory size physical limit cannot
be exceeded. So, for example, the physical limit is reached with a sum (nSample-intrinsic + nSample-individual) of 16384 samples when nMp = 4, or the equivalent of 65535 samples at nMp = 1.
SEIKO NPC CORPORATION —10
SM5921A
Intrinsic delay
The intrinsic delay is the common delay applied to each channel group, and is used to add the same delay value
to the channel group data. The default value is 0 samples. The intrinsic delay is set by the values of REG 0/H
(DIA/DOA and DIB/DOB groups) and REG 1/H (DIC/DOC and DID/DOD groups), with the values measured
in 16-sample units (333.2µs @ fs = 48kHz).
When the TRACKT flag in REG A/H is set to HIGH, the same delay value is added to all the channel groups
(DIA/DOA, DIB/DOB, DIC/DOC, DID/DOD). See the “MCU Interface” section.
Individual delay
The individual delay is the delay applied to each channel individually, and is used to add a delay offset for each
channel data. The default value is 0 samples. The individual delay is set by the values of REG 2/H, REG 3/H,
REG 4/H, REG 5/H, REG 6/H, REG 7/H, REG 8/H, and REG 9/H, with the values measured in 1-sample units
(20.8µs @ fs = 48kHz).
When the TRACKD flag in REG A/H is set to HIGH, the delay value set in REG 2/H (DIA/DOA left-channel)
is also applied to the DIA/DOA right-channel, DIB/DOB left-channel, and DIB/DOB right-channel data. Similarly, the delay value set in REG 6/H (DIC/DOC left-channel) is also applied to the DIC/DOC right-channel,
DID/DOD left-channel, and DID/DOD right-channel data.
The minimum parameter settings required to apply the same delay to all channels is to set delay values in REG
0/H, REG 2/H, REG 6/H, and to set the TRACKT and TRACKD flags to HIGH. The relationship between the
intrinsic delay, individual delay, and the registers is shown in the following table.
Channel
Intrinsic delay
DIA/DOA left-channel
Individual delay
REG 2/H
DIA/DOA right-channel
REG 3/H
REG 0/H
DIB/DOB left-channel
REG 4/H
DIB/DOB right-channel
REG 5/H
DIC/DOC left-channel
REG 6/H
DIC/DOC right-channel
REG 7/H
REG 1/H
DID/DOD left-channel
REG 8/H
DID/DOD right-channel
REG 9/H
Delay time examples
The total delay value is defined by the equation described earlier. The following table shows some examples.
Sampling frequency (fs)
nSample-intrinsic + nSample-individual setting
Unit
32kHz
44.1kHz
48kHz
96kHz
192kHz
0*1
62.5
45.4
41.7
20.8
10.4
µs
1000
31.3
22.7
20.8
10.4
5.2
ms
10000
312.5
226.8
208.3
104.2
52.1
ms
20000
625
453.5
416.7
208.3
104.2
ms
36863
1152
835.9
768
384
192
ms
65535
2048
1486.1
1365.3
682.7
341.3
ms
*1. Even when the set value is 0 samples, a fixed 2-sample system delay is applied.
SEIKO NPC CORPORATION —11
SM5921A
Delay set value upper limit
The upper limit for the delay set value input {(nSample-intrinsic + nSample-individual) × nMp} for each channel is 65535 samples. If a delay value input exceeding 65536 is incorrectly set, an internal limiter treats the
channel delay set value as 65535 samples. The following table shows some delay value setting examples.
Delay set value input
nMp
REG 0/H
REG 2/H
nSample-intrinsic + nSample-individual × nMp
[samples]
Limiter delay set value
[samples]
1
FFF/H
00F/H
(65520 + 15) × 1 = 65535
65535
1
FFF/H
010/H
(65520 + 16) × 1 = 65536
65535
2
7FF/H
00F/H
(32752 + 15) × 2 = 65534
65534
2
7FF/H
010/H
(32752 + 16) × 2 = 65536
65535
4
3FF/H
00F/H
(16368 + 15) × 4 = 65532
65532
4
3FF/H
010/H
(16368 + 16) × 4 = 65536
65535
System Reset (RSTN, WPOLN pins, INIT flag)
The SM5921A must be reset when power is applied. The system is reset by applying a LOW-level pulse on the
RSTN pin. When the system is reset, all registers are cleared and the sequencer is also reset. The system reset
is released by a LOW-to-HIGH transition on RSTN when the supply voltage has stabilized and the WCKI and
BCKI clocks have stabilized. If the WCKI or BCKI clocks stop during operation, the system should be reset
again after the clocks have stabilized. After the system reset is released, the SM5921A enters the initialization
sequence and starts SDRAM initialization. The initialization requires an interval of 1/fs × 64. During the initialization sequence, input data on DIA, DIB, DIC, or DID is ignored. The system can also be reset without
applying a LOW-level pulse on RSTN under the following conditions.
When switching WPOLN pin or INIT flag
The SDRAM initialization sequence also begins when the WPOLN pin is switched or the INIT flag is set. During SDRAM initialization, each output is muted by the direct mute function.
Word Clock Polarity (WPOLN pin)
The SM5921A handles 64fs slot data as 1 word, enabling the word boundary polarity to be specified. The
WPOLN pin has pull-up resistor built-in. When WPOLN is open circuit (or HIGH), data is handled as leftchannel data when WCKI is HIGH. The data-through (bypass), output enable, and direct mute functions operate on the word boundary set by the WPOLN pin.
Refer to the “TIMING DIAGRAMS” section for more information.
WPOLN
Function
LOW
Data is handled as left-channel data during the LOW-level pulse on WCKI. The word boundary is a falling edge on
WCKI.
HIGH
Data is handled as left-channel data during the HIGH-level pulse on WCKI. The word boundary is a rising edge on
WCKI.
Data Through (THROU flag)
The SM5921A applies a fixed 2-sample system delay when exchanging with the SDRAM, even if the delay
setting is 0 (see the “Delay Settings” section). The THROU flag in REG A/H can be set to 1 when a completely
zero delay is required. When the THROU flag is set to 1, the DIA, DIB, DIC, DID input data bypasses the
delay processing and is passed directly to the DOA, DOB, DOC, DOD outputs, respectively. The default setting of the THROU flag is 0, so if not set specifically, delayed data is output on the DOA, DOB, DOC, DOD
pins. The THROU flag is detected on the WCKI boundary edge, which means that there is a maximum 1-word
delay before the change is reflected at the output.
SEIKO NPC CORPORATION —12
SM5921A
Output Enable (OEN pin)
The SM5921A has an output enable control for the DOA, DOB, DOC, DOD outputs. When OEN is HIGH, the
output pins are disabled. The OEN pin has a pull-down resistor built-in. When the OEN pin is open-circuit (or
LOW), the output pins are enabled and delay data is output. The OEN pin is detected on the WCKI boundary
edge, which means that there is a maximum 1-word delay before the change is reflected at the output.
Direct Mute (DMUTEN pin)
Direct mute ON/OFF
DMUTEN
Function
LOW
0 data output from the next output word after writing the setting.
HIGH
Normal delay data output from the next output word after writing the setting.
Other mute operations
The outputs are also muted (direct mute) when a reset pulse is applied.
RSTN
Function
LOW
0 data output from the next output word after writing the setting.
HIGH
Normal delay data output after 64 output words after writing the setting.
The outputs are also muted (direct mute) when the INIT flag is set.
INIT
Function
LOW
Normal output operation.
HIGH
Normal delay data output after a 64-word mute interval after writing the setting.
The outputs are also muted (direct mute) when the PDW flag is set.
PDW
Function
LOW (HIGH → LOW)
0 data output from the next output word after writing to the register. The outputs are muted during the interval until the
initialization data write point, and then mute is released for delay data output.
HIGH
0 data output from the next output word after writing data to the register.
The outputs are also muted (direct mute) setting the delay data values.
Delay setting
Function
Intrinsic delay
0 data output from the next output word after writing to registers REG 0/H and 1/H. The outputs are muted during the
interval until the initialization data write point, and then mute is released for delay data output.
Individual delay
0 data output from the next output word after writing to registers REG 3/H to 9/H. The outputs are muted during the
interval until the initialization data write point, and then mute is released for delay data output.
SEIKO NPC CORPORATION —13
SM5921A
The outputs are also muted (direct mute) when changing the setting of the MP0n and MP1N flags.
MP0N, MP1N
Function
(L,L) → (H,L)
(L,L) → (L,H)
(H,H) → (H,L)
(H,H) → (L,H)
0 data output from the next output word after changing the setting of the flags. The outputs are muted during the interval
until the initialization data write point, and then mute is released for delay data output.
(H,L) → (L,L)
(H,L) → (L,H)
(H,L) → (H,H)
0 data output from the next output word after changing the setting of the flags. The outputs are muted during the interval
until the initialization data write point, and then mute is released for delay data output.
(L,H) → (L,L)
(L,H) → (H,L)
(L,H) → (H,H)
0 data output from the next output word after changing the setting of the flags. The outputs are muted during the interval
until the initialization data write point, and then mute is released for delay data output.
(L,L) → (H,H)
(H,H) → (L,L)
Normal output operation.
The outputs are also muted (direct mute) when setting the TRACKT and TRACKD flags.
■
■
TRACKT
Function
LOW (HIGH → LOW)
0 data output from the next output word after writing to the register. The outputs are muted during the interval until the
initialization data write point, and then mute is released for delay data output.
HIGH (LOW → HIGH)
0 data output from the next output word after writing to the register. The outputs are muted during the interval until the
initialization data write point, and then mute is released for delay data output.
TRACKD
Function
LOW (HIGH → LOW)
0 data output from the next output word after writing to the register. The outputs are muted during the interval until the
initialization data write point, and then mute is released for delay data output.
HIGH (LOW → HIGH)
0 data output from the next output word after writing to the register. The outputs are muted during the interval until the
initialization data write point, and then mute is released for delay data output.
If the delay value is set during the 64-word direct mute interval after reset is released, the output muting is
extended until the initialization data write point after the direct mute interval.
If the delay value is updated during mute operation, and the extended mute interval determined by a previous
delay setting is longer than that due to the updated value, muting continues until the previously set delay
value setting. If that mute interval is smaller than that due to the updated value, muting continues until the
point determined by the updated value. In other words, muting continues until a point determined by the
larger of the two values.
SEIKO NPC CORPORATION —14
SM5921A
Intrinsic delay timing example (TRACKT = LOW)
After writing, the first data writing point
WCKI
DIA, DIB
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
DIC, DID
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
DOUTA, DOUTB
Lch
Rch
DMUTE
Lch
Rch
Lch
Rch
DOUTC, DOUTD
Lch
Rch
DMUTE
Lch
Rch
Lch
Rch
0/H writing
Individual delay timing example (TRACKD = LOW)
■
Mute interval determined by REG 2/H is larger than that determined by REG 4/H
After 2/H writing, the first data writing point
WCKI
After 4/H writing, the first data writing point
DIA
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
DIB
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
DIC
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
DID
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
DOUTA
Lch
Rch
DMUTE
Lch
Rch
DOUTB
Lch
Rch
DMUTE
Lch
Rch
DOUTC
Lch
Rch
DMUTE
Lch
Rch
DOUTD
Lch
Rch
DMUTE
Lch
Rch
2/H writing
4/H writing
SEIKO NPC CORPORATION —15
SM5921A
Individual delay timing example (TRACKD = LOW)
■
Mute interval determined by REG 2/H is smaller than that determined by REG 4/H
Movement
After 2/H writing, the first data writing point
WCKI
After 4/H writing, the first data writing point
DIA
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
DIB
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
DIC
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
DID
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
DOUTA
Lch
Rch
DMUTE
Lch
Rch
DOUTB
Lch
Rch
DMUTE
Lch
Rch
DOUTC
Lch
Rch
DMUTE
Lch
Rch
DOUTD
Lch
Rch
DMUTE
Lch
Rch
2/H writing
4/H writing
SEIKO NPC CORPORATION —16
SM5921A
MCU Interface
The MCU interface is comprised by a 4-wire serial interface.
SCLK
XCS
SI
RD/ A3
WR
SI
READ
■
■
RD/ A3
WR
A2
A1
A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
"1"
SIO
■
A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
SIO
■
A1
"0"
WRITE
■
A2
Hi-Z
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
The SCLK clock may trace the dotted line path or not, as long as there is 17 SCLK pulses during the XCS
LOW-level pulse interval.
When the RD/WR bit is set to 1 the device enters register read mode, and the register contents addressed by
bits A3 to A0 are output as serial data on the SIO pin. In read mode, the SI input data bits D11 to D0 are
ignored.
When the RD/WR bit is set to 0 the device enters register write mode, and the SI input data bits D11 to D0
are written to the register addressed by bits A3 to A0.
Systems that hold the serial input high-impedance during the D11 to D0 data interval in read mode can bind
the SI and SIO pins and function as a 3-wire serial interface.
In read mode, the output for non-assigned addresses is 0 data.
SEIKO NPC CORPORATION —17
SM5921A
REG 0/H
A3
0
A2
0
A1
0
A0
0
Intrinsic delay (DIA, DIB)
D11
×
D10
×
D9
×
D8
×
D7
×
D6
×
D5
×
D4
×
D3
×
D2
×
D1
×
D0
×
Minimum unit setting: 16 samples
0000 0000 0000 → 0 samples (default)
0000 0000 0001 → 16 samples
0000 0000 1000 → 128 samples
0000 0001 0000 → 256 samples
0000 1000 0000 → 2048 samples
0001 0000 0000 → 4096 samples
1000 0000 0000 → 32768 samples
1111 1111 1111 → 65520 samples
333.2µs/step @ fs = 48kHz
1365ms/step @ fs = 48kHz
83.3µs/step @ fs = 192kHz
341.2ms/step @ fs = 192kHz
REG 1/H
A3
0
A2
0
A1
0
Intrinsic delay (DIC, DID)
A0
1
D11
×
D10
×
D9
×
D8
×
D7
×
D6
×
D5
×
D4
×
D3
×
D2
×
D1
×
D0
×
Minimum unit setting: 16 samples
0000 0000 0000 → 0 samples (default)
0000 0000 0001 → 16 samples
0000 0000 1000 → 128 samples
0000 0001 0000 → 256 samples
0000 1000 0000 → 2048 samples
0001 0000 0000 → 4096 samples
1000 0000 0000 → 32768 samples
1111 1111 1111 → 65520 samples
333.2µs/step @ fs = 48kHz
1365ms/step @ fs = 48kHz
83.3µs/step @ fs = 192kHz
341.2ms/step @ fs = 192kHz
SEIKO NPC CORPORATION —18
SM5921A
REG 2/H
A3
0
A2
0
A1
1
A0
0
Individual delay (DIA left-channel)
D11
×
D10
×
D9
×
D8
×
D7
×
D6
×
D5
×
D4
×
D3
×
D2
×
D1
×
D0
×
Minimum unit setting: 1 sample
0000 0000 0000 → 0 samples (default)
0000 0000 0001 → 1 samples
0000 0000 1000 → 8 samples
0000 0001 0000 → 16 samples
0000 1000 0000 → 128 samples
0001 0000 0000 → 256 samples
1000 0000 0000 → 2048 samples
1111 1111 1111 → 4095 samples
20.8µs/step @ fs = 48kHz
85.3ms/step @ fs = 48kHz
5.2µs/step @ fs = 192kHz
21.3ms/step @ fs = 192kHz
REG 3/H
A3
0
A2
0
A1
1
Individual delay (DIA right-channel)
A0
1
D11
×
D10
×
D9
×
D8
×
D7
×
D6
×
D5
×
D4
×
D3
×
D2
×
D1
×
D0
×
Minimum unit setting: 1 sample
0000 0000 0000 → 0 samples (default)
0000 0000 0001 → 1 samples
0000 0000 1000 → 8 samples
0000 0001 0000 → 16 samples
0000 1000 0000 → 128 samples
0001 0000 0000 → 256 samples
1000 0000 0000 → 2048 samples
1111 1111 1111 → 4095 samples
20.8µs/step @ fs = 48kHz
85.3ms/step @ fs = 48kHz
5.2µs/step @ fs = 192kHz
21.3ms/step @ fs = 192kHz
SEIKO NPC CORPORATION —19
SM5921A
REG 4/H
A3
0
A2
1
A1
0
A0
0
Individual delay (DIB left-channel)
D11
×
D10
×
D9
×
D8
×
D7
×
D6
×
D5
×
D4
×
D3
×
D2
×
D1
×
D0
×
Minimum unit setting: 1 sample
0000 0000 0000 → 0 samples (default)
0000 0000 0001 → 1 samples
0000 0000 1000 → 8 samples
0000 0001 0000 → 16 samples
0000 1000 0000 → 128 samples
0001 0000 0000 → 256 samples
1000 0000 0000 → 2048 samples
1111 1111 1111 → 4095 samples
20.8µs/step @ fs = 48kHz
85.3ms/step @ fs = 48kHz
5.2µs/step @ fs = 192kHz
21.3ms/step @ fs = 192kHz
REG 5/H
A3
0
A2
1
A1
0
Individual delay (DIB right-channel)
A0
1
D11
×
D10
×
D9
×
D8
×
D7
×
D6
×
D5
×
D4
×
D3
×
D2
×
D1
×
D0
×
Minimum unit setting: 1 sample
0000 0000 0000 → 0 samples (default)
0000 0000 0001 → 1 samples
0000 0000 1000 → 8 samples
0000 0001 0000 → 16 samples
0000 1000 0000 → 128 samples
0001 0000 0000 → 256 samples
1000 0000 0000 → 2048 samples
1111 1111 1111 → 4095 samples
20.8µs/step @ fs = 48kHz
85.3ms/step @ fs = 48kHz
5.2µs/step @ fs = 192kHz
21.3ms/step @ fs = 192kHz
SEIKO NPC CORPORATION —20
SM5921A
REG 6/H
A3
0
A2
1
A1
1
A0
0
Individual delay (DIC left-channel)
D11
×
D10
×
D9
×
D8
×
D7
×
D6
×
D5
×
D4
×
D3
×
D2
×
D1
×
D0
×
Minimum unit setting: 1 sample
0000 0000 0000 → 0 samples (default)
0000 0000 0001 → 1 samples
0000 0000 1000 → 8 samples
0000 0001 0000 → 16 samples
0000 1000 0000 → 128 samples
0001 0000 0000 → 256 samples
1000 0000 0000 → 2048 samples
1111 1111 1111 → 4095 samples
20.8µs/step @ fs = 48kHz
85.3ms/step @ fs = 48kHz
5.2µs/step @ fs = 192kHz
21.3ms/step @ fs = 192kHz
REG 7/H
A3
0
A2
1
A1
1
Individual delay (DIC right-channel)
A0
1
D11
×
D10
×
D9
×
D8
×
D7
×
D6
×
D5
×
D4
×
D3
×
D2
×
D1
×
D0
×
Minimum unit setting: 1 sample
0000 0000 0000 → 0 samples (default)
0000 0000 0001 → 1 samples
0000 0000 1000 → 8 samples
0000 0001 0000 → 16 samples
0000 1000 0000 → 128 samples
0001 0000 0000 → 256 samples
1000 0000 0000 → 2048 samples
1111 1111 1111 → 4095 samples
20.8µs/step @ fs = 48kHz
85.3ms/step @ fs = 48kHz
5.2µs/step @ fs = 192kHz
21.3ms/step @ fs = 192kHz
SEIKO NPC CORPORATION —21
SM5921A
REG 8/H
A3
1
A2
0
A1
0
A0
0
Individual delay (DID left-channel)
D11
×
D10
×
D9
×
D8
×
D7
×
D6
×
D5
×
D4
×
D3
×
D2
×
D1
×
D0
×
Minimum unit setting: 1 sample
0000 0000 0000 → 0 samples (default)
0000 0000 0001 → 1 samples
0000 0000 1000 → 8 samples
0000 0001 0000 → 16 samples
0000 1000 0000 → 128 samples
0001 0000 0000 → 256 samples
1000 0000 0000 → 2048 samples
1111 1111 1111 → 4095 samples
20.8µs/step @ fs = 48kHz
85.3ms/step @ fs = 48kHz
5.2µs/step @ fs = 192kHz
21.3ms/step @ fs = 192kHz
REG 9/H
A3
1
A2
0
A1
0
Individual delay (DID right-channel)
A0
1
D11
×
D10
×
D9
×
D8
×
D7
×
D6
×
D5
×
D4
×
D3
×
D2
×
D1
×
D0
×
Minimum unit setting: 1 sample
0000 0000 0000 → 0 samples (default)
0000 0000 0001 → 1 samples
0000 0000 1000 → 8 samples
0000 0001 0000 → 16 samples
0000 1000 0000 → 128 samples
0001 0000 0000 → 256 samples
1000 0000 0000 → 2048 samples
1111 1111 1111 → 4095 samples
20.8µs/step @ fs = 48kHz
85.3ms/step @ fs = 48kHz
5.2µs/step @ fs = 192kHz
21.3ms/step @ fs = 192kHz
SEIKO NPC CORPORATION —22
SM5921A
REG A/H
A3
1
A2
0
A1
1
A0
0
D11
L
Do not use
D10
L
Do not use
D9
L
Do not use
D8
L
Do not use
D7
L
Do not use
D6
L
MP0N address shift setting 0
D5
L
MP1N address shift setting 1
(MP0N, MP1N) = (L,L) → × 1 multiplication
(MP0N, MP1N) = (L,H) → × 2 multiplication
(MP0N, MP1N) = (H,L) → × 4 multiplication
(MP0N, MP1N) = (H,H) → × 1 multiplication
D4
L
THROU flag
THROU = H: Input data is passed through to the output bypassing delay processing.
THROU = L: Normal operating mode (default)
D3
L
TRACKD flag
TRACKD = H: REG 3/H to REG5/H follow the REG 2/H contents.
REG 7/H to REG9/H follow the REG 6/H contents.
TRACKD = L: Normal operating mode (default)
D2
L
TRACKT flag
TRACKT = H: REG 1/H follows the REG 0/H contents.
TRACKT = L: Normal operating mode (default)
D1
L
PDW flag
PDW = H:
PDW = L:
D0
L
Miscellaneous settings
INIT flag
INIT = H:
INIT = L:
Issues the power-down command to the SDRAM.
Normal operating mode (default)
Starts the SDRAM initialization process.
INIT is set to L when the initialization process ends.
Normal operating mode (default)
SEIKO NPC CORPORATION —23
SM5921A
SDRAM
SDRAM compatibility
The SM5921A transfers data when the SDRAM mode register (MRS) has the following settings. SDRAM
devices that support these settings are compatible.
CL (CAS latency) : 2
BL (Burst length) : 2, 8
WT (Wrap type) : Sequential
Connecting to SDRAM
The SM5921A supports 16M/64M/128M (×16 devices) SDRAM. The SDRAM interface is connected as
described in the following table.
SM5921A pins
SDRAM pins
16M SDRAM connection
64M SDRAM connection
128M SDRAM connection
CS
CSN
CSN
CSN
CLK
CLKO
CLKO
CLKO
CKE
CKE
CKE
CKE
BA1
–
LOW-level
LOW-level
BA0 (BA)
BA
BA
BA
A11
–
LOW-level
LOW-level
A10 to A0
A10 to A0
A10 to A0
A10 to A0
RAS
RASN
RASN
RASN
CAS
CASN
CASN
CASN
WE
WEN
WEN
WEN
HDQM
DQM
DQM
DQM
LDQM
DQM
DQM
DQM
DQ15 to DQ0
DQ15 to DQ0
DQ15 to DQ0
DQ15 to DQ0
SEIKO NPC CORPORATION —24
SM5921A
TIMING DIAGRAMS
Input Timing (WCKI, BCKI, DIA, DIB, DIC, DID pins)
WCKI (fs)
Lch
Rch
BCKI (64fs)
DI*
64 1 2
15 16
31 32 33 34
47 48
63 64 1
Figure 1. 64fs/slot, WPOLN = H
DI*: DIA, DIB, DIC, DID pins
WCKI (fs)
Lch
Rch
BCKI (64fs)
DI*
64 1 2
15 16
31 32 33 34
47 48
63 64 1
Figure 2. 64fs/slot, WPOLN = L
DI*: DIA, DIB, DIC, DID pins
Output Timing (WCKI, BCKI, DOUTA, DOUTB, DOUTC, DOUTD pins)
WCKI (fs)
Lch
Rch
BCKI (64fs)
DOUT*
64 1 2
15 16
31 32 33 34
47 48
63 64 1
Figure 3. 64fs/slot, WPOLN = H
DOUT*: DOUTA, DOUTB, DOUTC, DOUTD pins
WCKI (fs)
Lch
Rch
BCKI (64fs)
DOUT*
64 1 2
15 16
31 32 33 34
47 48
63 64 1
Figure 4. 64fs/slot, WPOLN = L
DOUT*: DOUTA, DOUTB, DOUTC, DOUTD pins
SEIKO NPC CORPORATION —25
SM5921A
TYPICAL APPLICATION CIRCUITS
16M SDRAM (MSM56V16160) Connection Example
XCS
SCLK
MCU
CSN
CLKO
CLE
SI
SIO
BA
A10 to A0
RASN
CASN
WEN
SM5921A
WCKI
BCKI
DQM
Digital signal
processor
DIA
DIB
DIC
DID
16M SDRAM
MSM56V16160
OKI
HDQM
LDQM
DQ15 to DQ0
WPOLN
OEN
DMUTEN
64M SDRAM (MD56V62160) Connection Example
XCS
MCU
SCLK
SI
CSN
CLKO
CLE
SIO
BA
BA0
A10 to A0
SM5921A
RASN
CASN
WEN
WCKI
BCKI
DQM
Digital signal
processor
DIA
DIB
DIC
DID
BA1
A11
64M SDRAM
MD56V62160
OKI
HDQM
LDQM
DQ15 to DQ0
WPOLN
OEN
DMUTEN
SEIKO NPC CORPORATION —26
SM5921A
Please pay your attention to the following points at time of using the products shown in this document.
The products shown in this document (hereinafter “Products”) are not intended to be used for the apparatus that exerts harmful influence on
human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such
use from SEIKO NPC CORPORATION (hereinafter “NPC”). Customers shall be solely responsible for, and indemnify and hold NPC free and
harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right
to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that
the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties.
Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document.
Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products,
and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or
modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in
compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested
appropriately take steps to obtain required permissions or approvals from appropriate government agencies.
SEIKO NPC CORPORATION
15-6, Nihombashi-kabutocho, Chuo-ku,
Tokyo 103-0026, Japan
Telephone: +81-3-6667-6601
Facsimile: +81-3-6667-6611
http://www.npc.co.jp/
Email: [email protected]
NC0514CE
2007.07
SEIKO NPC CORPORATION —27