Ordering number : EN*5543 CMOS LSI LC89051V Digital Audio Interface Receiver Preliminary Overview Package Dimensions The LC89051V is for use in IEC958 format data transmission between digital audio equipment. This LSI is used on the receiving side, and handles synchronization with the input signal and demodulation of that signal to a normal format signal. unit: mm 3175A-SSOP24 [LC89051V] Features • On-chip PLL circuit synchronizes with the transmitted IEC958 format signal. • Low-voltage operation (3.3 V) • Provides 128fs, bit, and L/R clock outputs. • System clock can be selected to be either 384fs or 512fs. • Microcontroller interface code settings for different output types — Input pin, emphasis output, input bi-phase data output, and validity flag output settings — Audio data output format setting — Channel status output (32-bit output for consumer products) — Subcode Q output with CRC flags (80 bits) — Start ID and shortening (skip) ID detection for DAT with subcodes • The built-in VCO can receive at speeds up to twice fs only when operating from a 5-V power supply. • Miniature package: SSOP-24 SANYO: SSOP24 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN N3097HA (OT) No. 5543-1/15 LC89051V Pin Assignment Pin Functions Pin No. Symbol I/O 1 DIN1 I Data input with built-in amplifier (for coaxial or optical module input) Description Data input (for optical module input) 2 DIN2 I 3 E/DOUT O Emphasis, input bi-phase, and validity flag output 4 VDD – Power supply 5 R I VCO gain control input 6 VIN I VCO free-running setting input 7 VCO O PLL low-pass filter setting 8 GND – Ground System clock selection input (384fs or 512fs) 9 CKSEL I 10 XMODE I Reset input 11 AVOCK I PLL error lock avoidance clock input 12 TEST1 I Test input (Must be connected to ground in normal operation) 13 TEST2 I Test input (Must be connected to ground in normal operation) 14 SCLK/CL I Microcontroller interface clock input 15 XLAT/CE I Microcontroller interface latch/chip enable input 16 SWDT/DI I Microcontroller interface write data input 17 SRDT/DO O Microcontroller interface read data output 18 DQSY/LD O Microcontroller interface subcode Q and ID synchronization output 19 CKOUT O VCO clock output (free running, 384fs, or 512fs) 20 FS128 O 128fs clock output 21 BCK O Bit clock output 22 LRCK O L/R clock output (left channel = high, right channel = low) 23 DATAOUT O Audio data output 24 ERROR O PLL lock error mute output No. 5543-2/15 LC89051V Block Diagram Microcontroller interface No. 5543-3/15 LC89051V Specifications Absolute Maximum Ratings Parameter Symbol Supply voltage Conditions Ratings VDD I/O voltages VI, VO Unit –0.3 to +7.0 V –0.3 to VDD + 0.3 V I/O current II, IO ±20 mA Operating temperature Topr –30 to +75 °C Storage temperature Tstg –55 to +125 °C Allowable Operating Ranges Parameter Supply voltage Operating temperature Symbol Conditions VDD min typ max Unit 3.0 5.0 5.5 V +75 C° (3.3) TOPR –30 Electrical Characteristics DC Characteristics (1) at Ta = –30 to +75°C, VDD = 4.5 to 5.5 V, VSS = 0 V max Unit Input high-level voltage Parameter Symbol VIH1 *1 Conditions 0.7 VDD VDD + 0.3 V Input low-level voltage VIL1 *1 –0.3 0.3 VDD V Input high-level voltage VIH2 *2 0.8 VDD VDD + 0.3 V Input low-level voltage VIL2 *2 –0.3 0.2 VDD V Input high-level voltage VIH3 *3 2.5 VDD + 0.3 V Input low-level voltage VIL3 *3 –0.3 +0.6 V Output high-level voltage VOH IOH = –4 mA Output low-level voltage VOL IOL= 4 mA 0.4 V 20 mA Current drain IDD *4 Input amplitude Vpp *5 Note: 1. 2. 3. 4. 5. min typ VDD – 2.1 V 0.4 VDD + 0.3 V Applies to the CKSEL, AVOCK, TEST1, and TEST2 pins. CMOS levels. Applies to the XMODE, SCLK/CL, XLAT/CE, SWDT/DI pins. CMOS Schmitt inputs. Applies to the DIN2 pin. TTL Schmitt levels. VDD = 5.0 V, Ta = 25°C, input data fs = 96 kHz Measured before the DIN1 pin input capacitor. DC Characteristics (2) at Ta = –30 to +75°C, VDD = 3.0 to 3.6 V, VSS = 0 V max Unit Input high-level voltage Parameter Symbol VIH1 *6 Conditions 0.7 VDD VDD + 0.3 V Input low-level voltage VIL1 *6 –0.3 0.2 VDD V Input high-level voltage VIH2 *7 0.75 VDD VDD + 0.3 V Input low-level voltage VIL2 *7 –0.3 0.15 VDD V Input high-level voltage VIH3 *8 2.4 VDD + 0.3 V Input low-level voltage VIL3 *8 –0.3 +0.3 V Output high-level voltage VOH IOH = –2 mA Output low-level voltage VOL IOL= 2 mA 0.4 V 10 mA Current drain IDD *9 Input amplitude Vpp *10 Note: 6. 7. 8. 9. 10. min typ VDD – 0.8 0.4 V VDD + 0.3 V Applies to the CKSEL, AVOCK, TEST1, and TEST2 pins. CMOS levels. Applies to the XMODE, SCLK/CL, XLAT/CE, SWDT/DI pins. CMOS Schmitt inputs. Applies to the DIN2 pin. TTL Schmitt levels. VDD = 3.3 V, Ta = 25°C, input data fs = 48 kHz Measured before the DIN1 pin input capacitor. No. 5543-4/15 LC89051V AC Characteristics (Normal Mode) at Ta = –30 to +75°C, VDD = 3.0 to 5.5 V Parameter AVOCK input pulse width Symbol VCO free-running frequency fVCO BCK output pulse width tWBO Output data setup time Output data hold time Output delay Conditions tWBI min typ max Unit 50 MHz 75 MHz 10 µs *11 *12 fs = 48 kHz 160 ns tDSO 80 ns tDHO 80 tBD –10 ns 0 +10 ns typ max Unit 80 MHz Note: 11.Ta = 25°C, VDD = 3.3 V, with the circuit constants for standard speed operation in the sample application circuit. 12.Ta = 25°C, VDD = 5.0 V, with the circuit constants for standard speed operation in the sample application circuit. AC Characteristics (Double Speed Mode) at Ta = –30 to +75°C, VDD = 4.5 to 5.5 V Parameter Symbol Conditions AVOCK input pulse width tWBI VCO free-running frequency fVCO *13 fs = 96 kHz min 10 µs BCK output pulse width tWBO 80 ns Output data setup time tDSO 40 ns Output data hold time tDHO 40 tBD –10 Output delay ns 0 +10 ns Note: 13.Ta = 25°C, VDD = 5.0 V, with the circuit constants for 2× speed operation in the sample application circuit. No. 5543-5/15 LC89051V Microcontroller Interface Block AC Characteristics at Ta = –30 to +75°C, VDD = 3.0 to 5.5 V (when CKSEL is low) Parameter Symbol Conditions min typ max Unit CL low pulse width tWL 100 ns CL high pulse width tWH 100 ns Data setup time tDS 50 ns Data hold time tDH 50 ns CE delay time tD3 1.0 µs CL delay time tD4 50 CE delay time tD5 LD pulse width tW Data delay time tD1 Data delay time tD2 ns 100 fs = 44.1 kHz 136 fs = 88.2 kHz 68 CL = 30 pF CL = 30 pF ns µs µs 100 ns 100 ns Input mode Output mode No. 5543-6/15 LC89051V Microcontroller Interface Block AC Characteristics at Ta = –30 to +75°C, VDD = 3.0 to 5.5 V (when CKSEL is high) Parameter Symbol Conditions min typ max Unit SCLK low pulse width tWL 100 ns SCLK high pulse width tWH 100 ns Setup time tDS 50 ns Hold time tDH 50 ns Delay time tD 100 µs DQSY pulse width tW XLAT pulse width fs = 44.1 kHz 136 µs fs = 88.2 kHz 68 µs tWLA Data delay time tD1 Data delay time tD2 100 CL = 30 pF CL = 30 pF ns 100 ns 100 ns Input mode Output mode No. 5543-7/15 LC89051V Functions 1. Data Input and Output (DIN1, DIN2, E/DOUT) The DIN1 pin has a built-in amplifier, and can receive signals with an amplitude of about 400 mVp-p (coaxial input). The DIN2 pin is only for use in optical modules. Note that although the data input pins are controlled by the microcontroller, DIN1 can be selected when a microcontroller is not used. The microcontroller interface pins must be tied low in such applications. The E/DOUT normally outputs channel status information. However, it can be set to output either the input bi-phase data or the validity flag by command codes from the microcontroller. 2. PLL (R, VIN, VCO, AVOCK) This circuit includes a built-in VCO and supports sampling frequencies of 32, 44.1, and 48 kHz. This LSI can also receive at the 2× sampling frequencies of 64 kHz, 88.2 kHz, and 96 kHz, but only when operating from a 5-V power-supply voltage. However, the demodulated data and clock output during double speed reception follow the received sampling frequency, and the transmission format for 2×-speed data must follow the IEC958 standard. The built-in VCO is controlled by the resistors connected to the R and VIN pins. The resistor connected to R functions as both the VCO gain control and as temperature compensation. The VIN pin sets the VCO free-running frequency. Recommended circuit constants are shown in the sample application circuit. Note that the VCO free-running frequency varies with temperature and with manufacturing variations between samples. The recommended circuit constants shown in the sample application circuit take these variations into account so that the PLL circuit lockup characteristics are not adversely affected. These values are not designed to reduce variations in the free-running frequency. The VCO pin is the PLL loop filter pin. The loop filter is formed by attaching an external capacitor and a resistor to this pin. See the sample application circuit for these circuit constants. PLL Loop Filter Structure The PLL circuit will be reset within a fixed period when PLL lock pull-in fails if a continuously operating clock of no more than 50 kHz is input to the AVOCK pin. This allows incorrect PLL operation to be avoided. 3. Clock Settings and Output (FS128, BCK, LRCK, DATAOUT, CKSEL, CKOUT) A 128fs clock signal is output from the FS128 pin. Figure 1 shows the output timing for the BCK, LRCK, and DATAOUT pins. The CKOUT clock output is set by the CKSEL pin as listed in the table below. CKSEL CKOUT L 384fs clock output H 512fs clock output The microcontroller interface format is also set by CKSEL as listed in the table below. CKSEL Microcontroller interface L Figure 2 H Figure 3 No. 5543-8/15 LC89051V Figure 1 Data Output Timing No. 5543-9/15 LC89051V Figure 2 Microcontroller Interface Timing 1 No. 5543-10/15 LC89051V Figure 3 Microcontroller Interface Timing 2 No. 5543-11/15 LC89051V Microcontroller Interface (SCLK/CL, XLAT/CE, SWDT/DI, SRDT/DO, DQSY/LD) 1. Data input and output addresses are allocated as follows: Figure 2: Microcontroller Interface Timing 1 Data input or output Figure 3: Microcontroller Interface Timing 2 B0 B1 B2 B3 A0 A1 A2 A3 B0 B1 B2 B3 A0 A1 A2 Data input F7 1 1 1 0 1 1 1 1 EA 0 1 0 1 0 1 1 A3 1 C bit output F8 0 0 0 1 1 1 1 1 E9 1 0 0 1 0 1 1 1 Subcode Q, ID output F9 1 0 0 1 1 1 1 1 E8 0 0 0 1 0 1 1 1 2. The input command codes control the following setting: • System stop • Data input pin setting • Input bi-phase data output selection • Validity flag output selection • Audio data output format setting DI1: Stops VCO operation and thus stops the system. DI1 L H System Operating Stopped DI2: Selects which input data to demodulate. DI2 L H Data demodulation input DIN1 DIN2 DI3 and DI4: Select the E/DOUT pin output. DI3 L H DI4 L H L H E/DOUT Emphasis data output Validity flag output DIN1 input data output DIN2 input data output DI5 and DI6: Set the audio data output format. DI5 DI6 DATAOUT L L H H 16-bit right- 20-bit rightjustified justified MSB first LSB first L H 20-bit rightjustified MSB first 20-bit leftjustified MSB first All bits are set low immediately after XMODE is switched from low to high. DI0 and DI7 are not used. No. 5543-12/15 LC89051V 3. The following output settings can be controlled: • Channel status (C bit) output • Subcode Q data output • Start ID and shortening ID detection for DAT with subcodes C bit output • This IC only handles the first 32 bits. • The flag is fixed at the high level (only when CKSEL is high), and the data format is LSB first. • Error and update checking is not applied to the data. • The internal shift register is reset if a PLL lock error occurs. • Since the channel status information consists of 192 frames, a fixed period must be provided between data readout operations. 1 × 192 (ms) < (the interval between data readout operations) fs Subcode Q output • Subcode Q can be read out after the fall of the DQSY/LD signal. Also note that the data is updated every time this signal falls. However, this signal will not be output (fall) unless 96-bit subcode Q data (including the CRC check bits) is input. • The flag outputs a high when the CRC check passes, and low if the CRC check fails. Besides, the shift clock SCLK is required to be input regardless of the CRC flag status after latch pulse input. • The bit order is LSB first within each byte of the 80 bits of subcode Q data. ID detection • The start ID and shortening ID are only detected when the DAT category code (1100000L) is received. • These IDs are detected as follows: — A low pulse is output from DQSY/LD if a start ID (R0) or a shortening ID (L1) is detected following a sync signal (L0). — After this signal, data can be read out from SRDT/DO by inputting the same address value as that used for subcode Q data to SWDT/DI. Figure 4 User Data for DAT with Subcodes • The table below shows the relationship between the sync signal (L0), the start ID (R0), the shortening ID (L1), and the data output. (L0): SYNC H (R0): Start ID H L (L1): Shortening ID L H Flags + 80 data bits Detected ID H all H all L Start ID Shortening ID • Output pins The output scheme used for SRDT/DO differs depending on the microcontroller interface format selected by CKSEL Format SRDT/DO L Figure 2 High open-drain output H Figure 3 Three-state output No. 5543-13/15 LC89051V Error (ERROR) The ERROR pin goes high if there is an error in the input data or if the PLL is unlocked. It holds the high level for about 100 to 300 ms after data demodulation returns to normal and then goes low. The table below lists the data processing when an error has occurred. DATAOUT C bit Sub Q ID E/DOUT Up to 8 consecutive parity errors Type of error Previous data value Output Output Output Output Over 8 consecutive parity errors L Output Output Output Output PLL lock error L L L L L System Reset (XMODE) Normal system operation is started by setting XMODE high after the power supply has risen above at least 4.5 V (3.0 V). After power is applied, the system will be reset if a low level is applied once more to the XMODE pin. If XMODE is set low, the VCO free-running oscillator clock is output from CKOUT. Figure 5 XMODE Pin Operation No. 5543-14/15 LC89051V Sample Application Circuit Circuit constants Value Item Symbol 5.0-V operation Standard speed Resistors Capacitors 2× speed 3.3-V operation Standard speed R1 24 kΩ 24 kΩ 24 kΩ R2 5.1 kΩ 5.1 kΩ 5.1 kΩ R3 5.1 kΩ 12 kΩ 5.1 kΩ R4 150 Ω 150 Ω 150 Ω C1 0.1µF 0.1µF 0.1µF C2 0.01 µF 0.01 µF 0.01 µF ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 1997. Specifications and information herein are subject to change without notice. No. 5543-15/15