Ordering number : EN*5154B CMOS LSI LC895194 CD-ROM Error Correction LSI with On-Chip ATA-PI (IDE) Interface Preliminary Functions Package Dimensions CD-ROM error detection and correction, ATA-PI (IDE) interface (including the register and other blocks) unit: mm 3214-SQFP144 Features [LC895194] • ATA-PI (IDE) interface • Supports 16×-speed playback (with IORDY): Using 16× 70 ns DRAMs • 16.6 MB/s transfer rate: Using 16× 70 ns DRAMs • Supports the use of from 1 M to 32 M of buffer RAM. (DRAM) • Allows the user to arbitrarily set the CD main channel and C2 flag areas in buffer RAM. • Batch transfer function (function for transferring the CD main channel and C2 flag data in one operation) • Multi-transfer function (function for sending multiple blocks in one operation) SANYO: SQFP144 Specifications Absolute Maximum Ratings at VSS = 0 V Parameter Symbol Maximum supply voltage Conditions Ratings Unit VDD max Ta = 25°C –0.3 to +7.0 V I/O voltages VI, VO Ta = 25°C –0.3 to VDD + 0.3 V Allowable power dissipation Pd max Ta ≤ 70°C 550 mW Operating temperature Topr –30 to +75 °C Storage temperature Tstg –55 to +125 °C Soldering heat resistances (pins only) 10 seconds I/O power II, IO 235 °C ±20* mA Unit Note: * Per cell for basic I/O cells Allowable Operating Ranges at Ta = –30 to +75°C, VSS = 0 V min typ max Supply voltage Parameter Symbol VDD Conditions 4.5 5.0 5.5 V Input voltage range VIN 0 VDD V SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN N3097HA(OT) /81095HA (OT) No. 5154-1/7 LC895194 DC Characteristics at VSS = 0 V, VDD = 4.5 to 5.5 V, Ta = –30 to +75°C Parameter Symbol Applicable Pins* (See below) Input high level voltage VIH Input low level voltage VIL Input high level voltage VIH Input low level voltage VIL Input high level voltage VIH Input low level voltage VIL Input high level voltage VIH Input low level voltage VIL Input high level voltage VIH Input low level voltage VIL Output high level voltage VOH IOH = –2 mA Output low level voltage VOL IOL = 2 mA Output high level voltage VOH IOH = –8 mA Output low level voltage VOL IOL = 8 mA Output high level voltage VOH IOH = 4 mA Output low level voltage VOL IOL = 24 mA Output high level voltage VOH IOH = –2 mA Output low level voltage VOL IOL = 2 mA Output low level voltage VOL IOL = 2 mA (11) Output low level voltage VOL IOL = 24 mA (12) TTL compatible: (1) TTL compatible, with pull-up resistor: (13) TTL compatible, with pull-down resistor: (2) TTL compatible, Schmitt: (3), (5), and (14) COMS compatible, Schmitt: (4) (8), (10), and (13) (7) (9), and (14) (6) min typ max Unit 2.2 — — — — 0.8 V V 2.2 — — V — — 0.8 V 2.2 — — V — — 0.8 V 2.4 — — V — — 0.8 V 0.8 VDD — — V — — 0.2 VDD V VDD – 2.1 — — V — — 0.4 V VDD – 2.1 — — V — — 0.4 V VDD – 2.1 — — V — — 0.4 V VDD – 2.1 — — V — — 0.4 V — — 0.4 V — — 0.4 V IIL VI = VSS, VDD: (1), (3), (4), (9), and (14) –10 — +10 µA Output leakage current IOZ For high-impedance outputs: (6), (12), and (14) –10 — +10 µA Pull-up resistance RUP (13) 40 80 160 kΩ Pull-down resistance RDN (2), (5) 40 80 160 kΩ Input voltage hysteresis VHYS (3), and (14) 0.8 1.0 1.3 mV Input leakage current Note: * The entries in the “Applicable Pins” column specify the following pin sets. [Input] 1: CSCTRL, SUA0 to SUA6 2: TEST0 to TEST4 3: DA0 to DA2, ZCS1FX, ZCS3FX, ZDIOR, ZDIOW, ZDMACK, ZHRST, ZRESET, BCK, C2PO, LRCK, SDATA 4: ZCS, ZRD, ZWR 5: WFCK, SCOR [Output] 6: ZINT1 7: MCK, MCK2 8: ZINT, ZSWAIT 9: DMARQ, HINTRQ 10: RA0 to RA9, ZCAS0, ZCAS1, ZLWE, ZOE, ZRAS0, ZRAS1, ZUWE 11: ZRSTCPU, ZRSTIC 12: IORDY, ZIOCS16 [I/O] 13: D0 to D7, IO0 to IO15 14: DD0 to DD15, ZDASP, ZPDIAG Note: XTAL, XTALCK The above pins are not included in the DC characteristics. Sample Recommended Oscillator Circuit R1 = 120 kΩ R2 = 47 kΩ C1 = 30 pF For a crystal oscillator frequency of 16.9344 MHz. Alternatively: R1 = 3.3 kΩ R2 = None C1 = 5 pF For a crystal oscillator frequency of 33.8688 MHz. For an oscillator frequency of 33.8688, the third harmonic is used. This means that precise component values will be influenced by the printed circuit board. Consult the manufacturer of the crystal to determine the circuit constants for this frequency. No. 5154-2/7 LC895194 Block Diagram Each block register R0 to R99 Note: 1. 2. 3. 4. 5. 6. 7. 8. 9. WFCK, SCOR BCK, SDATA, LRCK, C2PO DD0 to DD15, ZDASP, ZPDIAG ZCS1FX, ZCS3FX, DA0 to DA2, ZDIOR, ZDIOW, ZDMACK DMARQ, HINTRQ, ZIOCS16, IORDY, ZHRST ZRD, ZWR, SUA0 to SUA6, ZCS, CSCTRL D0 to D7 IO0 to IO15 RA0 to RA9, ZRAS0, ZRAS1, ZCAS0, ZCAS1, ZOE, ZUWE, ZLWE Note: HISIDE (WD25C32) is made by WESTERN DIGITAL. No. 5154-3/7 LC895194 Pin Functions Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin Pin No. Symbol Type 1 VSS0 P Function 2 ZRAS0 O Buffer DRAM RAS signal output 0 (This pin is used normally.) 3 ZRAS1 O Buffer DRAM RAS signal output 1 4 VSS0 P 5 ZCAS0 O Buffer DRAM CAS signal output 0 (This pin is used normally.) 6 ZCAS1 O Buffer DRAM CAS signal output 1 7 VSS0 P 8 ZOE O Buffer RAM output enable 9 ZUWE O Buffer RAM upper write enable 10 ZLWE O Buffer RAM lower write enable 11 RA0 O 12 RA1 O 13 RA2 O 14 RA3 O 15 RA4 O 16 RA5 O 17 RA6 O 18 VDD P 19 VSS0 P 20 RA7 O 21 RA8 O 22 RA9 O 23 RA0 to RA9 are the data buffer DRAM address lines. NC 24 25 RA0 to RA9 are the data buffer DRAM address lines. NC TEST0 NC 26 TEST1 NC 27 TEST2 NC 28 TEST3 NC 29 Test pins. NC 30 IO0 B 31 IO1 B 32 IO2 B 33 IO3 B 34 IO4 B 35 IO5 B 36 VSS0 P 37 VDD P 38 IO6 B 39 IO7 B 40 IO8 B 41 IO9 B 42 IO10 B 43 IO11 B 44 IO12 B 45 IO13 B 46 IO14 B 47 IO15 B 48 EXCK O 49 WFCK I 50 SBSO I 51 SCOR I Data buffer RAM data I/O These pins have built-in pull-up resistors. Data buffer RAM data I/O These pins have built-in pull-up resistors. SUB-CODE input/out pin Note: 1. NC (no connection) pins must be left open. 2. Pin names (signal names) that begin with a Z have negative (inverted) logic. 3. VSS0 is the logic system ground and VSS1 is the IDE interface driver ground. Continued on next page. No. 5154-4/7 LC895194 Continued from preceding page. Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin Pin No. Symbol Type 52 VSS0 P 53 VSS0 TEST4 P 54 55 VSS0 P 56 57 VSS0 ZINT1 O 58 VSS0 P 59 VSS0 P 60 VSS0 61 I Function Test input. This pin must be tied low. P Interrupt request signal output to the microcontroller from the IDE block P NC 62 NC 63 VSS0 P 64 SDATA I 65 BCK I 66 LRCK I CD-DSP interface 67 C2PO I 68 MCK2 O 69 VSS0 P 70 XTALCK I Crystal oscillator input 71 XTAL O Crystal oscillator output 72 VSS0 P XTALCK 1/1, 1/2, 1/512, and stop output 73 VDD P 74 MCK O 75 VSS0 P 76 ZRSTIC O Reset signal to drive reset IC 77 CSCTRL I Selects active high or active low for the microcontroller CS line. 78 ZRESET I LSI reset 79 ZRD I Microcontroller data read signal input 80 ZWR I Microcontroller data write signal input 81 ZCS I Input for the register chip select signal from the microcontroller 82 VSS0 P 83 SUA0 I 84 SUA1 I 85 SUA2 I 86 SUA3 I 87 SUA4 I 88 SUA5 I 89 SUA6 I 90 VDD P 91 VSS0 P 92 D0 B 93 D1 B 94 D2 B 95 D3 B 96 D4 B 97 D5 B 98 D6 B 99 D7 B 100 ZINT O XTALCK 1/1, 1/2, and stop output Microcontroller register select signals Microcontroller data signals These pins have built-in pull-up resistors. Interrupt request signal output to the microcontroller Note: 1. NC (no connection) pins must be left open. 2. Pin names (signal names) that begin with a Z have negative (inverted) logic. 3. VSS0 is the logic system ground and VSS1 is the IDE interface driver ground. Continued on next page. No. 5154-5/7 LC895194 Continued from preceding page. Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin Pin No. Symbol Type 101 ZRSTCPU O Reset signal to CPU 102 ZSWAIT O Wait signal output to the microcontroller 103 ZHRST I 104 ZDASP B 105 ZCS3FX I 106 ZCS1FX I 107 DA2 I 108 VSS0 P 109 VDD P 110 DA0 I 111 ZPDIAG B 112 DA1 I 113 ZIOCS16 O 114 HINTRQ O 115 ZDMACK I 116 VSS1 P 117 IORDY O 118 ZDIOR I 119 ZDIOW I 120 DMARQ O 121 DD15 B 122 VSS1 P 123 DD0 B 124 DD14 B 125 DD1 B 126 DD13 B 127 VSS1 P 128 VDD P 129 DD2 B 130 DD12 B 131 DD3 B 132 VSS1 DD11 P 133 134 DD4 B 135 DD10 B 136 VSS1 P 137 VDD P 138 DD5 B 139 DD9 B 140 DD6 B Function ATAPI control signals ATAPI control signals ATAPI control signals ATAPI data bus ATAPI data bus ATAPI data bus B 141 VSS1 P 142 DD8 B 143 DD7 B 144 VDD P ATAPI data bus ATAPI data bus ATAPI data bus Note: 1. NC (no connection) pins must be left open. 2. Pin names (signal names) that begin with a Z have negative (inverted) logic. 3. VSS0 is the logic system ground and VSS1 is the IDE interface driver ground. No. 5154-6/7 LC895194 ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 1997. Specifications and information herein are subject to change without notice. No. 5154-7/7