Ordering number : EN5262 NMOS LSI LM7001J, 7001JM Direct PLL Frequency Synthesizers for Electronic Tuning Features Package Dimensions • The LM7001J and LM7001JM are PLL frequency synthesizer LSIs for tuners, making it possible to make up high-performance AM/FM tuners easily. • These LSIs are software compatible with the LM7000, but do not include an IF calculation circuit. • The FM VCO circuit includes a high-speed programmable divider that can divide directly. • Seven reference frequencies: 1, 5, 9, 10, 25, 50, and 100 kHz • Band-switching outputs (3 bits) • Controller clock output (400 kHz) • Clock time base output (8 Hz) • Serial input circuit for data input (using the CE, CL, and DATA pins) unit: mm 3006B-DIP16 [LM7001J] SANYO: DIP16 unit: mm 3036B-MFP20 [LM7001JM] SANYO: MFP20 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN D3095HA (OT) No. 5262-1/8 LM7001J, 7001JM Pin Assignments Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Symbol Conditions Allowable power dissipation Unit VDD1, VDD2 –0.3 to +7.0 VIN1 max CE, CL, DATA –0.3 to +7.0 V VIN2 max Input pins other than VIN1 –0.3 to VDD + 0.3 V V VOUT1 max SYC –0.3 to +7.0 V VOUT2 max BO1 to BO3 –0.3 to +13 V VOUT3 max Output pins other than VOUT1 and VOUT2 Maximum output current Ratings VDD max IOUT max Pd max BO1 to BO3 –0.3 to VDD + 0.3 V 0 to 3.0 mA Ta = 85°C: LM7001J (DIP16) 300 mW Ta = 85°C: LM7001JM (MFP20) 180 mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V Parameter Supply voltage Symbol Conditions Ratings Unit VDD1 VDD1, PLL circuit operating 4.5 to 6.5 V VDD2 VDD2, crystal oscillator time base 3.5 to 6.5 V Input high-level voltage VIH CE, CL, DATA 2.2 to 6.5 V Input low-level voltage VIL CE, CL, DATA 0 to 0.7 V VOUT1 SYC 0 to 6.5 V VOUT2 BO1 to BO3 0 to 13 V IOUT BO1 to BO3, VDD = 4.5 to 6.5 V 0 to 3.0 mA fIN1 XIN, sine wave, capacitor coupled 1.0 to 7.2 typ to 8.0 MHz fIN2 FMIN, sine wave, capacitor coupled*1, s*3 = 1 45 to 130 MHz fIN3 FMIN, sine wave, capacitor coupled*2, s*3 = 1 5 to 30 MHz 0.5 to 10 MHz Output voltage Output current Input frequency Crystal element for guaranteed oscillation Input amplitude fIN4 AMIN, sine wave, capacitor coupled, s*3 = 0 Xtal XIN to XOUT, CI ≤ 30 Ω VIN1 5.0 to 7.2 typ to 8.0 MHz XIN, sine wave, capacitor coupled 0.5 to 1.5 Vrms VIN2 FMIN, sine wave, capacitor coupled 0.1 to 1.5 Vrms VIN3 AMIN, sine wave, capacitor coupled 0.1 to 1.5 Vrms Note: 1. fref = 25, 50, or 100 kHz 2. fref = Reference frequencies other than those for *1. 3. “s” refers to the control bit in the serial data. No. 5262-2/8 LM7001J, 7001JM Electrical Characteristics in the Allowable Operating Ranges Parameter Symbol Conditions min typ max Unit Rf1 XIN 1.0 MΩ Rf2 FMIN 500 kΩ Rf3 AMIN 500 Input high-level current IIH CE, CL, DATA: VIN = 6.5 V 5.0 µA Input low-level current IIL CE, CL, DATA: VIN = 0 V 5.0 µA VOL1 FMIN, AMIN: IOUT = 0.5 mA 3.5 V VOL2 SYC: IOUT = 0.1 mA, *1 0.3 V V Built-in feedback resistance Output low-level voltage Output off leakage current Output high-level voltage 0.02 kΩ VOL3 BO1 to BO3: IOUT = 2.0 mA 1.0 VOL4 PD1, PD2: IOUT = 0.1 mA 0.3 V IOFF1 SYC: VOUT = 6.5 V 5.0 µA 3.0 µA IOFF2 BO1 to BO3: VOUT = 13 V VOH PD1, PD2: IOUT = –0.1 mA 0.5 VDD V High-level 3-state off leakage current IOFFH PD1, PD2: VOUT = VDD 0.01 10.0 nA Low-level 3-state off leakage current IOFFL PD1, PD2: VOUT = 0 V 0.01 10.0 nA IDD1 VDD1 + VDD2: *2 25 40 mA IDD2 VDD2: PLL block stopped 2.0 3.5 mA CIN FMIN 2 3 pF Current drain Input capacitance 1 Note: 1. VDD = 3.5 to 6.5 V 2. With a 7.2 MHz crystal connected between XIN and XOUT, fIN2 = 130 MHz, VIN2 = 100 mVrms, other input pins at VSS, output pins open. Oscillator Circuit Example Kinseki, Ltd. HC43/U: 2114-84521 (1): CL = 10 pF, C1 = 15 (10 to 22) pF, C2 = 15 pF HC43/U: 2114-84521 (2): CL = 16 pF, C1 = 22 (15 to 33) pF, C2 = 33 pF Nihon Denpa Kogyou, Ltd. NR-18: LM-X-0701: CL = 10 pF, C1 = 15 pF, C2 = 15 pF Since the circuit constants in the crystal oscillator circuit depend on the crystal element used and the printed circuit board pattern, we recommend consulting with the manufacturer of the crystal element concerning this circuit. No. 5262-3/8 LM7001J, 7001JM Equivalent Circuit Block Diagram Pin Functions Symbol Description SYC Controller clock (400 kHz) XIN, XOUT Crystal oscillator (7.2 MHz) FMIN, AMIN Local oscillator signal input CE, CL, DATA BO1 to BO3 VDD1, VDD2, VSS PD1, PD2 Data input Band data output. BO1 can be used as a time base output (8 Hz). Power supply (Apply power to both VDD1 and VDD2 when the PLL circuit is operating. VDD2 is the crystal oscillator and time base power supply. Internal data cannot be maintained on VDD2 only.) Charge pump output No. 5262-4/8 LM7001J, 7001JM Data Input Timing VIH = 2.2 to 6.5 V, VIL = 0 to 0.7 V, Xtal = 5.00 to 7.20 (typ) to 8.00 MHz Data acquisition: On the CL rising edge Note: Data transfers must be started only after the crystal oscillator is operating normally, i.e., after a proper input signal has been supplied to XIN. Parameter Symbol Xtal: 7.20 MHz Xtal: for frequencies other than 7.2 MHz 1 ×8 f Xtal 1 ×8 f Xtal 1 ×8 f Xtal 1 ×8 f Xtal 1 ×8 f Xtal 1 ×8 f Xtal Example: XIN = 2.048 MHz ] × 1.35 At least 5.27 µs ] × 1.35 At least 5.27 µs ] × 1.35 At least 5.27 µs ] × 1.35 At least 5.27 µs ] × 1.35 At least 5.27 µs ] × 1.35 At least 5.27 µs Enable setup time tES At least 1.5 µs At least [ Enable hold time tEH At least 1.5 µs At least [ Data setup time tSU At least 1.5 µs At least [ Data hold time tHD At least 1.5 µs At least [ Clock low-level time tLO At least 1.5 µs At least [ Clock high-level time tHI At least 1.5 µs At least [ Rise time tR Up to 1 µs Up to 1 µs Up to 1 µs Fall time tF Up to 1 µs Up to 1 µs Up to 1 µs No. 5262-5/8 LM7001J, 7001JM Data Input (1) D0 (LSB) to D13 (MSB): Divisor data FMIN uses D0 to D13 and AMIN uses D4 to D13. Sample calculation ① FM 100 kHz steps (fref = 100 kHz) FM VCO = 100.7 MHz (FM RF = 90.0 MHz, IF = 10.7 MHz) Divisor = 100.7 MHz (FM VCO) ÷ 100 kHz (fref) = 1007 → 3EF(HEX) ② AM 10 kHz steps (fref = 10 kHz) AM VCO = 1450 kHz (AM RF = 1000 kHz, IF = 450 kHz) Divisor = 1450 kHz (AM VCO) ÷ 10 kHz (fref) = 145 → 91(HEX) (2) T0 and T1 are LSI test bits and both should be set to 0. (3) B0 to B2, TB: Band data Time base data Note: *: Determined by R0 to R3. See item (4) on next page. Input Output B0 B1 B2 TB BO1 BO2 0 0 0 0 * * BO3 * 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 1 1 0 0 1 1 1 0 0 0 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 0 1 1 1 0 1 1 1 0 0 0 1 TB * * ✕ 1 0 1 TB 1 0 ✕ 0 1 1 TB 0 1 ✕ 1 1 1 TB 1 1 1 0 0 1 TB 0 0 ✕: Don’t care TB: 8 Hz No. 5262-6/8 LM7001J, 7001JM (4) R0 to R2: Reference frequency data R0 R1 R2 BO1 BO2 0 0 0 fref [kHz] 100 1 1 BO3 0 0 0 1 50 1 1 0 0 1 0 25 1 1 0 0 1 1 5 0 0 1 1 0 0 10 1 0 1 1 0 1 9 1 0 1 1 1 0 1 0 1 1 1 1 1 5 0 0 1 Note: The values listed for BO1, BO2, and BO3 are for the case when the B0 to B2 data is set to all zeros. (5) S: Divider selection data 1: FMIN, 0: AMIN Notes on PLL IC Usage 1. PLL IC printed circuit board patterns ① Power supply pins A capacitor must be inserted between the VDD and VSS power supply pins for noise exclusion. This capacitor must be located as close as possible to these pins. ② FMIN and AMIN pins The coupling capacitors must be located as close as possible to these pins. ③ PD pins, low-pass filter Since those are high-impedance pins, they are susceptible to noise. Therefore, the pattern should be kept as short as possible and the area around this circuit should be covered by the ground pattern. 2. Initial states of the output ports (BO1 to BO3) The initial states of the output ports after power is applied are undefined until data has been transferred. In particular, it is possible for the BO1 and BO3 pins to output the internal clock, so data must be transferred as soon as possible. However, note that the LSI cannot accept data until the crystal oscillator is operating normally. No. 5262-7/8 LM7001J, 7001JM 3. VCO The VCO circuit is designed so that it does not stop oscillating even if the control voltage (Vtune) becomes 0 V. (This is because the PLL circuit could become deadlocked if the VCO stopped.) ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. No. 5262-8/8