Ordering number : EN*5785 CMOS LSI LC895297 Full CAV 20× CD-ROM Decoder with Built-in ATA-PI (IDE) Interface and CD-DSP Preliminary Overview The LC895297 is a single-chip CD-ROM decoder and CD-DSP system that supports full CAV 20× operation and includes a built-in ATA-PI (IDE) interface. Functions • Full CAV 20× CD-DSP and CD-ROM decoder functions with built-in ATA-PI (IDE) interface Features [CD-ROM Decoder and ATA-PI (IDE) Interface Blocks] • • • • • • • • • Full CAV 20× operation ATA-PI (IDE) interface Supports the use of EDO DRAM. Supports the use of up to 4 Mbits of buffer RAM. The user can set up arbitrary CD main channel and C2 flag areas in buffer RAM. Batch transfer function (function that automatically transfers the CD main channel and C2 flag data in a single operation.) Multi-block transfer function (function that automatically transfers multiple blocks in a single operation.) DVD ECC interface Intelligent functions [CD-DSP Block] • The IC inputs a high-frequency signal, slices that signal at the correct level, converts that result to an EFM coded signal, and compares the phase with that of the built-in VCO. • Uses an external 16.9344-MHz crystal element to generate a standard clock and to correctly generate the required internal timings. • Performs frame synchronization, signal detection, protection, and insertion, and assures stable data readout. • Demodulates the EFM coded signal to produce 8-bit symbol data. • After applying a CRC check to the subcode Q signal, outputs that signal to a microprocessor over a parallel I/O channel. • Performs unscrambling and de-interleaving to reorder the demodulated EFM signal in the prescribed manner. • Performs error code detection and correction, and flag processing. (C1: dual errors, C2: four errors) • Sets the C2 flags based on the C1 flags and a C2 check, and performs interpolation or muting depending on the C2 flags. Adopts a 2-point interpolation circuit, and converges the signal to the muting level if the C2 flags indicate over 2 consecutive uncorrectable errors. • Accepts the input of commands from a control microprocessor over an 8-bit parallel interface. Supports track jump, disc motor start/stop, muting on/off, and track counting commands. • Can perform arbitrary track counts. • Includes CAV audio functions. • Adopts zero-cross muting. • Includes 8× oversampling digital filters. • D/A converter with PWM output. • Includes independent left and right channel digital attenuators. • Provides digital deemphasis. • Supports bilingual functions. Package Dimensions unit: mm 3230-SQFP176 [LC897297] SANYO: SQFP176 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN 22898HA (OT) No. 5785-1/9 LC895297 Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Maximum supply voltage VDD max Input and output voltage VI, VO Allowable power dissipation Pd max Conditions Ratings Unit –0.3 to +7.0 V –0.3 to VDD+0.3 V Ta ≤ 70°C *1 500 mW Operating temperature Topr –30 to +70 Storage temperature Tstg –55 to +125 °C 10s 235 °C Per individual input or output cell ±20 mA Soldering conditions (pins only) Input and output current II, IO °C Note 1: Applications that use this IC must adopt heat dissipation measures, such as the insertion of a thermally conductive sheet. Allowable Operating Ranges at Ta = –30 to +70°C, VSS = 0 V Parameter Symbol Ratings Conditions min typ Unit max [Input and Output Cell Power Supply] Supply voltage VDD 4.5 Input voltage range VIN 0 Supply voltage VDD 3.9 Input voltage range VIN 0 5.0 5.5 V VDD V [Internal Cell Power Supply] 4.0 4.1 V VDD V Electrical Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 4.5 to 5.5 V Parameter Symbol Conditions Input high-level voltage VIH Input low-level voltage VIL Input high-level voltage VIH TTL levels. Applicable pins: (1) Input low-level voltage VIL Pull-up resistor included. Ratings min typ Unit max 2.2 V TTL levels. Applicable pins: (10) and (13) 0.8 2.2 Input high-level voltage VIH TTL levels. Applicable pins: (2), (3), and (15) VIL Schmitt inputs. Input high-level voltage VIH CMOS levels: Applicable pins: (14) 0.7 VDD 0.8 VDD VIL Input high-level voltage VIH CMOS levels: Applicable pins: (4) Input low-level voltage VIL Schmitt inputs. Output high-level voltage VOH IOH = –2 mA: Applicable pins: (5), (1), (9), (10), and (15) Output low-level voltage VOL IOL = 2 mA: Applicable pins: (5), (1), (9), (10), and (15) V 0.8 Input low-level voltage Input low-level voltage V 2.4 V 0.8 V V 0.3 VDD V V 0.2 VDD VDD – 2.1 V V 0.4 V Output high-level voltage VOH IOH = –4 mA: Applicable pins: (3) and (6) Output low-level voltage VOL IOL = 24 mA: Applicable pins: (3) and (6) 0.4 V Output low-level voltage VOL IOL = 2 mA: Applicable pins: (7) and (11) 0.4 V Output low-level voltage VOL IOL = 24 mA: Applicable pins: (12) 0.4 V Input leakage current IIL VI = VSS, VDD: Applicable pins: (2), (3), (4), (10), and (15) Output leakage current IOZ In high-impedance output mode: Applicable pins: (3), (6), (7), (9), (10), (12), and (15) Pull-up resistance RUP Applicable pins: (1) and (11) VDD – 2.1 V –10 +10 µA –10 +10 µA 160 kΩ 40 80 The applicable pin sets are as follows: [INPUT] (2) ZRESET, ZDMACK, ZHRST, DA0to DA2, ZCS1FX, ZCS3FX, ZDIOR, ZDIOW, FG (4) ZCSCTRL, ZCS, ZRD, ZWR, HFL, TES (14) DEFI (13) SUA0 o SUA6 [OUTPUT] (6) DMARQ, HINTRQ (5) RA0 to RA8, ZRAS0, ZCAS0, ZOE, ZUWE, ZLWE, C2F, ROMXA, FSX, EFLG, PCK, FSEQ, TOFF, TGL, 4.2M, WRQ, RWC, COIN, ZCQCK, RCHP, RCHN, LCHP, LCHN (7) ZRSTCPU, ZRSTIC (9) JP+, JP–, SPO (11) ZINT0, ZINT1, ZSWAIT Continued on next page. (12) IORDY, ZIOCS16 No. 5785-2/9 LC895297 Continued from preceding page. [INOUT] (1) D0 to D7, IO0 to IO15 (3) DD0 to DD15, ZDASP, ZPDIAG (10) IOP0 to IOP7 (15) DRESP, DREQ Note: XTAL, XTALCK, R0, VCNT0, PDO0, R1, VCNT1, PO11, PO21, BSN1, R2, VCNT2, PO12, PO22, and BSN2 The above pins are not covered by the electrical characteristics. The 1-bit D/A converter block pins are only measured using a logic tester; no analog measurements are performed. EFM Input and Output Signals Electrical Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 4.5 to 5.5 V Parameter Symbol Input high-level voltage VIH Input low-level voltage VIL Conditions Micro-signal amplifier. Applicable pins: EFMI Output high-level voltage VOH IOH = –4 mA. Applicable pins: EFMO and ZEFMO Output low-level voltage VOL IOL = 4 mA. Applicable pins: EFMO and ZEFMO Input leakage current Output leakage current Ratings min typ Unit max 3.2 V 1.8 VDD – 2.1 V V 0.4 V IIL VI = VSS, VDD: Applicable pins: EFMI –10 +10 µA IOZ In high-impedance mode: Applicable pins: EFMO and ZEFMO –10 +10 µA External Clock Generator PLL Circuit Figure 1 PLL Circuit Symbol Currently used value R1 7.5 kΩ Notes VCO adjustment resistor R2 10 kΩ Low-pass filter resistor R3 200 Ω Low-pass filter phase compensation resistor C1 0.1 µF Low-pass filter capacitor C2 0.1 µF VCO bias stabilization capacitor While the circuit structure is fixed, the values of the components will vary with the circuit board capacitance and other application circuit parameters. No. 5785-3/9 LC895297 Block Diagram DVD interface IDE interface *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 *11 *12 *13 *14 **1 External buffer RAM DEFI, EFMI, HFL, TES 4.2M, EFMO, PCK, FSEQ, TOFF, TGL, JP+, JP–, RWC, COIN, ZCQCK RCHP, RCHN, LCHP, LCHN DD0 to DD15, ZDASP, ZPDIAG ZCS1FX, ZCS3FX, DA0 to DA2, ZDIOR, ZDIOW, ZDMACK, ZHRST DMARQ, HINTRQ, ZIOCS16, IORDY ZRD, ZWR, ZCS, ZCSCTRL, SUA0 to SUA6 D0 to D7 IO0 to IO15 RA0 to RA8, ZRAS0, ZCAS0, ZOE, ZUWE, ZLWE DREQ DRESP IOP0 to IOP7 R0, VCNT0, PDO0 HISIDE (WD25C32) is made by WESTERN DIGITAL No. 5785-4/9 LC895297 Pin Functions I : Input pin, O: Output pin, B : Bidirectional pin, P: Power supply pin, NC: Not connected Pin No. Pin name Type 1 AVSS0 P Function 2 R0 I VCO bias resistor connection 3 VCNT0 I VCO control voltage input Charge pump output 4 PDO0 O 5 TEST0 I 6 TEST1 I 7 IOP0 (HDB7) B 8 IOP1 (HDB6) B 9 IOP2 (HDB5) B 10 IOP3 (HDB4) B General-purpose I/O ports 11 IOP4 (HDB3) B These pins are used for DVD ECC data input when the DVD interface is used. 12 IOP5 (HDB2) B 13 IOP6 (HDB1) B 14 IOP7 (HDB0) B 15 VDD2 P 4.0 V 16 TEST3 I Test pin 17 TEST4 I Test pin 18 DRESP I DVD ECC data latch signal input 19 DREQ O DVD ECC data request output 20 RCHP O 1-bit D/A converter right channel P output 21 RCHN O 1-bit D/A converter right channel N output 22 VDD1 P 1-bit D/A converter left and right channel power supply Test pins 23 VSS1 P 1-bit D/A converter right channel ground 24 LCHP O 1-bit D/A converter left channel P output 25 LCHN O 1-bit D/A converter left channel N output 26 VSS0 P 27 XTALCK I Crystal oscillator circuit input (16.9344 MHz) 28 XTAL O Crystal oscillator circuit output 29 VSS0 P 30 NC 31 ZRSTCPU O CPU reset signal output 32 ZRSTIC O Drive IC reset signal output 33 ZRESET I IC reset input 34 D7 B 35 D6 B 36 D5 B 37 D4 B Microcontroller data signal connection. 38 D3 B These pins include built-in pull-up resistors. 39 D2 B 40 D1 B 41 D0 B Continued on next page. No. 5785-5/9 LC895297 Continued from preceding page. I : Input pin, O: Output pin, B : Bidirectional pin, P: Power supply pin, NC: Not connected Pin No. Pin name Type 42 SUA0 I 43 SUA1 I 44 VDD0 P 45 VSS0 P 46 VDD2 P 47 SUA2 I 48 SUA3 I 49 SUA4 I 50 SUA5 I Function Microcontroller register selection 5V 4.0 V Microcontroller register selection 51 SUA6 I 52 ZCSCTRL I Microcontroller chip select active-low/high selection 53 ZCS I Register chip select signal input (from the microcontroller) 54 ZSWAIT O Wait signal output (to the microcontroller) 55 ZWR I Data write signal input (from the microcontroller) 56 ZRD I Data read signal input (from the microcontroller) 57 ZINT0 O 58 ZINT1 O 59 WRQ O Subcode Q output standby output 60 FSEQ O Synchronization signal detection output 61 C2F O C2 flag output for ROMXA 62 ROMXA O Interpolation data output for ROMXA 63 FSX (CK2) O 7.35-kHz signal output (Bit clock output for ROMXA) 64 EFLG (LRSY) O C1 and C2 error correction monitor output (LRSY output for ROMXA) 65 FG I FG pulse input for CAV control 66 VDD2 P 4.0 V P Interrupt request signal output (to the microcontroller) 67 VSS0 68 TEST2 I Test pin 69 ZEFMO O Inverted EFM signal output 70 EFMO O EFM signal output 71 EFMI I EFM signal input 72 VDD0 P 5V 73 JP– O 74 JP+ O 75 TGL O Tracking gain switching output 76 TOFF O Tracking off output 77 TES I Tracking error signal input. Schmitt input 78 HFL I Tracking detection signal input. Schmitt input 79 NC Track jump output 80 SPO O CAV control output 81 DEFI I Defect detection signal input 82 4.2M O 4.2336-MHz output 83 R1 I VCO bias resistor connection 84 BSN1 I Charge pump bias resistor connection 85 VCNT1 I VCO control voltage 86 PO11 O 87 PO21 O 88 AVDD1 P 89 AVSS1 P Charge pump outputs 4.0 V Continued on next page. No. 5785-6/9 LC895297 Continued from preceding page. I : Input pin, O: Output pin, B : Bidirectional pin, P: Power supply pin, NC: Not connected Pin No. Pin name Type 90 R2 I VCO bias resistor connection 91 BSN2 I Charge pump bias resistor connection 92 VCNT2 I VCO control voltage 93 PO12 O 94 PO22 O 95 VDD2 P 4.0 V 96 PCK O EFM data reproduction bit clock monitor 97 Function Charge pump outputs NC 98 ZCQCK O ASP command acquisition clock output 99 COIN O ASP command output 100 RWC O Output to the ASP read/write control input 101 ZRAS0 O Buffer RAM RAS signal output 102 ZCAS0 O Buffer RAM CAS signal output 103 ZOE O Buffer RAM output enable 104 VSS0 P 105 ZUWE O Buffer RAM upper write enable 106 ZLWE O Buffer RAM lower write enable 107 RA0 O 108 RA1 O 109 RA2 O 110 VDD0 P 111 VSS0 O 112 RA3 O 113 RA4 O 114 RA5 O 115 RA6 O 116 RA7 O 117 RA8 O 118 IO8 B 119 IO9 B 120 IO10 B P 121 VSS0 122 IO11 B 123 IO12 B 124 IO13 B 125 IO14 B Data buffer RAM address signal outputs 5V Data buffer RAM address signal outputs Data buffer RAM data input and output These pins include built-in pull-up resistors. 126 IO15 B Data buffer RAM data input and output 127 IO7 B These pins include built-in pull-up resistors. 128 IO6 B 129 IO5 B 130 IO4 B 131 IO3 B 132 VDD2 P 133 VSS0 P 134 IO2 B 135 IO1 B 136 IO0 B 4.0 V Data buffer RAM data input and output These pins include built-in pull-up resistors. Continued on next page. No. 5785-7/9 LC895297 Continued from preceding page. I : Input pin, O: Output pin, B : Bidirectional pin, P: Power supply pin, NC: Not connected Pin No. Pin name Type 137 ZHRST I 138 VSS2 P 139 DD7 B 140 DD8 B 141 DD6 B 142 DD9 B 143 VDD0 P 144 VSS2 P 145 DD5 B 146 DD10 B 147 DD4 B 148 DD11 B 149 VSS2 P 150 DD3 B 151 DD12 B 152 DD2 B 153 DD13 B 154 VDD0 P 155 VSS2 P 156 DD1 B 157 DD14 B 158 DD0 B 159 DD15 B 160 VSS2 P 161 DMARQ O 162 ZDIOW I 163 ZDIOR I 164 IORDY O 165 ZDMACK I 166 HINTRQ O 167 ZIOCS16 O 168 VSS2 P 169 DA1 I 170 ZPDIAG B 171 DA0 I 172 DA2 I 173 ZCS1FX I 174 ZCS3FX I 175 ZDASP B 176 AVDD0 P Function ATAPI control signal ATAPI data bus 5V ATAPI data bus ATAPI data bus 5V ATAPI data bus ATAPI control signal ATAPI control signal 4.0 V Pin names that start with the letter Z are negative-logic signals. The following power-supply voltages must be provided; VDD0: 5 V, VDD1 (for the 1-bit D/A converter): 5 V, and VDD2: 4.0 V. VSS0 is the logic system ground, VSS1 is the 1-bit D/A converter ground, and VSS2 is the IDE interface drive ground. No. 5785-8/9 LC895297 Thermal Design Since this IC supports operation at up to 20× speeds, it operates at extremely high speeds internally. Applications must take measures to dissipate the heat that results from this high-speed operation. IC operation is not guaranteed if adequate heat dissipation measures are not taken. Heat Dissipation Example Steel plate Thermally conductive sheet Applications must be designed with a thermally conductive sheet above the LC895297 and the LC895297 positioned so that the system chassis contacts the thermally conductive sheet. ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1998. Specifications and information herein are subject to change without notice. PS No. 5785-9/9