Ordering number : EN*5826 CMOS LSI LC78632RE Compact Disk Player DSP Preliminary Overview Package Dimensions The LC78632RE is a compact disc D/A signal-processing LSI for Video-CD players that provides a variable clock error correction (VCEC) mode. The LC78632RE demodulates the EFM signal from the optical pickup and performs de-interleaving, error detection, error correction, digital filtering, and other processing. The LC78632RE includes an on-chip 1-bit D/A converter, and executes commands sent from a control microprocessor. unit: mm 3174-QFP80E [LC78632RE] Features • VCEC support • Built-in PLL circuit for EFM detection (supports 4× playback) • 18KB RAM on chip • Error detection and correction (corrects two errors in C1 and four errors in C2) • Frame jitter margin: ±8 frames • Frame synchronization signal detection, protection, and insertion • Dual interpolation adopted in the interpolation circuit. • EFM data demodulation • Subcode demodulation • Zero-cross muting adopted • Servo command interface • 2fs digital filter • Digital de-emphasis • Built-in independent left- and right-channel digital attenuators (239 attenuation steps) • Supports the bilingual function • Left/right swap function • Built-in 1-bit D/A converter (third-order ∆∑ noise shaper, PWM output) • Built-in digital output circuit • CLV servo • Arbitrary track jumping (of up to 255 tracks) • Variable sled voltage (four levels) • Six extended I/O ports and 2 extended output ports • Built-in oscillator circuit using an external 16.9344 MHz or 33.8688 MHz (for 4× playback) element • Supply voltage: 4.5 to 5.5 V SANYO: QFP80E SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN D3097HA (OT) No. 5826-1/9 LC78632RE Equivalent Circuit Block Diagram No. 5826-2/9 LC78632RE Pin Assignment LC78632RE Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Maximum supply voltage Conditions Ratings VDD max Input voltage Output voltage Allowable power dissipation Unit –0.3 to +7.0 V VIN –0.3 to VDD + 0.3 V VOUT –0.3 to VDD + 0.3 Pd max 470 V mW Operating temperature Topr –30 to +75 °C Storage temperature Tstg –40 to +125 °C Allowable Operating Ranges at Ta = 25°C, VSS = 0 V Parameter Supply voltage Input high-level voltage Input low-level voltage Data setup time Data hold time Symbol Conditions min typ max Unit VDD VDD, AVDD, XVDD, LVDD, RVDD VIH1 TEST1 to TEST5, TAI, HFL, TES, P0/DFCK, P1/DFIN, P2, P3/DFLR, P4, P5, SBCK, RWC, COIN, CQCK, RES, CS, XIN, DEFI VIH2 EFMI VIL1 TEST1 to TEST5, TAI, HFL, TES, P0/DFCK, P1/DFIN, P2, P3/DFLR, P4, P5, SBCK, RWC, COIN, CQCK, RES, CS, XIN, DEFI VIL2 EFMI tSU COIN, RWC: Figures 1 and 4 400 ns tPRS RWC: Figure 4 100 ns tHD COIN, RWC: Figures 1 and 4 400 ns 4.5 5.0 5.5 V 0.7 VDD VDD V 0.6 VDD VDD V 0 0.3 VDD V 0 0.4 VDD V Continued on next page. No. 5826-3/9 LC78632RE Continued from preceding page. Parameter Symbol Conditions min High-level clock pulse width tWH SBCK, CQCK: Figures 1, 2, 3, and 4 400 Low-level clock pulse width tWL SBCK, CQCK: Figures 1, 2, 3, and 4 400 Data read access time tRAC SQOUT, PW: Figures 2, 3, and 4 Command transfer time tRWC RWC: Figures 1 and 4 Subcode Q read enable time tSQE typ ns 0 400 1000 ns ns WRQ: Figure 2, with no RWC signal 11.2 tSC SFSY: Figure 3 136 Subcode read enable tSE SFSY: Figure 3 Input level Unit ns Subcode read cycle Port output delay time max ms µs 400 ns tPD CONT1, CONT2, P0 to P5: Figure 5 VEI EFMI 1.0 Vp-p VXI XIN: Capacitance coupled input 1.0 Vp-p 1200 ns Note: Due to the structure of this IC, the identical voltage must be applied to all power-supply pins. Electrical Characteristics at Ta = 25°C, VDD = 5 V, VSS = 0 V Parameter Current drain Input high-level current Input low-level current Output high-level voltage Output low-level voltage Symbol Sled output voltage min typ max Unit Normal-speed playback IIH1 EFMI, HFL, TES, SBCK, RWC, COIN, CQCK, RES, DEFI: VIN = 5 V IIH2 TAI, TEST1 to TEST5, CS: VIN = 5 V 25 TAI, EFMI, HFL, TES, SBCK, RWC, COIN, CQCK, RES, TEST1 to TEST5, CS, DEFI: VIN = 0 V –5 µA IIL 30 mA 5 µA 75 µA VOH1 EFMO, CLV+, CLV–, V/P, PCK, FSEQ, TOFF, TGL, THLD, JP+, JP–, EMPH, EFLG, FSX IOH = –1 mA 4 V VOH2 MUTEL, MUTER, LRCKO, DFLRO, DACKO, P0/DFCK, P1/DFIN, P2, P3/DFLR, P4, P5, LRSY, CK2, ROMXA, C2F, SBSY, PW, SFSY, WRQ, SQOUT, 16M, 4.2M, CONT1, CONT2: IOH = –0.5 mA 4 V VOH3 VPDO: IOH = –1 mA 4.5 V VOH4 DOUT: IOH = –12 mA 4.5 V VOH5 LCHP, RCHP, LCHN, RCHN: IOH = –1 mA 3.0 VOL1 EFMO, CLV+, CLV–, V/P, PCK, FSEQ, TOFF, TGL, THLD, JP+, JP–, EMPH, EFLG, FSX IOL = 1 mA VOL2 MUTEL, MUTER, LRCKO, DFLRO, DACKO, P0/DFCK, P1/DFIN, P2, P3/DFLR, P4, P5, LRSY, CK2, ROMXA, C2F, SBSY, PW, SFSY, WRQ, SQOUT, 16M, 4.2M, CONT1, CONT2: IOL = 2 mA 4.5 V 1 V 0.4 V VOL3 VPDO: IOL = 1 mA 0.5 V VOL4 DOUT: IOL = 12 mA 0.5 V VOL5 LCHP, RCHP, LCHN, RCHN: IOL = 1 mA 2.0 V IOFF1 PDO1, PDO2, VPDO, P0/DFCK, P1/DFIN, P2, P3/DFLR, P4, P5: VOUT = 5 V 5 µA IOFF2 PDO1, PDO2, VPDO, P0/DFCK, P1/DFIN, P2, P3/DFLR, P4, P5: VOUT = 0 V IPDOH PDO1, PDO2: RISET = 68 kΩ –96 –80 –64 µA IPDOL PDO1, PDO2: RISET = 68 kΩ 64 80 96 µA VSLD1 1.0 1.25 1.5 V VSLD2 2.25 2.5 2.75 V VSLD3 3.5 3.75 4.0 V VSLD4 4.75 Output off leakage current Charge pump output current Conditions IDD 0.5 –5 µA V No. 5826-4/9 LC78632RE D/A Converter Analog Characteristics at Ta = 25°C, VDD = 5 V, VSS = 0 V Parameter Total harmonic distortion Symbol THD + N Conditions min LCHP, LCHN, RCHP, RCHN; 1 kHz: 0 dB input, using a 20-kHz low-pass filter (AD725D built in) typ max Unit 0.006 % 90 dB Dynamic range DR LCHP, LCHN, RCHP, RCHN; 1 kHz: –60 dB input, using the 20-kHz low-pass filter (A filter (AD725D built in)) Signal-to-noise ratio S/N LCHP, LCHN, RCHP, RCHN; 1 kHz: 0 dB input, using the 20-kHz low-pass filter (A filter (AD725D built in)) 98 100 dB Crosstalk CT LCHP, LCHN, RCHP, RCHN; 1 kHz: 0 dB input, using a 20-kHz low-pass filter (AD725D built in) 96 98 dB Note: Measured in normal-speed playback mode in a Sanyo 1-bit D/A converter block reference circuit, with the digital attenuator set to EE (hexadecimal). Figure 1 Command Input Figure 2 Subcode Q Output Figure 3 Subcode Output No. 5826-5/9 LC78632RE Figure 4 General-Purpose Port Read Figure 5 General-Purpose Port Output No. 5826-6/9 LC78632RE LC78632RE One-Bit D/A Converter Output Block Reference Circuit No. 5826-7/9 LC78632RE Pin Functions Pin No. Symbol I/O 1 VPDO O Test output Function 2 PDO2 O Double-speed and quad-speed mode playback PLL charge pump output. Must be left open if unused. 3 PDO1 O Normal-speed mode playback PLL charge pump output 4 AVSS 5 FR 6 AVDD Analog system power supply 7 ISET PDO1 and PDO2 output current setting resistor connection Analog system ground. Must be connected to 0 V. Built-in VCO frequency range setting resistor connection 8 TAI I Test input. A pull-down resistor is built in. Must be connected to 0 V. 9 EFMO O EFM signal output 10 VSS 11 EFMI I EFM signal input 12 TEST1 I Test input. A pull-down resistor is built in. Must be connected to 0 V. 13 CLV+ O 14 CLV– O Spindle servo control output. CLV+ outputs a high level for acceleration, and CLV– outputs a high level for deceleration. 15 V/P O Rough servo/phase control automatic switching monitor output. A high-level output indicates rough servo, and a low-level output indicates phase control. Test input. A pull-down resistor is built in. Must be connected to 0 V. Digital system ground. Must be connected to 0 V. 16 TEST2 I 17 TEST3 I 18 P4 I/O 19 HFL I Track detection signal input. This is a Schmitt input. 20 TES I Tracking error signal input. This is a Schmitt input. 21 PCK O EFM data playback bit clock monitor. Outputs 4.3218 MHz when the phase is locked in normal-speed mode playback. 22 FSEQ O Synchronization signal detection output. Outputs a high level when the synchronization signal detected from the EFM signal matches the internally generated synchronization signal. Tracking off output Test input. A pull-down resistor is built in. Must be connected to 0 V. I/O port 23 TOFF O 24 TGL O Tracking gain switching output. Increase the gain when this pin outputs a low level. 25 THLD O Tracking hold output I Test input. A pull-down resistor is built in. Must be connected to 0 V. 26 TEST4 27 VDD 28 JP+ O Digital system power supply 29 JP– O 30 SLD+ O 31 SLD– O Track jump output. JP+ outputs a high level both for acceleration during outward direction jumps and for deceleration during inward direction jumps. JP– outputs a high level both for acceleration during inward direction jumps and for deceleration during outward direction jumps. Sled output. This pin can be set to 1 of 4 levels by commands sent from the system control microprocessor. 32 EMPH O De-emphasis monitor. A high level indicates that a disk requiring de-emphasis is being played. 33 P5 I/O I/O port 34 LRCKO O 35 DFLRO O 36 DACKO O 37 CONT1 O Output port 38 P0/DFCK I/O I/O port. DF bit clock input in antishock mode. 39 P1/DFIN I/O I/O port. DF data input in antishock mode. LR clock output Digital filter outputs LR data output. The digital filter can be turned off with the DFOFF command. Bit clock output 40 P2 I/O I/O port. Used as the de-emphasis filter on/off switching pin in antishock mode. The de-emphasis filter is turned on when this pin is high. I/O port output or digital filter LR clock input (when anti-shock mode) 41 P3/DFLR I/O 42 LRSY O 43 CK2 O LR clock output Bit clock output. The polarity can be inverted with the CK2CON command. ROMXA pins 45 C2F O Interpolated data output. Data that has not been interpolated can be output by issuing the ROMXA command. C2 flag output 46 MUTEL O Left channel mute output 47 LVDD 48 LCHP O One-bit D/A Left channel P output 49 LCHN O converter pins Left channel N output 44 ROMXA O Left channel power supply 50 LVSS Left channel ground. Must be connected to 0V. Note: Of the general-purpose I/O ports, any unused input ports must be connected to 0 V, or set to be output ports. Continued on next page. No. 5826-8/9 LC78632RE Continued from preceding page. Pin No. Symbol 51 XVSS I/O 52 XOUT O 53 XIN I Function Crystal oscillator ground. Must be connected to 0 V. 16.9344 MHz crystal oscillator connections. Use a 33.8688 MHz crystal oscillator for quad-speed playback. 54 XVDD 55 RVSS 56 RCHN O 57 RCHP O 58 RVDD 59 MUTER O 60 SBSY O Subcode block synchronization signal output 61 EFLG O C1 and C2 error correction state monitor 62 PW O Subcode P, Q, R, S, T, U, V, and W output 63 SFSY O Subcode frame synchronization signal output. Falls when the subcode output goes to the standby state. 64 SBCK I Subcode readout clock input. This is a Schmitt input. This pin must be connected to 0 V if unused. 65 DOUT O Digital output 66 FSX O Outputs a 7.35 kHz synchronization signal generated by dividing the crystal oscillator frequency. 67 WRQ O Subcode Q output standby output 68 RWC I Read/write control input 69 SQOUT O Subcode Q output 70 COIN I Input for commands from the control microprocessor 71 CQCK I Command input acquisition clock. Also used as the SQOUT subcode readout clock input. This is a Schmitt input. 72 RES I Chip reset input. This pin must be set low temporarily when power is first applied. 73 TESTF O Test output 74 CONT2 O Output port 75 16M O 16.9344 MHz output 76 4.2M O 4.2336 MHz output 77 TEST5 I Test input. A pull-down resistor is built in. Must be connected to 0 V. 78 CS I Chip select input. A pull-down resistor is built in. When control is not used, this pin must be connected to 0 V. 79 DEFI I Defect detection signal input. Must be connected to 0 V if unused. Crystal oscillator power supply Right channel ground. Must be connected to 0 V. Right channel N output One-bit D/A converter pins Right channel P output Right channel power supply Right channel mute output 80 VCOC I Test input. Must be connected to 0 V. Note: Of the general-purpose I/O ports, any unused input ports must be connected to 0 V, or set to be output ports. ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provide information as of December, 1997. Specifications and information herein are subject to change without notice. No. 5826-9/9