HIGH SPEED SYNCHRONOUS POWER MOSFET DRIVER PRELIMINARY - December 7, 1999 SC1205 TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com DESCRIPTION FEATURES The SC1205 is a cost effective Dual MOSFET Driver designed for switching High and Low side Power MOSFETs. Each driver is capable of driving a 3000pF load in 20ns rise/fall time and has a 20ns max propagation delay from input transition to the gate of the power FET’s. An internal Overlap Protection Circuit prevents shoot-through from Vin to GND in the main switching and synchronous MOSFET’s. The Overlap Protection circuit ensures the Bottom FET does not turn on until the Top FET source has reached a voltage low enough to prevent cross-conduction. • The high current drive capability (2A peak) allows fast switching, thus reducing switching losses at high (1MHz) PWM frequencies. The high voltage CMOS process allows operation from 5-25 Volts at top MOSFET drain, thus making SC1205 suitable for battery powered applications. Connecting Enable pin (EN) to logic low shuts down both drives and reduces operating current to less than 10uA. An Under-Voltage-Lock-Out circuit is included to guarantee that both driver outputs are low when the 5V logic level is less than or equal to 4.4V (typ) at supply ramp up (4.35V at supply ramp down). An Internal temperature sensor shuts down all drives in the event of overtemperature. SC1205 is fabricated utilizing CMOS technology for low quiescent current. The SC1205 is offered in a standard SO-8 package. • • • • • • • • Fast rise and fall times (15ns typical with 3000pf load) 2Amp peak drive current 14ns max Propagation delay (BG going low) Adaptive Non-overlapping Gate Drives provide shoot-through protection Floating top drive switches up to 25V Under-Voltage lock-out Overtemperature protection Less than 10uA supply current when EN is low Low cost APPLICATIONS • • • • • High Density sunchronous power supplies Motor Drives/Class-D amps/Half bridge drivers High frequency (to 1.2 MHz) operation allows use of small inductors and low cost caps in place of electrolytics Portable computers Battery powered applications ORDERING INFORMATION (1) DEVICE SC1205CS PACKAGE TEMP. RANGE (T J) SO-8 0 - 125°C Note: (1) Add suffix ‘TR’ for tape and reel. PIN CONFIGURATION BLOCK DIAGRAM Top View (SO-8) 1 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET DRIVER SC1205 PRELIMINARY - December 7, 1999 ABSOLUTE MAXIMUM RATINGS Parameter Symbol VCC Supply Voltage BST to PGND BST to DRN DRN to PGND OVP_S to PGND Input pin Continuous Power Dissipation Conditions Maximum Units Tamb = 25°C, TJ = 125°C Tcase = 25°C, TJ = 125°C 7 30 7 25 10 -0.3 to 7.3 0.66 2.56 V V V V V V W θϑΧ 40 °C/W θJA 150 °C/W TJ 0 to +125 °C TSTG -65 to +150 °C TLEAD 300 °C VMAX5V VMAXBST-PGND VMAXBST-DRN VMAXDRN-PGN VMAXOVP_S-PGND CO Pd Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 sec NOTE: (1) Specification refers to application circuit in Figure 1. ELECTRICAL CHARACTERISTICS (DC OPERATING SPECIFICATIONS) Unless specified: -0 < θJ < 125°C; VCC = 5V; 4V < VBST < 26V PARAMETER SYMBOL CONDITIONS MIN TYP MAX VCC VCC 4.15 5 6.0 Quiescent Current, operating Iq_op VCC = 5V, CO = 0V Quiescent Current Iq_stby UNITS POWER SUPPLY Supply Voltage 1 EN = 0V V ma 10 µA 4.6 V UNDER-VOLTAGE LOCKOUT Start Threshold Hysteresis Logic Active Threshold VSTART VhysUVLO VACT 4.2 4.4 0.05 V 1.5 V 2 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET DRIVER SC1205 PRELIMINARY - December 7, 1999 ELECTRICAL CHARACTERISTICS (DC OPERATING SPECIFICATIONS) Cont. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CO High Level Input Voltage VIH Low Level Input Voltage VIL 2.0 V 0.8 V THERMAL SHUTDOWN Over Temperature Trip Point TOTP 165 °C Hysteresis THYST 10 °C IPKH 2 A 1 Ω HIGH-SIDE DRIVER Peak Output Current Output Resistance RsrcTG RsinkTG duty cycle < 2%, tpw < 100µs, TJ = 125°C, VBST - VDRN = 4.5V, VTG = 4.0V (src)+VDRN or VTG = 0.5V (sink)+VDRN .7 Ω LOW-SIDE DRIVER Peak Output Current Output Resistance IPKL RsrcBG RsinkBG duty cycle < 2%, tpw < 100µs, TJ = 125°C VV_5 = 4.6V, VBG = 4V (src), or VLOWDR = 0.5V (sink) 2 A 1.2 Ω 1.0 Ω 3 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET DRIVER SC1205 PRELIMINARY - December 7, 1999 AC OPERATING SPECIFICATIONS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS rise time trTG, CI = 3nF, VBST - VDRN = 4.6V, T J = 125°C 14 23 ns fall time tf TG CI = 3nF, VBST - VDRN = 4.6V, T J = 125°C 12 19 ns propagation delay time, TG going high tpdhTG CI = 3nF, VBST - VDRN = 4.6V, T J = 125°C 20 32 ns propagation delay time, TG going low tpdlTG CI = 3nF, VBST - VDRN = 4.6V, T J = 125°C 15 24 ns rise time trBG CI = 3nF, VV_5 = 4.6V, T J = 125°C 15 24 ns fall time trBG CI = 3nF, VV_5 = 4.6V, T J = 125°C 13 21 ns propagation delay time BG going high tpdhBGHI CI = 3nF, VV_5 = 4.6V, T J = 125°C, DRN < 1V 12 19 ns progagation delay time BG going low tpdlBG CI = 3nF, VV_5 = 4.6V, T J = 125°C 7 12 ns V_5 ramping up tpdhUVLO EN is High 10 us V_5 ramping down tpdlUVLO EN is High 10 us HIGH-SIDE DRIVER LOW-SIDE DRIVER UNDER-VOLTAGE LOCKOUT 4 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET DRIVER SC1205 PRELIMINARY - December 7, 1999 PIN DESCRIPTION Pin # Pin Name Pin Function 1 DRN This pin connects to the junction of the switching and synchronous MOSFET’s. This pin can be subjected to a -2V minimum relative to PGND without affecting operation. 2 TG Output gate drive for the switching (high-side) MOSFET. 3 BST Bootstrap pin. A capacitor is connected between BST and DRN pins to develop the floating bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1µF and 1µF (ceramic). 4 CO TTL-level input signal to the MOSFET drivers. 5 EN When high, this pin enables the internal circuitry of the device. When low, TG, BG and PRDY are forced low and the supply current (5V) is less than 10µA. 6 VS +5V supply. A .22-1µF ceramic capacitor should be connected from 5V to PGND very close to this pin. 7 BG Output drive for the synchronous MOSFET. 8 PGND Ground. NOTE: (1) All logic level inputs and outputs are open collector TTL compatible. TIMING DIAGRAM 5 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET DRIVER SC1205 PRELIMINARY - December 7, 1999 Figure 1 - Timing characteristics while driving a 3nf load at Tamb = 125°C after CO low to high transition. Ch1. CO input going high (start of cycle) Ch2. BG drive Ch3. TG drive Cload = 3 nf C_delay = 0 Ch1. DRN (phase node) voltage going low Ch2. BG going high Cload = 3 nf C_delay = 0 Figure 2-Timing characteristics while driving a 3nf load at Tamb = 125°C after DRN voltage transition to a low voltage (DRN <1V) 6 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 7 B121 A121 VCC_L2 VID[4] 9 10 11 12 13 14 15 16 INPUT +5V 8 7 6 5 4 3 2 1 Vout/Clk switch S1 1u,16V 1u,16V 1u,16V C8 1000uf,16V .01 C26 3.9k R6 EN C11 .1 C9 100 R7 C12 .1 C27 10k 35k R10 10 9 8 7 6 5 4 3 2 vcc5v 1 R38 10 R1 OC- OC+ Vid4 Vid3 Vid2 Vid1 Vid0 Rref NC U1 Comp FB Bgout FBG Enable GND Drv0 Drv1 Outv Vcc12v SC1142CSW 35k R10 Vcc5v C23 .022 11 12 13 14 C25 R8 .022 6k VOUT 10 R43 10 R44 300k R11 15 EN 16 17 18 19 20 VIN SC1205 CO EN VS EN 4 5 6 U12 3 BG TG 7 1 2 7 1 2 0 R13 * 51 * OPTIONAL R12 * FDB7030 Q4 IR7811 Q3 FDB7030 51 4.7 R45 0 R41 VIN 0 R40 Q1 IR7811 4.7 R45 Q2 VIN 0 R39 R42 C31 C4 22u,10V 1u,10V BG DRN BST TG DRN SC1205 CO EN VS D11 4 5 6 5819 D10 GND C16 22u,10V .1 5819 C57 U11 1u,10V C28 R9 10 C55 .1 C15 1u,10V 8 Long PCB Trace 3 BST 1000uf C10 GND C5 C6 C7 100UF 10uf 8 +12V R14 * 51 VOUT R15 * 51 D2 SS12 .6uh L2 .1 C58 D1 SS12 .6uh L1 C56 .1 22u,10V C36 22u,10V C32 22u,10V C29 22u,10V C24 22u,10V C22 22u,10V C21 22u,10V C20 22u,10V C19 22u,10V C18 22u,10V C14 22u,10V C13 1500uf C17 1500uf C30 Date: B Size Title Tuesday, June 29, 1999 SC1142EVB-A SC1142-1205 Evaluation Board PentiumII Document Number A120 A119 A118 A117 A116 A115 A114 A113 A112 A111 A110 A109 A108 A107 A106 A105 A104 A103 A102 A101 A100 A99 A98 A97 A96 A95 A94 A93 A92 A91 A90 A89 A88 A87 A86 A85 A84 A83 A82 A81 A80 A79 A78 A77 A76 A75 A74 A73 A72 A71 A70 A69 A68 A67 A66 A65 A64 A63 A62 A61 A60 A59 A58 A57 A56 A55 A54 A53 A52 A51 A50 A49 A48 A47 A46 A45 A44 A43 A42 A41 A40 A39 A38 A37 A36 A35 A34 A33 A32 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 VID[1] VID[2] GND $PIN116 $PIN115 $PIN114 GND $PIN112 $PIN111 $PIN110 GND $PIN108 $PIN107 $PIN106 GND $PIN104 $PIN103 $PIN102 GND $PIN100 $PIN99 $PIN98 GND $PIN96 $PIN95 $PIN94 GND $PIN92 $PIN91 $PIN90 GND $PIN88 $PIN87 $PIN86 GND $PIN84 $PIN83 $PIN82 GND $PIN80 $PIN79 $PIN78 GND $PIN76 $PIN75 $PIN74 GND $PIN72 $PIN71 $PIN70 GND $PIN68 $PIN67 $PIN66 GND $PIN64 $PIN63 $PIN62 GND $PIN60 $PIN59 $PIN58 GND $PIN56 $PIN55 $PIN54 GND $PIN52 $PIN51 $PIN50 GND $PIN48 $PIN47 $PIN46 GND $PIN44 $PIN43 $PIN42 GND $PIN40 $PIN39 $PIN38 GND $PIN36 $PIN35 $PIN34 GND $PIN32 $PIN31 $PIN30 GND $PIN28 $PIN27 $PIN26 GND $PIN24 $PIN23 $PIN22 GND $PIN20 $PIN19 $PIN18 GND $PIN16 Reserved THERMTRIP# GND TESTHI PWRGOOD TDO GND TDI IGNNE# FERR# GND A20M# IERR# VCC_VTT GND VCC_VTT J1 VID[0] VID[3] $PIN238 VCC_L2 $PIN236 $PIN235 $PIN234 VCC_L2 $PIN232 $PIN231 $PIN230 VCC5 $PIN228 $PIN227 $PIN226 VCC_CORE $PIN224 $PIN223 $PIN222 $PIN221 $PIN220 $PIN219 $PIN218 VCC_CORE $PIN216 $PIN215 $PIN214 VCC_CORE $PIN212 $PIN211 $PIN210 VCC_CORE $PIN208 $PIN207 $PIN206 VCC_CORE $PIN204 $PIN203 $PIN202 $PIN201 $PIN200 $PIN199 $PIN198 VCC_CORE $PIN196 $PIN195 $PIN194 VCC_CORE $PIN192 $PIN191 $PIN190 VCC_CORE $PIN188 $PIN187 $PIN186 VCC_CORE $PIN184 $PIN183 $PIN182 $PIN181 $PIN180 $PIN179 $PIN178 VCC_CORE $PIN176 $PIN175 $PIN174 VCC_CORE $PIN172 $PIN171 $PIN170 VCC_CORE $PIN168 $PIN167 $PIN166 VCC_CORE $PIN164 $PIN163 $PIN162 $PIN161 $PIN160 $PIN159 $PIN158 VCC_CORE $PIN156 $PIN155 $PIN154 VCC_CORE $PIN152 $PIN151 $PIN150 VCC_CORE $PIN148 $PIN147 $PIN146 VCC_CORE $PIN144 $PIN143 $PIN142 $PIN141 $PIN140 $PIN139 $PIN138 VCC_CORE $PIN136 $PIN135 $PIN134 VCC_CORE $PIN132 $PIN131 $PIN130 VCC_VTT $PIN128 $PIN127 $PIN126 VCC_VTT $PIN124 $PIN123 $PIN122 $PIN121 +5V B120 B119 B118 B117 B116 B115 B114 B113 B112 B111 B110 B109 B108 B107 B106 B105 B104 B103 B102 B101 B100 B99 B98 B97 B96 B95 B94 B93 B92 B91 B90 B89 B88 B87 B86 B85 B84 B83 B82 B81 B80 B79 B78 B77 B76 B75 B74 B73 B72 B71 B70 B69 B68 B67 B66 B65 B64 B63 B62 B61 B60 B59 B58 B57 B56 B55 B54 B53 B52 B51 B50 B49 B48 B47 B46 B45 B44 B43 B42 B41 B40 B39 B38 B37 B36 B35 B34 B33 B32 B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 Sheet 1 of 1 Figure 3-SC1205 Evaluation Board Rev N/C PRELIMINARY - December 7, 1999 HIGH SPEED SYNCHRONOUS POWER MOSFET DRIVER SC1205 HIGH SPEED SYNCHRONOUS POWER MOSFET DRIVER SC1205 PRELIMINARY - December 7, 1999 BILL OF MATERIAL Item Qty Reference Value Manufacturer 1 3 C4,C15,C28 1u,10V, Cer. AVX, Murata 2 3 C5,C6,C7 1u,16V, Cer. AVX, Murata 3 1 C8 1000uF, 16V Nichicon, any 4 1 C9 100uF Nichicon, any 5 1 C10 1000uf Nichicon, any 7 1 C12 10uF Nichicon, any 8 13 C13,C14,C16,C18,C19,C20,C21,C22,C24,C29,C31,C32, C36 9 2 C17,C30 1500uf 10 2 C23,C25 .022 Avx, any 11 1 C26 .01 Avx, any 12 6 C11,C27,C55,C56,C57,C58 .1 Avx, any 14 2 D1,D2 SS12 General Instruments, any 15 2 D10,D11 5819 General Instruments, any 16 1 J1 Input 17 2 L1,L2 .6uh 18 2 Q1,Q3 IR7811 Int. Rectifier (310) 252-7099 19 2 Q2,Q4 FDB7030 Fairchild Semi. (408) 822-2000 20 4 R1,R9,R43,R44 21 1 22 22u, 10V Murata (GRM235Y5V226Z010) Nichicon, Sanyo 13 Falco, P/N: TO2508 or SDIP0804-608M (305) 662-9076 10 any R6 3.9k any 1 R7 100 any 23 1 R8 6k any 24 1 R10 35k any 25 1 R11 300k any 26 4 R12,R13,R14,R15 27 1 R38 28 4 R39,R40,R41,R42 29 1 R45 30 1 S1 Vout/Clk switch 31 1 U2 Pentium II™ Slot 1 Connector 32 1 U1 SC1142CSW Semtech, (805) 499-2111 33 2 U11,U12 SC1205S Semtech, (805) 499-2111 51 any, Required in asynch. operation 10K any 0 any 4.7 any Digikey 8 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET DRIVER SC1205 PRELIMINARY - December 7, 1999 APPLICATION INFORMATION: SC1205 is a high speed, smart dual MOSFET driver. It is designed to drive Low Rds_On power MOSFET’s with ultra-low rise/fall times and propagation delays. As the switching frequencies of PWM controllers is increased to reduce power supply and Class-D amplifier volume and cost, fast rise and fall times are necessary to minimize switching losses (TOP MOSFET) and reduce Dead-time (BOTTOM MOSFET). While 2 Low Rds_On MOSFET’s present a power saving in I R losses, the MOSFET’s die area is larger and thus the effective input capacitance of the MOSFET is increased. Often a 50% decrease in Rds_On more than doubles the effective input gate charge, which must be supplied by the driver. The Rds_On power savings can be offset by the switching and dead-time losses with a sub-optimum driver. While discrete solution can achieve reasonable drive capability, implementing shoot-through, programmable delay and other housekeeping functions necessary for safe operation can become cumbersome and costly. The SC120X family of parts presents a total solution for the high-speed, high power density applications. Wide input supply range of 4.5V-25V allows use in battery powered applications, new high voltage, distributed power servers as well as Class-D amplifiers. THEORY OF OPERATION The control input (CO) to the SC1205 is typically supplied by a PWM controller that regulates the power supply output. (See Application Evaluation Schematic, Figure 3). The timing diagram demonstrates the sequence of events by which the top and bottom drive signals are applied. The shoot-through protection is implemented by holding the bottom FET off until the voltage at the phase node (intersection of top FET source, the output inductor and the bottom FET drain) has dropped below 1V. This assures that the top FET has turned off and that a direct current path does not exist between the input supply and ground, a condition which both the top and bottom FET’s are on momentarily. The top FET is also prevented from turning on until the bottom FET is off. This time is internally set to 20ns. to figure 3) shows a two-phase synchronous design with all surface mountable components. While components connecting to EN are relatively non-critical, tight placement and short,wide traces must be used in layout of The Drives, DRN, and especially PGND pin. The top gate driver supply voltage is provided by bootstrapping the +5V supply and adding it the phase node voltage (DRN). Since the bootstrap capacitor supplies the charge to the top gate, it must be less than .5” away from the SC1205. Ceramic X7R capacitors are a good choice for supply bypassing near the chip. The Vcc pin capacitor must also be less than .5” away from the SC1205. The ground node of this capacitor, the SC1205 PGND pin and the Source of the bottom FET must be very close to each other, preferably with common PCB copper land with multiple vias to the ground plane (if used). The parallel Shottkey must be physically next to the Bottom FETS Drain and source. Any trace or lead inductance in these connections will drive current way from the Shottkey and allow it to flow through the FET’s Body diode, thus reducing efficiency. PREVENTING INADVERTENT BOTTOM FET TURN-ON At high input voltages, (12V and greater) a fast turn-on of the top FET creates a positive going spike on the Bottom FET’s gate through the Miller capacitance, crss of the bottom FET. The voltage appearing on the gate due to this spike is: Vspike=Vin*crss/(Crass+ciss) Where Ciss is the input gate capacitance of the bottom FET. This is assuming that the impedance of the drive path is too high compared to the instantaneous impedance of the capacitors. (since dV/dT and thus the effective frequency is very high). If the BG pin of the SC1205 is very close to the bottom FET, Vspike will be reduced depending on trace inductance, rate of rise of current,etc. LAYOUT GUIDELINES As with any high speed , high current circuit, proper layout is critical in achieving optimum performance of the SC1205. The Evaluation board schematic (Refer 9 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET DRIVER SC1205 PRELIMINARY - December 7, 1999 While not shown in Figure 3, a capacitor may be added from the gate of the Bottom FET to its source, preferably less than .1” away. This capacitor will be added to Ciss in the above equation to reduce the effective spike voltage, Vspike. The selection of the bottom MOSFET must be done with attention paid to the Crss/Ciss ratio. A low ratio reduces the Miller feedback and thus reduces Vspike. Also MOSFETs with higher Turn-on threshold voltages will conduct at a higher voltage and will not turn on during the spike. The MOSFET shown in the schematic (figure 3) has a 2 volt threshold and will require approximately 4.5 volts Vgs to be conducting, thus reducing the possibility of shoot-through. A zero ohm bottom FET gate resistor will obviously help keeping the gate voltage low. Ultimately, slowing down the top FET by adding gate resistance will reduce di/dt which will in turn make the effective impedance of the capacitors higher, thus allowing the BG driver to hold the bottom gate voltage low. It does this at the expense of increased switching times ( and switching losses) for the top FET. can often eliminate the EMI issue. If double pulsing is caused due to excessive ringing, placing 4.7-10 ohm resistor between the phase node and the DRN pin of the SC1205 should eliminate the double pulsing. Proper layout will guarantee minimum ringing and eliminate the need for external components. Use of SO-8 or other surface mount MOSFETs while increasing thermal resistance, will reduce lead inductance as well as radiated EMI. OVER TEMP SHUTDOWN The SC1205 will shutdown by pulling both driver if its junction temperature, Tj, exceeds 165 °C. RINGING ON THE PHASE NODE The top MOSFET source must be close to the bottom MOSFET drain to prevent ringing and the possibility of the phase node going negative. This frequency is determined by: Fring =1/(2¶* Sqrt(Lst*Coss)) Where: Lst = The effective stray inductance of the top FET added to trace inductance of the connection between top FET’s source and the bottom FET’s drain added to the trace resistance of the bottom FET’s ground connection. Coss=Drain to source capacitance of bottom FET. If there is a Shottkey used, the capacitance of the Shottkey is added to the value. Although this ringing does not pose any power losses due to a fairly high Q, it could cause the phase node to go too far negative, thus causing improper operation, double pulsing or at worst driver damage. On the SC1205, the drain node, DRN, can go as far as 2V below ground without affecting operation or sustaining damage. The ringing is also an EMI nuisance due to its high resonant frequency. Adding a capacitor, typically 1000-2000pf, in parallel with Coss of the bottom FET 10 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET DRIVER SC1205 PRELIMINARY - December 7, 1999 Figure 4-Timing diagram: Ch1:CO input Ch2:TG drive Ch3:BG non-overlap drive Ch4:phase node Iout=20A (10A/phase) Refer to Eval. Schematic (fig.3) Figure 5-Timing diagram: Rise/Fall times Ch1:TG drive Ch2:BG drive Cursor:TpdhTG Iout=20A (10A/phase) Refer to Eval. Schematic (fig.3) 11 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET DRIVER SC1205 PRELIMINARY - December 7, 1999 OUTLINE DRAWING - SO-8 JEDEC REF: MS-012AA LAND PATTERN - SO-8 ECN99-742 12 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320