SEMTECH SK100E111

SK10/100E111
1:9 Differential
Clock Driver
HIGH-PERFORMANCE PRODUCTS
PRODUCTS
HIGH-PERFORMANCE
Description
Features
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The SK10E/100E111 is a low skew 1-to-9 differential
driver designed with clock distribution in mind. It accepts
one signal input which can be either differential or singleended if the VBB output is used. The signal is fanned
out to 9 identical differential outputs. An enable input
is also provided. A HIGH disables the device by forcing
all Q outputs LOW and all Q* outputs HIGH.
The device is specifically designed, modeled, and
produced with low skew as the key goal. Optimal design
and layout serve to minimize gate-to-gate skew withindevice, and characterization is used to determine process
control limits that ensure consistent tpd distributions
from lot to lot. The net result is a dependable, guaranteed
low skew device.
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PRELIMINARY
Low Skew
Guaranteed Skew Spec
Differential Design
VBB Output
Enable Input
Extended 100E VEE Range of –4.2 to –5.5V
75KΩ Internal Input Pulldown Resistors
Fully Compatible with MC10E111 and
MC100E111
Specified Over Industrial Temperature Range:
–40 oC to 85oC
ESD Protection of >4000V
Available in 28-pin PLCC Package
Functional Block Diagram
To ensure that the tight skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50Ω , even if only one side is being used.
In most applications, all nine differential pairs will be
used and therefore terminated. In the case where fewer
than nine pairs are used, it is necessary to terminate at
least the output pairs on the same package side (i.e.
sharing the same VCCO) as the pair(s) being used on
that side in order to maintain minimum skew. Failure to
do this will result in small degradations of propagation
delay (on the order of 10–20ps) of the output(s) being
used which, while not being catastrophic to most designs,
will mean a loss of skew margin.
Q0
Q0*
Q1
Q1*
Q2
Q2*
Q3
Q3*
Q4
Q4*
IN
IN*
Q5
Q5*
EN*
Q6
Q6*
Q7
Q7*
VBB
Revision 1 /February 13, 2001
1
Q8
Q8*
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SK10/100E111
HIGH-PERFORMANCE PRODUCTS
PIN Description
Q0
Q0*
Q1
VCC0
Q1*
Q2
Q2*
Pinout
25
24
23
22
21
20
19
VEE
26
18
Q3
EN*
27
17
Q3*
IN
28
16
Q4
15
VCC0
28 Lead PLCC
VCC
1
(Top View)
VBB
3
13
Q5
N/C
4
12
Q5*
7
Q7*
6
Q8
Q8*
5
8
9
10
11
Q6
Q4*
Q6*
14
Q7
2
VCC0
IN*
Pin Names
Pin
Function
IN, IN*
EN*
Q0, Q0* - Q8, Q8*
VBB
Differential Input Pair
Enable
Differential Outputs
VBB Output
Revision 1 /February 13, 2001
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SK10/100E111
HIGH-PERFORMANCE PRODUCTS
Package Information
NOTES:
1. Datums –L–, –M–, and –N– determined where top of
lead shoulder exits plastic body at mold parting line.
2. DIM G1, true position to be measured at Datum –T–,
Seating Plane.
3. DIM R and U do not include mold flash. Allowable
mold flash is 0.010 (0.250) per side.
4. Dimensioning and tolerancing per ANSI Y14.5M,
1982.
5. Controlling Dimension: Inch.
6. The package top may be smaller than the package
bottom by up to 0.012 (0.300). Dimensions R and U
are determined at the outermost extremes of the
plastic body exclusive of mold flash, tie bar burrs, gate
burrs and interlead flash, but including any mismatch
betweeen the top and bottom of the plastic body.
7. Dimension H does not include Dambar protrusion or
intrusion. The Dambar protrusion(s) shall not cause
the H dimension to be greater than 0.037 (0.940).
The Dambar intrusion(s) shall not cause the H
dimension smaller than 0.025 (0.635).
Y BRK
–N–
D
PIN Descriptions
–L–
–M–
D
W
V
28
1
Z
C
A
0.007 (0.180) M T L – M
S
NS
R
0.007 (0.180)
S
NS
M
T L–M
+
+
E
0.004 (0.100)
–T– SEATING PLANE
G
J
G1
VIEW S
0.010 (0.250) S T L – M S N S
B
0.007 (0.180)
M
T
L - M
S
N
S
INCHES
U
0.007 (0.180)
T
M
L - M
S
N
Z
+
0.010 (0.250) S
G1
X
T L - M
S
N
S
DIM
MIN
MAX
MIN
MAX
A
0.485
0.495
12.32
12.57
B
0.485
0.495
12.32
12.57
C
0.165
0.180
4.20
4.57
E
0.090
0.110
2.29
2.79
F
0.013
0.019
0.33
0.48
G
H
0.007(0.180) M T L – M S N S
K1
K
F
MILLIMETERS
S
+
0.007 (0.180) M T L – M
S
N
0.050 BSC
1.27 BSC
H
0.026
0.032
0.66
0.81
J
0.020
--
0.51
--
K
0.025
--
0.64
--
R
0.450
0.456
11.43
11.58
U
0.450
0.456
11.43
11.58
V
0.042
0.048
1.07
1.21
W
0.042
0.048
1.07
1.21
X
0.042
0.056
1.07
1.42
Y
--
0.020
--
0.50
Z
2o
10o
2o
10o
G1
0.410
0.430
10.42
10.92
K1
0.040
--
1.02
--
S
VIEW S
Revision 1 /February 13, 2001
3
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SK10/100E111
HIGH-PERFORMANCE PRODUCTS
DC Characteristics
SK10/100E111 DC Electrical Characteristics (Notes 1, 2)
Ω to VCC – 2.0V)
(VCC – VEE = 4.2V to 5.5V; VOUT Loaded 50Ω
Symbol
V BB
Ch a r a c t e r i s t i c
Output Reference Voltage13
10EL
100EL
IIN
I n p u t Cu r r e n t ( Di f f )
( SE)
I EE
Power Supply Cur rent
TA = –40oC
TA = 0oC
Min
Max
Min
Max
Min
Max
Min
Max
Un i t
- 1. 43
- 1. 38
- 1. 30
- 1. 26
- 1. 38
- 1. 38
- 1. 27
- 1. 26
- 1. 35
- 1. 38
- 1. 25
- 1. 26
- 1. 31
- 1. 38
- 1. 19
- 1. 26
V
V
- 150
150
150
- 150
150
150
- 150
150
150
- 150
150
150
µA
µA
64
mA
64
TA = +25oC
64
TA = +85oC
64
AC Characteristics
SK10/100E111 AC Electrical Characteristics
Ω to VCC – 2.0V)
(VCC – VEE = 4.2V to 5.5V; VOUT Loaded 50Ω
TA = –40oC
Min
t PLH
t P HL
Propagation Delay to
Ou t p u t
I N ( Di f f ) 5
I N ( SE) 6
Enabl e7
Di s a b l e
475
280
400
400
ts
S e t u p T i me 9
EN t o I N
250
0
200
0
200
0
200
0
ps
tH
H o l d T i me 1 0
I N t o EN
50
- 200
0
- 200
0
- 200
0
- 200
ps
tR
R e l e a s e T i me 1 1
E N* t o I N
350
100
300
100
300
100
tskew
Within-Device Skew8
VPP(AC)
Mi n i mu m I n p u t
Swi n g 12
250
1000
250
1000
250
1000
V C MR
C o mmo n Mo d e
Range4
VEE
+
1. 6
VCC
– 0. 4
VEE
+
1. 6
VCC
– 0. 4
VEE
+
1. 6
tr , tf
Rise/Fall Time
20% t o 80%
215
545
225
570
230
450
Min
630
780
900
900
490
330
450
450
75
Typ
25
4
375
Max
Min
655
730
850
850
500
330
450
450
50
Typ
TA = +85oC
Ch a r a c t e r i s t i c
25
Max
TA = +25oC
Symbol
Revision 1 /February 13, 2001
Typ
TA = 0oC
25
375
Max
Min
660
730
850
850
520
330
450
450
Typ
Max
Un i t
655
730
850
850
ps
ps
ps
ps
300
100
ps
25
50
ps
250
1000
mV
VCC
– 0. 4
VEE
+
1. 6
VCC
– 0. 4
V
545
240
475
ps
50
375
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SK10/100E111
HIGH-PERFORMANCE PRODUCTS
AC Characteristics (continued)
IN
IN*
IN*
IN*
ts
tr
th
EN*
50%
EN*
IN
IN
≤75 mV
EN*
50%
Q*
Q*
Q*
Q
Q
Q
≤75 mV
Figure 1. Setup Time
50%
≤75 mV
≤75 mV
Figure 3. Release Time
Figure 2. Hold Time
Notes:
1. 10E circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has
been established. The circuit is in a test socket or mounted on a printed circuit board and transverse
airflow greater than 500 lfpm is maintained.
2. 100E circuits are designed to meet the DC specifications shown in the table where transverse airflow
greater than 500 lfpm is maintained.
3. Differential input voltage required to obtain a full ECL swing on the outputs.
4. VCMR range is referenced to the most positive side of the differential input signal. Normal operation is
obtained if the high level falls within the specified range and the peak-to-peak voltage lies between
VPP(min) and 1V. The lower end of VCMR range varies 1:1 with VEE and is equal to VEE+1.6V.
5. The differential propagation delay is defined as the delay from the crossing points of the differential
input signals to the crossing point of the differential output signals.
6. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to
the 50% point of the output signal.
7. Enable is defined as the propagation delay from the 50% point of a negative transition on EN* to the
50% point of a positive transition on Q (or a negative transition on Q). Disable is defined as the
propagation delay from the 50% point of a positive transition on EN* to the 50% point of a negative
transition on Q (or a positive transition on Q).
8. The within-device skew is defined as the worst case difference between any two similar delay paths
within a single device.
9. The setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to
prevent an output response greater than ±75 mV to that IN/IN transition (see Figure 1).
10. The hold time is the minimum time that EN must remain asserted after a negative going IN or a positive
going IN* to prevent an output response greater than ±75 mV to the IN/IN transition (see Figure 2).
11. The release time is the minimum time that EN must be deasserted prior to the next IN/IN* transition to
ensure an output response that meets the specified IN to Q propagation delay and output transition times
(see Figure 3).
12. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the
propagation delay. The VPP(min) is AC limited for the E111 as a differential input as low as 250 mV
will still produce full ECL levels at the output.
13. Voltages referenced to VCC = 0V.
14. For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specifications Data
Sheet.
15. For part ordering descriptions, see HPP Part Ordering Information Data Sheet.
Revision 1 /February 13, 2001
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SK10/100E111
HIGH-PERFORMANCE PRODUCTS
Ordering Information
Ordering Code
Package ID
Temperature Range
SK10E111PJ
28-PLCC
Industrial
SK10E111PJT
28-PLCC
Industrial
SK100E111PJ
28-PLCC
Industrial
SK100E111PJT
28-PLCC
Industrial
Contact Information
Division Headquarters
10021 Willow Creek Road
San Diego, CA 92131
Phone: (858) 695-1808
FAX:
(858) 695-2633
Revision 1 /February 13, 2001
Semtech Corporation
High-Performance Products Division
6
Marketing Group
1111 Comstock Street
Santa Clara, CA 95054
Phone: (408) 566-8776
FAX: (408) 727-8994
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