SK10/100E445 4-Bit Serial/Parallel Converter HIGH-PERFORMANCE PRODUCTS Description Features The SK10/100E445 is an integrated 4-bit serial-toparallel data converter. The device is designed to operate for NRZ data rates of up to 2.0 Gb/s. The chip generates a divide by 4 and a divide by 8 clock for both 4-bit conversion and a two chip 8-bit conversion function. The conversion sequence was chosen to convert the first serial bit to Q0, the second to Q1, etc. • • • • • • • • • • • Two selectable serial inputs provide a loopback capability for testing purposes when the device is used in conjunction with the R446 parallel to serial converter. The start bit for conversion can be moved using the SYNC input. A single pulse applied asynchronously for at least two input clock cycles shifts the start bit for conversion from Qn to Qn–1. For each additional shift required, an additional pulse must be applied to the SYNC input. Asserting the SYNC input will force the internal clock dividers to “swallow” a clock pulse, effectively shifting a bit from the Qn to the Qn–1 output (see Timing Diagram B). On-Chip Clock ÷ 4 and ÷8 2.0 Gb/s Data Rate Capability Differential Clock and Serial Inputs VBB Output for Single-Ended Input Applications Asynchronous Data Synchronization Mode Select to Expand to 8-Bits Internal 75 kΩ Input Pulldown Resistors ESD Protection of >4000V Extended 100E VEE Range of –4.2V to –5.46V Fully Compatible with MC10/100E445 Available in 28-Pin PLCC Package Functional Block Diagram SINB SINB* SINA SINA* D Q D Q Q3 D Q D Q Q2 D Q D Q Q1 D Q D Q SEL The MODE input is used to select the conversion mode of the device. With the MODE input LOW, or open, the device will function as a 4-bit converter. When the mode input is driven HIGH, the data on the output will change on every eighth clock cycle, thus allowing for an 8-bit conversion scheme using two E445’s. When cascaded in an 8-bit conversion scheme, the devices will not operate at the 2.0 Gb/s data rate of a single device. Refer to the applications section of this data sheet for more information on cascading the E445. Q0 SOUT SOUT* 0 1 For lower data rate applications, a VBB reference voltage is supplied for single-ended inputs. When operating at clock rates above 500 MHz, differential input signals are recommended. For single-ended inputs, the VBB pin is tied to the inverting differential input and bypassed via a 0.01 µF capacitor. The VBB provides the switching reference for the input differential amplifier. The VBB can also be used to AC couple an input signal. MODE Out ¸4 CLK CLK* R Out ¸2 Upon power-up, the internal flip-flops will attain a random state. To synchronize multiple E445’s in a system, the master reset must be asserted. CL/4* Latch EN SYNC Revision 1/February 21, 2001 In Out CL/4 CL/8 CL/8* R D Q D Q* RESET 1 www.semtech.com SK10/100E445 HIGH-PERFORMANCE PRODUCTS PIN Description Pinout SINA SINA* SYNC RESET MODE NC VCCO Pin Names 25 24 23 22 21 20 19 Pin SinA, SINA* Differential Serial Data Input A SINB, SINB* Differential Serial Data Input B SEL Serial Input Selector Pin Q0 - Q3 Parallel Data Outputs CLK, CLK* Differential Clock Inputs CL/4, CL/4* Differential 4Clock Output VCC0 CL/8, CL/8* Differential 8Clock Output Q2 MODE Conversion Mode 4-Bit/8Bit SYNCH Conversion Synchronizing Input SINB 26 18 SOUT SINB* 27 17 SOUT* SEL 28 16 VCC VEE 1 15 Q0 CLK 2 14 Q1 CLK* 3 13 VBB 4 12 28 Lead PLCC 8 9 10 11 CL/4* VCC0 Q3 7 VCC0 CL/8 CL/8* 6 CL/4 (Top View) 5 Function Function Table Revision 1/February 21, 2001 2 Mode Conversion SEL Serial Input L 4-Bit H A H 8-Bit L B www.semtech.com SK10/100E445 HIGH-PERFORMANCE PRODUCTS Application Information The SK10/100E445 is an integrated 4-bit serial-toparallel data converter. The chip is designed to work with the E446 device to provide both transmission and receiving of a high speed serial data path. The E445 can convert up to a 2.0 GB/s NRZ data stream into 4-bit parallel data. The device also provides a divide by four clock output to be used to synchronize the parallel data with the rest of the system. The E445 features multiplexed dual serial inputs to provide test loop capability when used in conjunction with the E446. Figure 1 illustrates the loop test architecture. The architecture allows for the electrical testing of the link without requiring actual transmission over the serial data path medium. The SINA serial input of the E446 has an extra buffer delay and should be used as the loopback serial input. The clock frequency is significantly lower than that of a single converter. To increase this frequency, some games can be played with the clock input of the higher order E445. By delaying the clock feeding the second E445 relative to the clock of the first E445, the frequency of operation can be increased. The delay between the two clocks can be increased until the minimum delay of clock to serial out would potentially cause a serial bit to be swallowed (Figure 3). CLOCK CLOCK* E445a SERIAL INPUT DATA SIN SIN* Q3 SOUT SOUT* Q2 Q1 Q0 Q7 Q6 Q5 Q4 PARALLEL DATA SOUT SOUT* TO SERIAL MEDIUM E445b SIN SIN* Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 PARALLEL OUTPUT DATA 100 ps PARALLEL DATA SINA SINA* CLOCK FROM SERIAL MEDIUM Tpd CLK to SOUT 800 ps 1150 ps Figure 1. Loopback Test Architecture Figure 2. Cascaded 1:8 Converter Architecture The E445 features a differential serial output and a divide by 8 clock output to facilitate the cascading of two devices to build a 1:8 demultiplexer. Figure 2 illustrates the architecture for a 1:8 demultiplexer using two E445’s; the timing diagram for this configuration can be found in Figure 6. Notice the serial outputs (SOUT of the lower order converter feed the serial inputs of the higher order device. This feedthrough of the serial inputs bounds the upper end of the frequency of operation. The clock to serial output propagation delay plus the setup time of the serial input pins must fit into a single clock period for the cascade architecture to function properly. Using the worst case values for these two parameters from the datasheet, TPD CLK to SOUT = 1150 ps and tS for SIN = –100 ps, yields a minimum period of 1050 ps or a clock frequency of 950 MHz. With a minimum delay of 800 ps on this output, the clock for the lower order E445 cannot be delayed more than 800 ps relative to the clock of the first E445 without potentially missing a bit of information. Because the setup time on the serial input pin is negative, coincident excursions on the data and clock inputs of the E445 will result in correct operation. CLOCK A CLOCK B Tpd CLK to SOUT 800 ps 1150 ps Figure 3. Cascade Frequency Limitation Revision 1/February 21, 2001 3 www.semtech.com SK10/100E445 HIGH-PERFORMANCE PRODUCTS Application Information (continued) Perhaps the easiest way to delay the second clock relative to the first is to take advantage of the differential clock inputs on the E445. By connecting the clock for the second E445 to the complimentary clock input pin, the device will clock a half a clock period after the first E445 (Figure 5). Utilizing this simple technique will raise the potential conversion frequency up to 1.4 GHz. The divide by eight clock of the second E445 should be used to synchronize the parallel data to the rest of the system as the parallel data of the two E445’s will no longer by synchronized. This skew problem between the outputs can be worked around as the parallel information will be static for eight more clock pulses. CLOCK CLOCK* 100 ps E445a E445b CLOCK A SERIAL INPUT DATA SIN SIN* SIN SIN* SOUT SOUT* Q3 Q2 Q1 Q0 Q7 Q6 Q5 CLOCK B Q3 Q4 Q3 Q2 Q2 Tpd CLK to SOUT Q1 Q0 Q1 800 ps 1150 ps Q0 PARALLEL OUTPUT DATA Figure 7. Extended Frequency 1:8 Demultiplexer CLK SIN Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 Q0 Dn–4 Q1 Dn–3 Q2 Dn–2 Q3 Dn–41 Q4 (Q0 a) Dn Q5 (Q1 a) Dn+1 Q6 (Q2 a) Dn+2 Q7 (Q3 a) Dn+3 SOUTa Dn-4 SOUTa Dn-3 Dn-2 Dn-1 Dn Dn-4 Dn+1 Dn+2 Dn+3 Dn-3 Dn-2 DnÐ1 Dn Dn+1 CL/4a CL/4b CL/8a CL/8b Figure 8. Timing Diagram A: 1:8 Serial to Parallel Conversion Revision 1/February 21, 2001 4 www.semtech.com SK10/100E445 HIGH-PERFORMANCE PRODUCTS Package Information Y BRK –N– B 0.007 (0.180) U M T 0.007 (0.180) D L - M M T S N L - M S N S S + Z PIN Descriptions –L– –M– + 0.010 (0.250) G1 X S T L - M S N S D W V 28 1 H Z C A 0.007 (0.180) M T L – M S NS R 0.007 (0.180) S NS M T L–M K1 VIEW S K + E + 0.007(0.180) M T L – M S N S G J 0.007 (0.180) M T L – M F 0.004 (0.100) –T– SEATING PLANE S N S G1 0.010 (0.250) S T L – M S N S VIEW S NOTES: 1. Datums -L-, -M-, and -N- determined where top of lead shoulder exits plastic body at mold parting line. 2. DIM G1, true position to be measured at Datum -T-, Seating Plane. 3. DIM R and U do not include mold flash. Allowable mold flash is 0.010 (0.250) per side. 4. Dimensioning and tolerancing per ANSI Y14.5M, 1982. 5. Controlling Dimension: Inch. 6. The package top may be smaller than the package bottom by up to 0.012 (0.300). Dimensions R and U are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. Dimension H does not include Dambar protrusion or intrusion. The Dambar protrusion(s) shall not cause the H dimension to be greater than 0.037 (0.940). The Dambar intrusion(s) shall not cause the H dimension to be smaller than 0.025 (0.635). Revision 1/February 21, 2001 5 INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.485 0.495 12.32 12.57 B 0.485 0.495 12.32 12.57 C 0.165 0.180 4.20 4.57 E 0.090 0.110 2.29 2.79 F 0.013 0.019 0.33 0.48 G 0.050 BSC H 0.026 0.032 1.27 BSC 0.66 0.81 -- J 0.020 -- 0.51 K 0.025 -- 0.64 -- R 0.450 0.456 11.43 11.58 U 0.450 0.456 11.43 11.58 V 0.042 0.048 1.07 1.21 W 0.042 0.048 1.07 1.21 X 0.042 0.056 1.07 1.42 Y -- 0.020 -- 0.50 Z 2o 10o 2o 10o G1 0.410 0.430 10.42 10.92 K1 0.040 -- 1.02 -- www.semtech.com SK10/100E445 HIGH-PERFORMANCE PRODUCTS DC Characteristics SK10E445 DC Electrical Characteristics (VEE = VEE(min) to VEE(max); VCC = VCCO = GND) TA = +25oC TA = 0oC Symbol Characteristic Min IIN Input Current (Diff) (SE) VOH Typ Max Min -150 150 150 Output High Current (SOUT Only) -1020 VBB Output Reference Voltage -1.38 IEE Power Supply Current Max Min -150 150 150 -790 -980 -1.27 -1.35 154 185 Typ TA = +85oC 154 Max Unit -150 150 150 µA µA -760 -910 -670 V -1.25 -1.31 -1.19 V 185 mA 185 Typ 154 Condition Note 1 SK100E445 DC Electrical Characteristics (VEE = VEE(min) to VEE(max); VCC = VCCO = GND) TA = 0oC Symbol Characteristic Min IIN Input Current (Diff) (SE) VOH Typ TA = +25oC Max Min -150 150 150 Output High Current (SOUT Only) -1025 VBB Output Reference Voltage -1.38 IEE Power Supply Current 154 Max Min -150 150 150 -830 -1025 -1.26 -1.38 185 Typ TA = +85oC 154 Max Unit -150 150 150 µA µA -830 -1025 -830 V -1.26 -1.38 -1.26 V 211 mA 185 Typ 177 Condition Note 1 Note 1: The maximum VOH limit was relaxed from standard ECL due to the high frequency output design. All other outputs are specified with the standard 10E and 100E VOH levels. Revision 1/February 21, 2001 6 www.semtech.com SK10/100E445 HIGH-PERFORMANCE PRODUCTS AC Characteristics SK10/100E445 AC Electrical Characteristics (VEE = VEE(min) to VEE(max); VCC = VCCO = GND) TA = 0oC Symbol Characteristic Min Typ fmax Maximum Conversion Frequency 2.0 tPLH tPHL Propagation Delay to Output CLK to Q CLK to SOUT CLK to CL/4 CLK to CL/8 1500 800 1100 1100 1800 975 1325 1325 ts Setup Time SINA, SINB SEL -100 0 th Hold Time SINA, SINB, SEL tRR TA = +25oC Max Min Typ TA = +85oC Max 2.0 2100 1150 1500 1500 1800 975 1325 1325 -250 -200 -100 0 450 300 Reset Recover y Time 500 300 tPW Minimum Pulse Width CLK, MR 400 tr, tf Rise/Fall Times SOUT CL/4. CL/8 Qn 130 200 370 2100 1150 1500 1500 Max Unit 1800 975 1325 1325 -250 -200 -100 0 -250 -200 ps ps 450 300 450 300 ps 500 300 500 300 ps 2100 1150 1500 1500 400 130 200 370 225 425 490 270 520 700 130 200 370 Condition GB/s NRZ 1500 800 1100 1100 400 270 520 700 Typ 2.0 1500 800 1100 1100 225 425 490 Min ps ps ps ps ps 225 425 490 270 520 700 ps ps ps 20% - 80% Note: 1. For Standard ECL DC Specifications, refer to the ECL Logic Family Standard DC Specification Data Sheet. 2. For part ordering description, see HPP Part Ordering Information Data Sheet. CLK SIN Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 RESET Q0 Dn-4 Dn Q1 Dn-3 Dn+1 Q2 Dn-2 Dn+2 Q3 Dn-1 Dn+3 SOUT Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 CL/4 CL/8 Timing Diagram A. 1:4 Serial to Parallel Conversion Revision 1/February 21, 2001 7 www.semtech.com SK10/100E445 HIGH-PERFORMANCE PRODUCTS AC Characteristics (continued) CLK SIN Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 Dn+4 RESET SYNC Q0 Dn-4 Dn+1 Q1 Dn-3 Dn+2 Q2 Dn-2 Dn+3 Q3 Dn-1 Dn+4 SOUT Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 Dn+4 CL/4 CL/8 Timing Diagram B. 1:4 Serial to Parallel Conversion with SYNC Pulse Ordering Information Ordering Code Package ID Temperature Range SK10E445PJ 28-PLCC Industrial SK10E445PJT 28-PLCC Industrial SK100E445PJ 28-PLCC Industrial SK100E445PJT 28-PLCC Industrial Contact Information Division Headquarters 10021 Willow Creek Road San Diego, CA 92131 Phone: (858) 695-1808 FAX: (858) 695-2633 Revision 1/February 21, 2001 Semtech Corporation High-Performance Products Division 8 Marketing Group 1111 Comstock Street Santa Clara, CA 95054 Phone: (408) 566-8776 FAX: (408) 727-8994 www.semtech.com