74ACT373 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 6 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8 µA (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN), VIL = 0.8V (MAX) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The ACT373 is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power applications mantaining high speed operation similar to equivalent Bipolar Schottky TTL. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input B M (Plastic Package) (Micro Package) ORDER CODES : 74ACT373B 74ACT373M (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input precisely or inversely. When the LE is taken low, the Q outputs will be latched precisely or inversely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. This device is designed to interface directly High Speed CMOS systems with TTL and NMOS components. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS April 1997 1/10 74ACT373 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 OE NAME AND F UNCTIO N 2, 5, 6, 9, 12, 15, 16, 19 Q0 to Q7 Data Inputs 3, 4, 7, 8, 13, 14, 17, 18 D0 to D7 3 State Outputs 11 LE Latch Enable Input 10 GND Ground (0V) 20 VCC Positive Supply Voltage 3 State Output Enable Input (Active LOW) TRUTH TABLE INPUT S OUT PUT S OE LE D Q H X X Z L L X NO CHANGE * L H L L L H H H X: DON’T CARE Z: HIGH IMPEDANCE *: Q OUTPUTS ARE LATCHED AT THE TIME WHEN THE LE INPUT IS TAKEN LOW LOGIC LEVEL. LOGIC DIAGRAMS 2/10 74ACT373 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V VI DC Input Voltage -0.5 to VCC + 0.5 V VO DC Output Voltage -0.5 to VCC + 0.5 V IIK DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 50 mA ± 400 mA ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) -65 to +150 o C 300 o C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol Valu e Unit Supply Voltage 4.5 to 5.5 V VI Input Voltage 0 to VCC V VO Output Voltage 0 to VCC VCC Top dt/dv Parameter Operating Temperature: Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1) -40 to +85 8 V o C ns/V 1) VIN from 0.8 V to 2.0 V 3/10 74ACT373 DC SPECIFICATIONS Symbol Parameter Test Con dition s VIH High Level Input Voltage 4.5 5.5 VIL Low Level Input Voltage 4.5 5.5 VOH High Level Output Voltage 4.5 5.5 4.5 VO = 0.1 V or VCC - 0.1 V (*) VI = V IH or V IL Low Level Output Voltage 4.5 5.5 4.5 5.5 (*) VI = V IH or V IL IO=-50 µA Unit o -40 to 85 C Min. Typ. 2.0 1.5 2.0 2.0 1.5 2.0 VO = 0.1 V or VCC - 0.1 V 5.5 VOL Value o T A = 25 C V CC (V) Max. Min . Max. V 1.5 0.8 0.8 1.5 0.8 0.8 4.4 4.49 5.49 V 4.4 IO=-50 µA 5.4 IO=-24 mA 3.86 3.76 IO=-24 mA 4.86 4.76 5.4 V IO=50 µA 0.001 0.1 IO=50 mA 0.001 0.1 0.1 IO=24 mA 0.36 0.44 IO=24 mA 0.36 0.44 0.1 V Input Leakage Current 5.5 VI = VCC or GND ±0.1 ±1 µA IOZ 3 State Output Leakage Current 5.5 VI = VIH or VIL VO = VCC or GND ±0.5 ±5 µA ICCT Max ICC /Input 5.5 VI = VCC -2.1 V 1.5 mA ICC Quiescent Supply Current 5.5 VI = VCC or GND 80 µA IOLD Dynamic Output Current (note 1, 2) 5.5 VOLD = 1.65 V max 75 mA VOHD = 3.85 V min -75 mA II IOHD 1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 Ω. (*) All outputs loaded. 4/10 0.6 8 74ACT373 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = t f =3 ns) Symbol Parameter T est Cond ition Value Unit o V CC (V) o -40 to 85 C T A = 25 C Min. Typ. Max. Min . Max. 6.0 10.0 11.5 tPLH tPHL Propagation Delay Time LE to Q 5.0(*) tPLH tPHL Propagation Delay Time D to Q 5.0(*) 5.5 10.0 11.5 ns tPZL tPZH Output Enable Time 5.0 (*) 6.0 9.5 10.5 ns tPLH tPHL Output Disable Time 5.0 (*) 7.0 11.0 12.5 ns tw CK Pulse Width, HIGH or LOW 5.0 (*) 1.0 7.0 8.0 ns ts Setup Time Q to CK HIGH or LOW 5.0(*) 0.5 7.0 8.0 ns th Hold Time Q to CK HIGH or LOW 5.0 (*) 0.5 0.0 1.0 ns ns (*) Voltage range is 5V ± 0.5V CAPACITIVE CHARACTERISTICS Symbol Parameter Test Con dition s V CC (V) Value T A = 25 oC Min. Typ. Max. Unit -40 to 85 o C Min . Max. Output Capacitance 5.0 10 pF CIN Input Capacitance 5.0 5 pF C PD Power Dissipation Capacitance (note 1) 5.0 25 pF C OUT 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/n (per circuit) 5/10 74ACT373 TEST CIRCUIT TEST t PLH, tPHL SWITCH Open t PZL, tPLZ 2VCC t PZH, tPHZ Open CL = 50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT =ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/10 74ACT373 WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) WAVEFORM 3: PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 7/10 74ACT373 Plastic DIP20 (0.25) MECHANICAL DATA mm DIM. MIN. a1 0.254 B 1.39 TYP. inch MAX. MIN. TYP. MAX. 0.010 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D 25.4 1.000 E 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 F 7.1 0.280 I 3.93 0.155 L Z 3.3 0.130 1.34 0.053 P001J 8/10 74ACT373 SO20 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 2.65 0.10 0.104 0.20 a2 MAX. 0.004 0.007 2.45 0.096 b 0.35 0.49 0.013 0.019 b1 0.23 0.32 0.009 0.012 C 0.50 0.020 c1 45° (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.299 L 0.50 1.27 0.19 0.050 M S 0.75 0.029 8° (max.) P013L 9/10 74ACT373 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. 1997 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A . 10/10