74VHC273 OCTAL D-TYPE FLIP FLOP WITH CLEAR PRELIMINARY DATA ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 165 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 273 IMPROVED LATCH-UP IMMUNITY LOW NOISE VOLP = 0.9V (Max.) DESCRIPTION The 74VHC273 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. M (Micro Package) T (TSSOP Package) ORDER CODES : 74VHC273M 74VHC273T Information signals applied to D inputs are transfered to the Q outputs on the positive going edge of the clock pulse. When the CLEAR input is held low, the Q outputs are held low independently of the other inputs . Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS October 1999 1/10 74VHC273 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 CLEAR NAME AND FUNCT ION 2, 5, 6, 9, 12, 15, 16, 19 Q0 to Q7 Flip-Flop Outputs 3, 4, 7, 8, 13, 14, 17, 18 D0 to D7 Data Inputs 11 CLOCK Clock Input (LOW-to-HIGH, EdgeTriggered) 10 GND Ground (0V) 20 VCC Positive Supply Voltage Asyncronous Master Reset (Active LOW) TRUTH TABLE INPUTS OUT PUT S CL EAR D CLO CK Q L X X L H L L H H H H X Qn X:Don’t Care LOGIC DIAGRAMS Thislogic diagram has notbe used to esimate propagation delays 2/10 F UNCTIO N CLEAR NO CHANGE 74VHC273 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Value Unit -0.5 to +7.0 V -0.5 to +7.0 V -0.5 to VCC + 0.5 V Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current - 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA ± 75 mA ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) -65 to +150 o 300 o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage Valu e Unit 2.0 to 5.5 V V VI Input Voltage 0 to 5.5 VO Output Voltage 0 to VCC Top dt/dv Operating Temperature V o -40 to +85 Input Rise and Fall Time (see note 1) (VCC = 3.3 ± 0.3V) (V CC = 5.0 ± 0.5V) C 0 to 100 0 to 20 ns/V ns/V 1) VIN from 30% to70%of VCC DC SPECIFICATIONS Symb ol VIH VIL VOH VOL II ICC Parameter T est Cond ition s Value o Min. Typ . Un it o T A = 25 C V CC (V) -40 to 85 C Max. Min . Max. High Level Input Voltage 2.0 1.5 1.5 3.0 to 5.5 0.7VCC 0.7VCC Low Level Input Voltage 2.0 0.5 0.5 3.0 to 5.5 0.3VCC 0.3VCC High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current V 2.0 IO=-50 µA 1.9 2.0 1.9 3.0 IO=-50 µA 2.9 3.0 2.9 4.5 IO=-50 µA 4.4 4.5 4.4 3.0 IO=-4 mA 2.58 4.5 IO=-8 mA 3.94 2.0 IO=50 µA 0.0 0.1 0.1 3.0 IO=50 µA 0.0 0.1 0.1 4.5 0.0 0.1 0.1 0.36 0.44 V V 2.48 3.8 V 3.0 IO=50 µA IO=4 mA 4.5 IO=8 mA 0.36 0.44 0 to 5.5 VI = 5.5V or GND ±0.1 ±1.0 µA 5.5 VI = VCC or GND 4 40 µA 3/10 74VHC273 AC ELECTRICAL CHARACTERISTICS (Input t r = tf =3 ns) Symb ol Parameter 3.3(*) 15 Value T A = 25 o C Min. Typ . Max. 8.7 13.6 3.3(*) 5.0(**) 5.0(**) 3.3(*) 3.3(*) 50 15 50 15 50 11.2 5.8 7.3 8.9 11.4 17.1 9.0 11.0 13.6 17.1 1.0 1.0 1.0 1.0 1.0 19.5 10.5 12.5 16.0 19.5 (**) 15 50 5.2 6.7 8.5 10.5 1.0 1.0 10.0 12.0 V CC (V) tPLH tPHL Propagation Delay Time CK to Q tPHL Propagation Delay Time CLR to Q Test Co ndition CL (pF ) 5.0 5.0(**) (*) Un it -40 to 85 o C Min . Max. 1.0 16.0 ns ns tw CLR pulse Width LOW 3.3 5.0(**) 5.0 5.0 6.0 5.0 ns tw CK pulse Width HIGH or LOW 3.3(*) 5.0(**) 5.5 5.0 6.5 5.0 ns ts Setup Time D to CK HIGH or LOW 3.3(*) 5.0(**) 5.5 4.5 6.5 4.5 ns th Hold Time D to CK HIGH or LOW 3.3(*) 5.0(**) 1.0 1.0 1.0 1.0 ns tREM Removal Time CLR to CK 3.3(*) 5.0(**) 2.5 2.0 2.5 2.0 ns fMAX Maximum Clock Frequency 3.3(*) 15 75 120 65 (*) 3.3 5.0(**) 50 15 50 120 75 165 45 100 5.0 3.3(*) (**) 50 50 80 110 5.0(**) 50 tOSLH tOSHL Output to Output Skew Time (note 1) MHz 70 1.5 1.5 1.0 1.0 ns (*) Voltage range is 3.3V ± 0.3V (**) Voltage range is 5V ± 0.5V Note 1: Parameter guaranteed by design. tsoLH = |tpLHm- tpLHn|, tsoHL = |tpHLm - tpHLn| CAPACITIVE CHARACTERISTICS Symb ol Parameter T est Cond ition s Value o T A = 25 C Min. Typ . Max. C IN Input Capacitance 4 CPD Power Dissipation Capacitance (note 1) 31 10 Un it o -40 to 85 C Min . Max. 10 pF pF 1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/8 (per Flip-Flop) 4/10 74VHC273 DYNAMIC SWITCHING CHARACTERISTICS Symb ol Parameter T est Cond ition s Dynamic Low Voltage Quiet Output (note 1, 2) 5.0 VIHD Dynamic High Voltage Input (note 1, 3) 5.0 VILD Dynamic Low Voltage Input (note 1, 3) 5.0 VOLP VOLV Value T A = 25 o C V CC (V) Min. -0.9 C L = 50 pF Un it -40 to 85 o C Typ . Max. 0.6 0.9 Min . Max. -0.6 3.5 V 1.5 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n -1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz. TEST CIRCUIT CL = 15/50 pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) 5/10 74VHC273 WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/10 74VHC273 WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) WAVEFORM 3: RECOVERY TIME (f=1MHz; 50% duty cycle) 7/10 74VHC273 SO-20 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 2.65 0.10 0.104 0.20 a2 MAX. 0.004 0.007 2.45 0.096 b 0.35 0.49 0.013 0.019 b1 0.23 0.32 0.009 0.012 C 0.50 0.020 c1 45 (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.299 L 0.50 1.27 0.19 0.050 M S 0.75 0.029 8 (max.) P013L 8/10 74VHC273 TSSOP20 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. A MIN. TYP. MAX. 1.1 0.433 A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.19 0.30 0.0075 0.0118 c 0.09 0.2 0.0035 0.0079 D 6.4 6.5 6.6 0.252 0.256 0.260 E 6.25 6.4 6.5 0.246 0.252 0.256 E1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 BSC 0.0256 BSC K 0o 4o 8o 0o 4o 8o L 0.50 0.60 0.70 0.020 0.024 0.028 A A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 9/10 74VHC273 Information furnished is believed to be accurate and reliable. However, STMicroelectronic s assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems withoutexpress written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com . 10/10