NEC UPD780031AY

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD78F0034B is a member of the µPD780034A Subseries in the 78K/0 Series, and is equivalent to the
µPD780034A (expanded-specification product) but with flash memory in place of internal ROM.
The µPD78F0034BY is a member of the µPD780034AY Subseries, featuring flash memory in place of the internal
ROM of the µPD780034AY.
The µPD78F0034B(A) and 78F0034BY(A) are products to which a quality assurance program more stringent than
that used for the µPD78F0034B and 78F0034BY (standard models) is applied (NEC Electronics classifies these
products as "special" quality grade models).
The µPD78F0034B, 78F0034BY, 78F0034B(A), and 78F0034BY(A) incorporate flash memory, which can be
programmed and erased while mounted on the board.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µPD780024A, 780034A, 780024AY, 780034AY Subseries User’s Manual: U14046E
78K/0 Series Instruction User’s Manual: U12326E
FEATURES
• Pin-compatible with mask ROM versions (except VPP pin)
• Flash memory:
32 KBNote
• Internal high-speed RAM: 1,024 bytesNote
• Supply voltage:
Note
VDD = 1.8 to 5.5 V
The flash memory and internal high-speed RAM capacities can be changed with the memory size switching
register (IMS).
Remark For the differences between the flash memory and the mask ROM versions, refer to 4. DIFFERENCES
BETWEEN µPD78F0034B, 78F0034BY, AND MASK ROM VERSIONS.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. U16369EJ1V0DS00 (1st edition)
Date Published January 2003 N CP(K)
Printed in Japan
©
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
ORDERING INFORMATION
Part Number
µPD78F0034BGB-8EU
Package
64-pin plastic LQFP (10 x 10)
Internal ROM
Flash memory
µPD78F0034BGC-8BS
64-pin plastic LQFP (14 x 14)
Flash memory
µPD78F0034BGK-9ET
64-pin plastic TQFP (12 x 12)
Flash memory
µPD78F0034BF1-CN3
73-pin plastic FBGA (9 x 9)
Flash memory
µPD78F0034BGB(A)-8EU
64-pin plastic LQFP (10 x 10)
Flash memory
µPD78F0034BGC(A)-8BS
64-pin plastic LQFP (14 x 14)
Flash memory
µPD78F0034BGK(A)-9ET
64-pin plastic TQFP (12 x 12)
Flash memory
µPD78F0034BYGB-8EU
64-pin plastic LQFP (10 x 10)
Flash memory
µPD78F0034BYGC-8BS
64-pin plastic LQFP (14 x 14)
Flash memory
µPD78F0034BYGK-9ET
64-pin plastic TQFP (12 x 12)
Flash memory
µPD78F0034BYF1-CN3
73-pin plastic FBGA (9 x 9)
Flash memory
µPD78F0034BYGB(A)-8EU
64-pin plastic LQFP (10 x 10)
Flash memory
µPD78F0034BYGC(A)-8BS
64-pin plastic LQFP (14 x 14)
Flash memory
µPD78F0034BYGK(A)-9ET
64-pin plastic TQFP (12 x 12)
Flash memory
QUALITY GRADE
Part Number
µPD78F0034BGB-8EU
Package
64-pin plastic LQFP (10 x 10)
Quality Grade
Standard
µPD78F0034BGC-8BS
64-pin plastic LQFP (14 x 14)
Standard
µPD78F0034BGK-9ET
64-pin plastic TQFP (12 x 12)
Standard
µPD78F0034BF1-CN3
73-pin plastic FBGA (9 x 9)
Standard
µPD78F0034BGB(A)-8EU
64-pin plastic LQFP (10 x 10)
Special
µPD78F0034BGC(A)-8BS
64-pin plastic LQFP (14 x 14)
Special
µPD78F0034BGK(A)-9ET
64-pin plastic TQFP (12 x 12)
Special
µPD78F0034BYGB-8EU
64-pin plastic LQFP (10 x 10)
Standard
µPD78F0034BYGC-8BS
64-pin plastic LQFP (14 x 14)
Standard
µPD78F0034BYGK-9ET
64-pin plastic TQFP (12 x 12)
Standard
µPD78F0034BYF1-CN3
73-pin plastic FBGA (9 x 9)
Standard
µPD78F0034BYGB(A)-8EU
64-pin plastic LQFP (10 x 10)
Special
µPD78F0034BYGC(A)-8BS
64-pin plastic LQFP (14 x 14)
Special
µPD78F0034BYGK(A)-9ET
64-pin plastic TQFP (12 x 12)
Special
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
2
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
CORRESPONDENCE BETWEEN MASK ROM PRODUCTS AND FLASH MEMORY PRODUCTS
• µPD780024A, 780034A Subseries
Mask ROM Products
Flash Memory Products
Expanded-specification products of µPD780021A, 780022A, 780023A, 780024A
Expanded-specification products of µPD780031A, 780032A, 780033A, 780034A
µPD78F0034B
Conventional products of µPD780021A, 780022A, 780023A, 780024A
Conventional products of µPD780031A, 780032A, 780033A, 780034A
µPD78F0034A
Expanded-specification products of µPD780021A(A), 780022A(A), 780023A(A), 780024A(A)
Expanded-specification products of µPD780031A(A), 780032A(A), 780033A(A), 780034A(A)
µPD78F0034B(A)
Conventional products of µPD780021A(A), 780022A(A), 780023A(A), 780024A(A)
Conventional products of µPD780031A(A), 780032A(A), 780033A(A), 780034A(A)
µPD78F0034B(A)
Caution The µPD78F0034B(A) and conventional products of the µPD780021A(A), 780022A(A), 780023A(A),
780024A(A) and µ PD780031A(A), 780032A(A), 780033A(A), and 780034A(A) differ in the operating
frequency ratings. When using the mask ROM versions in place of the flash memory versions,
take note of the power supply voltage and operating frequency used.
Remarks 1. The µPD78F0034B, 78F0034B(A) and 78F0034A differ in the operating frequency ratings and
communication mode of the flash memory programming. Refer to 5. DIFFERENCES BETWEEN
µPD78F0034B, 78F0034BY AND µPD78F0034A, 78F0034AY.
2. The expanded-specification products and conventional products of the mask ROM versions differ
in the operating frequency ratings. Refer to the data sheets of the products.
3. The special grade version of the µPD78F0034A is not provided (only the standard grade version
is provided).
• µPD780024AY, 780034AY Subseries
Mask ROM Products
Flash Memory Products
µPD780021AY, 780022AY, 780023AY, 780024AY
µPD780031AY, 780032AY, 780033AY, 780034AY
µPD78F0034AY
µPD78F0034BY
µPD780021AY(A), 780022AY(A), 780023AY(A), 780024AY(A)
µPD780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
µPD78F0034BY(A)
Remarks 1. The µPD78F0034BY, 78F0034BY(A) and 78F0034AY differ in the communication mode of the flash
memory programming. Refer to 5. DIFFERENCES BETWEEN µPD78F0034B, 78F0034BY AND
µPD78F0034A, 78F0034AY.
2. The expanded-specification products of the µPD780024AY, 780034AY Subseries are not provided
(only the conventional products are provided).
3. The special grade version of the µPD78F0034A is not provided (only the standard grade version
is provided).
Data Sheet U16369EJ1V0DS
3
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production
Products under development
Y subseries products are compatible with I2C bus.
Control
EMI-noise reduced version of the µPD78078
µ PD78075B
µ PD78078
µ PD78070A
µPD78078Y
µ PD78054 with timer and enhanced external interface
µ PD78070AY
80-pin
µ PD780058
µ PD780018AY
µ PD780058Y
ROMless version of the µ PD78078
µ PD78078Y with enhanced serial I/O and limited function
80-pin
µ PD78058F
µPD78054
µPD780065
100-pin
100-pin
100-pin
100-pin
80-pin
80-pin
64-pin
µ PD780078
64-pin
64-pin
52-pin
µ PD780034A
µ PD780024A
µ PD780034AS
52-pin
64-pin
µ PD780024AS
µPD78014H
64-pin
42/44-pin
µPD78018F
µ PD78083
64-pin
µPD780988
µ PD78058FY
µ PD78054 with enhanced serial I/O
EMI-noise reduced version of the µ PD78054
µ PD78018F with UART and D/A converter, and enhanced I/O
µ PD780024A with expanded RAM
µ PD780034A with timer and enhanced serial I/O
µ PD780078Y
µ PD780034AY µ PD780024A with enhanced A/D converter
µ PD780024AY µ PD78018F with enhanced serial I/O
52-pin version of the µ PD780034A
µ PD78054Y
52-pin version of the µ PD780024A
EMI-noise reduced version of the µ PD78018F
µ PD78018FY
Basic subseries for control
On-chip UART, capable of operating at low voltage (1.8 V)
Inverter control
On-chip inverter control circuit and UART. EMI-noise reduced.
VFD drive
78K/0
Series
100-pin
µ PD780208
µ PD78044F with enhanced I/O and VFD C/D. Display output total: 53
80-pin
For panel control. On-chip VFD C/D. Display output total: 53
80-pin
µ PD780232
µPD78044H
80-pin
µPD78044F
Basic subseries for driving VFD. Display output total: 34
µ PD78044F with N-ch open-drain I/O. Display output total: 34
LCD drive
100-pin
100-pin
120-pin
120-pin
120-pin
100-pin
100-pin
100-pin
µ PD780354
µ PD780344
µ PD780338
µ PD780328
µPD780318
µ PD780308
µPD78064B
µPD78064
µPD780354Y
µ PD780344 with enhanced A/D converter
µ PD780344Y
µ PD780308 with enhanced display function and timer.
µ PD780308 with enhanced display function and timer.
µ PD780308 with enhanced display function and timer.
µ PD780308 with enhanced display function and timer.
µPD780308Y
µ PD78064 with enhanced SIO, and expanded ROM and RAM
EMI-noise reduced version of the µ PD78064
µ PD78064Y
Basic subseries for driving LCDs, on-chip UART
Segment signal output: 40 pins max.
Segment signal output: 40 pins max.
Segment signal output: 32 pins max.
Segment signal output: 24 pins max.
Bus interface supported
100-pin
80-pin
µ PD780948
µ PD78098B
µ PD78054 with IEBusTM controller
µ PD780702Y
µPD780703Y
µ PD780833Y
80-pin
80-pin
80-pin
64-pin
On-chip CAN controller
µPD780816
On-chip IEBus controller
On-chip CAN controller
On-chip controller compliant with J1850 (Class 2)
Specialized for CAN controller function
Meter control
100-pin
µPD780958
80-pin
µPD780852
µPD780828B
80-pin
For industrial meter control
On-chip automobile meter controller/driver
For automobile meter driver. On-chip CAN controller
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some
documents, but the functions of the two are same.
4
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
The major functional differences among the subseries are listed below.
• Non-Y subseries
Function
Subseries Name
Control
ROM
Timer
8-Bit 10-Bit 8-Bit
Capacity
(Bytes) 8-Bit 16-Bit Watch WDT A/D A/D D/A
µPD78075B 32 K to 40 K 4 ch
µPD78078
µPD78070A
1 ch
1 ch
1 ch
8 ch
–
Serial Interface
2 ch 3 ch (UART: 1 ch)
I/O
VDD External
MIN.
Value Expansion
88
1.8 V
61
2.7 V
48 K to 60 K
–
µPD780058 24 K to 60 K 2 ch
3 ch (time-division UART: 1 ch)
68
1.8 V
µPD78058F 48 K to 60 K
3 ch (UART: 1 ch)
69
2.7 V
µPD78054
√
16 K to 60 K
2.0 V
µPD780065 40 K to 48 K
–
µPD780078 48 K to 60 K
2 ch
µPD780034A 8 K to 32 K
1 ch
–
8 ch
µPD780024A
8 ch
–
µPD780034AS
–
4 ch
µPD780024AS
4 ch
–
µPD78014H
8 ch
4 ch (UART: 1 ch)
60
2.7 V
3 ch (UART: 2 ch)
52
1.8 V
3 ch (UART: 1 ch)
51
39
–
2 ch
53
√
1 ch (UART: 1 ch)
33
–
µPD78018F 8 K to 60 K
µPD78083
8 K to 16 K
–
Inverter
control
µPD780988 16 K to 60 K 3 ch Note
VFD
drive
µPD780208 32 K to 60 K 2 ch
–
–
1 ch
–
8 ch
–
3 ch (UART: 2 ch)
47
4.0 V
√
1 ch
1 ch
1 ch
8 ch
–
–
2 ch
74
2.7 V
–
µPD780232 16 K to 24 K 3 ch
–
–
4 ch
40
4.5 V
µPD78044H 32 K to 48 K 2 ch
1 ch
1 ch
8 ch
68
2.7 V
3 ch (UART: 1 ch)
66
1.8 V
10 ch 1 ch 2 ch (UART: 1 ch)
54
1 ch
µPD78044F 16 K to 40 K
LCD
drive
2 ch
µPD780354 24 K to 32 K 4 ch
1 ch
1 ch
1 ch
µPD780344
µPD780338 48 K to 60 K 3 ch
2 ch
–
8 ch
8 ch
–
–
–
µPD780328
62
µPD780318
70
µPD780308 48 K to 60 K 2 ch
1 ch
8 ch
–
–
µPD78064B 32 K
µPD78064
3 ch (time-division UART: 1 ch)
–
57
2.0 V
79
4.0 V
√
69
2.7 V
–
2 ch (UART: 1 ch)
16 K to 32 K
Bus
µPD780948 60 K
interface
µPD78098B 40 K to 60 K
1 ch
supported µPD780816 32 K to 60 K
2 ch
2 ch
2 ch
1 ch
1 ch
8 ch
–
–
3 ch (UART: 1 ch)
2 ch
12 ch
–
2 ch (UART: 1 ch)
46
4.0 V
Meter
control
µPD780958 48 K to 60 K 4 ch
2 ch
–
1 ch
–
–
–
2 ch (UART: 1 ch)
69
2.2 V
–
Dashboard
control
µPD780852 32 K to 40 K 3 ch
1 ch
1 ch
1 ch
5 ch
–
–
3 ch (UART: 1 ch)
56
4.0 V
–
µPD780828B 32 K to 60 K
59
Note 16-bit timer: 2 channels
10-bit timer: 1 channel
Data Sheet U16369EJ1V0DS
5
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
• Y subseries
Function
Subseries Name
Control
ROM
Capacity
(Bytes)
Timer
8-Bit 16-Bit Watch WDT A/D
µPD78078Y 48 K to 60 K 4 ch
µPD78070AY
1 ch
D/A
VDD External
MIN.
Value Expansion
2 ch 3 ch (UART: 1 ch, I2C: 1 ch) 88
1.8 V
61
2.7 V
8-Bit 10-Bit 8-Bit
1 ch
1 ch
8 ch
A/D
–
Serial Interface
–
µPD780018AY 48 K to 60 K
–
µPD780058Y 24 K to 60 K 2 ch
2
3 ch (I C: 1 ch)
2 ch 3 ch (time-division UART: 1 ch, I C: 1 ch)
2
3 ch (UART: 1 ch, I C: 1 ch)
68
1.8 V
69
2.7 V
µPD78054Y 16 K to 60 K
2.0 V
µPD780078Y 48 K to 60 K
2 ch
µPD780034AY 8 K to 32 K
–
8 ch
–
1 ch
1 ch
1 ch
–
8 ch
–
8 ch
53
4 ch (UART: 1 ch,
66
1.8 V
57
2.0 V
67
3.5 V
65
4.5 V
3 ch (time-division UART: 1 ch, I2C: 1 ch)
µPD78064Y 16 K to 32 K
6
2 ch (I2C: 1 ch)
–
I C: 1 ch)
–
µPD780308Y 48 K to 60 K 2 ch
Remark
1.8 V
2
µPD780344Y
Bus
µPD780701Y 60 K
interface µPD780703Y
supported
µPD780833Y
52
–
µPD78018FY 8 K to 60 K
1 ch
4 ch (UART: 2 ch, I C: 1 ch)
3 ch (UART: 1 ch, I C: 1 ch) 51
8 ch
µPD780354Y 24 K to 32 K 4 ch
2
2
µPD780024AY
LCD
drive
√
88
2
µPD78058FY 48 K to 60 K
I/O
2
2 ch (UART: 1 ch, I C: 1 ch)
3 ch
2 ch
1 ch
1 ch 16 ch
–
–
4 ch (UART: 1 ch, I2C: 1 ch)
Functions other than the serial interface are common to both the Y and non-Y subseries.
Data Sheet U16369EJ1V0DS
–
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
OVERVIEW OF FUNCTIONS
µPD78F0034B
µPD78F0034B(A)
Part Number
Item
Internal
memory
Flash memory
32 KBNote 1
High-speed RAM
1,024 bytesNote 1
µPD78F0034BY
µPD78F0034BY(A)
Memory space
64 KB
General-purpose registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
On-chip minimum instruction execution time cycle variable function
When main system
0.166 µs/0.333 µs/0.666 µs/1.33 µs/2.66 µs
(@ 12 MHz operation, VDD = 4.5 to 5.5 V)
When subsystem
clock selected
122 µs (@ 32.768 kHz operation)
Instruction set
•
•
•
•
I/O ports
Total:
0.238 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs
(@ 8.38 MHz operation, VDD = 4.0 to 5.5 V)
16-bit operation
Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
Bit manipulation (set, reset, test, Boolean operation)
BCD adjust, etc.
51
• CMOS input:
8
• CMOS I/O:
39
• N-ch open-drain I/O (5 V withstand voltage): 4
A/D converter
• 10-bit resolution × 8 channels
• Operable over a wide power supply voltage range: AVDD = 1.8 to 5.5 V
Serial interface
• UART mode:
1 channel
• 3-wire serial I/O mode: 2 channels
Timers
•
•
•
•
Timer outputs
3 (8-bit PWM output capable: 2)
Clock output
• 93.75 kHz, 187.5 kHz, 375 kHz, 750 kHz,
1.25 MHz, 3 MHz, 6 MHz, 12 MHz
(@ 12 MHz operation with main system
clock)
• 32.768 kHz (@ 32.768 kHz operation with
subsystem clock)
• 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05
MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz
(@ 8.38 MHz operation with main system
clock)
• 32.768 kHz (@ 32.768 kHz operation with
subsystem clock)
Buzzer output
1.46 kHz, 2.93 kHz, 5.86 kHz, 11.7 kHz
(@ 12 MHz operation with main system clock)
1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz
(@ 8.38 MHz operation with main system clock)
Vectored interrupt
sources
Maskable
16-bit timer/event counter:
8-bit timer/event counter:
Watch timer:
Watchdog timer:
UART mode:
1 channel
3-wire serial I/O mode: 1 channel
I2C bus mode
(multimaster supporting): 1 channel
channel
channels
channel
channel
Internal: 13, external: 5
Non-maskable
Internal: 1
Software
1
Test inputs
Internal: 1, external: 1
Supply voltage
VDD = 1.8 to 5.5 V
Operating ambient temperature
TA = –40 to +85°C
Package
•
•
•
•
Notes 1.
1
2
1
1
•
•
•
64-pin
64-pin
64-pin
73-pin
plastic
plastic
plastic
plastic
LQFP (10 x 10)
LQFP (14 x 14)
TQFP (12 x 12)
FBGA (9 x 9)Note 2
The capacities of the flash memory and the internal high-speed RAM can be changed with the memory
size switching register (IMS).
2.
The special grade version of the 73-pin plastic FBGA (9 x 9) is not provided.
Data Sheet U16369EJ1V0DS
7
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ..............................................................................................
9
2. BLOCK DIAGRAM .......................................................................................................................... 12
3. PIN FUNCTIONS ............................................................................................................................. 13
3.1
Port Pins .................................................................................................................................................
13
3.2
Non-Port Pins .........................................................................................................................................
14
3.3
Pin I/O Circuits and Recommended Connection of Unused Pins ..................................................
16
4. DIFFERENCES BETWEEN µPD78F0034B, 78F0034BY, AND MASK ROM VERSIONS ......... 19
5. DIFFERENCES BETWEEN µPD78F0034B, 78F0034BY AND µPD78F0034A, 78F0034AY ..... 21
6. DIFFERENCES BETWEEN µ PD78F0034B, 78F0034BY AND µ PD78F0034B(A), 78F0034BY(A) ..... 22
7. MEMORY SIZE SWITCHING REGISTER (IMS) ............................................................................ 23
8. FLASH MEMORY PROGRAMMING .............................................................................................. 24
8.1
Selection of Communication Mode .....................................................................................................
24
8.2
Flash Memory Programming Functions .............................................................................................
26
8.3
Connection of Flashpro III/Flashpro IV ..............................................................................................
26
9. ELECTRICAL SPECIFICATIONS ................................................................................................... 28
9.2
µPD78F0034B, 78F0034B(A) ................................................................................................................
µPD78F0034BY, 78F0034BY(A) ............................................................................................................
46
9.3
Timing Chart ...........................................................................................................................................
64
9.1
28
10. PACKAGE DRAWINGS .................................................................................................................. 71
11. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 75
APPENDIX A. DEVELOPMENT TOOLS ............................................................................................. 77
APPENDIX B. RELATED DOCUMENTS ............................................................................................ 85
8
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
1. PIN CONFIGURATION (TOP VIEW)
• 64-pin plastic LQFP (10 x 10)
• 64-pin plastic TQFP (12 x 12)
P72/TI50/TO50
P73/TI51/TO51
P74/PCL
P75/BUZ
P64/RD
P65/WR
P66/WAIT
P67/ASTB
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
• 64-pin plastic LQFP (14 x 14)
P50/A8
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
P51/A9
2
47
P70/TI00/TO0
P52/A10
3
46
P03/INTP3/ADTRG
P53/A11
4
45
P02/INTP2
P54/A12
5
44
P01/INTP1
P55/A13
6
43
P00/INTP0
P56/A14
7
42
VSS1
P57/A15
8
41
X1
P71/TI01
VSS0
9
40
X2
VDD0
10
39
VPP
P30
11
38
XT1
P31
12
37
XT2
Note 1
P32/SDA0
13
36
RESET
P33/SCL0Note 1
14
35
AVDD
Note 2
15
34
AVREF
Notes 1.
2.
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
P14/ANI4
P15/ANI5
P16/ANI6
AVSS
P17/ANI7
VDD1
P25/ASCK0
P24/TxD0
P23/RxD0
P21/SO30
P22/SCK30
P36/SCK31Note 2
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P20/SI30
P34/SI31
P35/SO31Note 2
SDA0 and SCL0 are incorporated only in the µPD78F0034BY, 78F0034BY(A) Subseries.
SI31, SO31, and SCK31 are incorporated only in the µPD78F0034B, 78F0034B(A) Subseries.
Cautions 1. Connect the VPP pin directly to VSS0 or VSS1 in normal operation mode.
2. Connect the AVSS pin to VSS0.
Remark When the µPD78F0034B, 78F0034BY, 78F0034B(A), and 78F0034BY(A) are used in application fields
that require reduction of the noise generated from inside the microcontroller, the implementation of noise
reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and
VSS1 to different ground lines, is recommended.
Data Sheet U16369EJ1V0DS
9
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
• 73-pin plastic FBGA (9 x 9)
Top View
Bottom View
9
8
7
6
5
4
3
2
1
A B C D E F G H J
J H G F E D C B A
Index mark
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
A1
NC
C1
P52/A10
E1
P57/A15
G1
P33/SCL0Note 1
J1
NC
A2
P46/AD6
C2
P53/A11
E2
VDD0
G2
P32/SDA0Note 1
J2
P36/SCK31Note 2
A3
P44/AD4
C3
P45/AD5
E3
P54/A12
G3
P20/SI30
J3
NC
A4
P41/AD1
C4
P42/AD2
E4
−
G4
P21/SO30
J4
P25/ASCK0
A5
P67/ASTB
C5
P64/RD
E5
−
G5
P24/TxD0
J5
NC
A6
P65/WR
C6
P73/TI51/TO51
E6
−
G6
VDD1
J6
P17/ANI7
A7
P74/PCL
C7
P03/INTP3/ADTRG
E7
P00/INTP0
G7
P16/ANI6
J7
P12/ANI2
A8
NC
C8
P01/INTP1
E8
XT1
G8
AVDD
J8
P13/ANI3
A9
NC
C9
VSS1
E9
X2
G9
NC
J9
NC
B1
P51/A9
D1
P55/A13
F1
P30
H1
P34/SI31Note 2
B2
P47/AD7
D2
P56/A14
F2
P31
H2
P35/SO31Note 2
B3
P43/AD3
D3
P50/A8
F3
VSS0
H3
P23/RxD0
B4
P40/AD0
D4
NC
F4
−
H4
P22/SCK30
B5
P66/WAIT
D5
−
F5
−
H5
AVSS
B6
P75/BUZ
D6
−
F6
−
H6
P15/ANI5
B7
P72/TI50/TO51
D7
P02/INTP2
F7
P14/ANI4
H7
P11/ANI1
B8
P71/TI01
D8
VPP
F8
RESET
H8
P10/ANI0
B9
P70/TI00/TO0
D9
X1
F9
XT2
H9
AVREF
Notes 1. SDA0 and SCL0 are incorporated only in the µPD78F0034BY Subseries.
2. SI31, SO31, and SCK31 are incorporated only in the µPD78F0034B Subseries.
Cautions 1. Connect the VPP pin directly to VSS0 or VSS1 in normal operation mode.
2. Connect the AVSS pin to VSS0.
Remarks 1. When the µPD78F0034B, 78F0034BY, 78F0034B(A), and 78F0034BY(A) are used in application
fields that require reduction of the noise generated from inside the microcontroller, the implementation
of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting
VSS0 and VSS1 to different ground lines, is recommended.
2. The special grade version of the 73-pin plastic FBGA (9 x 9) is not provided.
10
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
A8 to A15:
Address bus
P70 to P75:
Port 7
AD0 to AD7:
Address/data bus
PCL:
Programmable clock
ADTRG:
AD trigger input
RD:
Read strobe
ANI0 to ANI7:
Analog input
RESET:
Reset
ASCK0:
Asynchronous serial clock
RxD0:
Receive data
ASTB:
Address strobe
SCK30, SCK31, SCL0: Serial clock
AVDD:
Analog power supply
SDA0:
Serial data
AVREF:
Analog reference voltage
SI30, SI31:
Serial input
AVSS:
Analog ground
SO30, SO31:
Serial output
BUZ:
Buzzer clock
TI00, TI01, TI50, TI51: Timer input
INTP0 to INTP3:
External interrupt input
TO0, TO50, TO51:
Timer output
NC:
No connection
TxD0:
Transmit data
P00 to P03:
Port 0
VDD0, VDD1:
Power supply
P10 to P17:
Port 1
VPP:
Programming power supply
P20 to P25:
Port 2
VSS0, VSS1:
Ground
P30 to P36:
Port 3
WAIT:
Wait
P40 to P47:
Port 4
WR:
Write strobe
P50 to P57:
Port 5
X1, X2:
Crystal (main system clock)
P64 to P67:
Port 6
XT1, XT2:
Crystal (subsystem clock)
Data Sheet U16369EJ1V0DS
11
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
2. BLOCK DIAGRAM
TI00/TO0/P70
16-bit timer/
event counter
Port 0
P00 to P03
TI50/TO50/P72
8-bit timer/
event counter 50
Port 1
P10 to P17
TI51/TO51/P73
8-bit timer/
event counter 51
Port 2
P20 to P25
Port 3
P30 to P36
Port 4
P40 to P47
Port 5
P50 to P57
Port 6
P64 to P67
Port 7
P70 to P75
External access
AD0/P40 to
AD7/P47
A8/P50 to
A15/P57
RD/P64
WR/P65
WAIT/P66
ASTB/P67
TI01/P71
Watchdog timer
Watch timer
78K/0
CPU core
SI30/P20
SO30/P21
SCK30/P22
Serial
interface 30
SI31/P34
SO31/P35
SCK31/P36
Serial
interface 31Note 1
RxD0/P23
TxD0/P24
ASCK0/P25
SDA0/P32
UART0
Flash
memory
(32 KB)
RAM
(1,024
bytes)
I2C busNote 2
SCL0/P33
ANI0/P10 to
ANI7/P17
AVDD
AVSS
AVREF
A/D converter
RESET
X1
INTP0/P00 to
INTP3/P03
Buzzer output
PCL/P74
Clock output
control
2.
12
X2
XT1
BUZ/P75
Notes 1.
System control
Interrupt control
XT2
VDD0 VDD1 VSS0 VSS1 VPP
Incorporated only in the µPD78F0034B and 78F0034B(A)
Incorporated only in the µPD78F0034BY and 78F0034BY(A)
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
Pin Name
P00
I/O
I/O
Function
Port 0
After Reset
Input
4-bit I/O port.
P01
INTP0
INTP1
Input/output can be specified in 1-bit units.
P02
Alternate
Function
INTP2
An on-chip pull-up resistor can be specified by software.
P03
INTP3/ADTRG
P10 to P17
P20
Input
I/O
Port 1
8-bit input-only port.
Input
ANI0 to ANI7
Port 2
Input
SI30
6-bit I/O port.
P21
SO30
Input/output can be specified in 1-bit units.
P22
SCK30
An on-chip pull-up resistor can be specified by software.
P23
RxD0
P24
TxD0
P25
ASCK0
P30
I/O
P31
Port 3
N-ch open-drain I/O port.
7-bit I/O port.
LEDs can be driven directly.
Input
Input/output can be specified
P32
–
SDA0Note 1
in 1-bit units.
SCL0Note 1
P33
P34
An on-chip pull-up resistor can be
SI31Note 2
P35
specified by software.
SO31Note 2
SCK31Note 2
P36
P40 to P47
I/O
Port 4
8-bit I/O port.
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by software.
Interrupt request flag KRIF is set to 1 by falling edge detection.
Input
AD0 to AD7
P50 to P57
I/O
Port 5
8-bit I/O port.
LEDs can be driven directly.
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by software.
Input
A8 to A15
P64
I/O
Port 6
Input
RD
4-bit I/O port.
P65
WR
Input/output can be specified in 1-bit units.
P66
An on-chip pull-up resistor can be specified by software.
P67
WAIT
ASTB
Notes 1.
2.
SDA0 and SCL0 are incorporated only in the µPD78F0034BY and 78F0034BY(A).
SI31, SO31, and SCK31 are incorporated only in the µPD78F0034B and 78F0034B(A).
Data Sheet U16369EJ1V0DS
13
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
3.1 Port Pins (2/2)
Pin Name
P70
I/O
I/O
Function
Port 7
After Reset
Input
6-bit I/O port.
P71
TI00/TO0
TI01
Input/output can be specified in 1-bit units.
P72
Alternate
Function
TI50/TO50
An on-chip pull-up resistor can be specified by software.
P73
TI51/TO51
P74
PCL
P75
BUZ
3.2 Non-Port Pins (1/2)
Pin Name
INTP0
I/O
Input
Function
External interrupt request input by which the valid edge (rising edge,
After Reset
Input
falling edge, or both rising and falling edges) can be specified.
INTP1
Alternate
Function
P00
P01
INTP2
P02
INTP3
P03/ADTRG
SI30
Input
Serial interface serial data input.
Input
SI31Note 1
SDA0Note 2
SO30
P34
I/O
Output
Serial interface serial data input/output
Input
P32
Serial interface serial data output.
Input
P21
SO31Note 1
SCK30
P20
P35
I/O
Serial interface serial clock input/output.
Input
P22
SCK31Note 1
P36
SCL0Note 2
P33
RxD0
Input
Serial data input for asynchronous serial interface.
Input
P23
TxD0
Output
Serial data output for asynchronous serial interface.
Input
P24
ASCK0
Input
Serial clock input for asynchronous serial interface.
Input
P25
TI00
Input
External count clock input to 16-bit timer/event counter 0.
Capture trigger signal input to capture register 01 (CR01) of 16-bit timer/
event counter 0.
Input
P70/TO0
TI01
Capture trigger signal input to capture register 00 (CR00) of 16-bit timer/
event counter 0.
P71
TI50
External count clock input to 8-bit timer/event counter 50.
P72/TO50
TI51
External count clock input to 8-bit timer/event counter 51.
P73/TO51
TO0
Output
16-bit timer/event counter 0 output.
Input
P70/TI00
TO50
8-bit timer/event counter 50 output (shared with 8-bit PWM output).
Input
P72/TI50
TO51
8-bit timer/event counter 51 output (shared with 8-bit PWM output).
P73/TI51
PCL
Output
Clock output (for trimming of main system clock and subsystem clock).
Input
P74
BUZ
Output
Buzzer output.
Input
P75
Lower address/data bus for extending memory externally.
Input
P40 to P47
AD0 to AD7
Notes 1.
2.
14
I/O
SI31, SO31, and SCK31 are incorporated only in the µPD78F0034B and 78F0034B(A).
SDA0 and SCL0 are incorporated only in the µPD78F0034BY and 78F0034BY(A).
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
3.2 Non-Port Pins (2/2)
Pin Name
I/O
Function
After Reset
Alternate
Function
A8 to A15
Output
Higher address bus for extending memory externally.
Input
P50 to P57
RD
Output
Strobe signal output for read operation of external memory.
Input
P64
WR
Strobe signal output for write operation of external memory.
WAIT
Input
ASTB
Output
P65
Inserting wait for accessing external memory.
Input
P66
Strobe output which externally latches address information output to
ports 4 and 5 to access external memory.
Input
P67
ANI0 to ANI7
Input
A/D converter analog input.
Input
P10 to P17
ADTRG
Input
A/D converter trigger signal input.
Input
P03/INTP3
AVREF
Input
A/D converter reference voltage input.
–
–
AVDD
–
A/D converter analog power supply.
Set the voltage equal to VDD0 or VDD1.
–
–
AVSS
–
A/D converter ground potential.
Set the voltage equal to VSS0 or VSS1.
–
–
RESET
Input
System reset input.
–
–
X1
Input
Connecting crystal resonator for main system clock oscillation.
–
–
X2
–
–
–
–
–
–
–
XT1
Input
XT2
–
VDD0
–
Positive power supply voltage for ports.
–
–
VSS0
–
Ground potential of ports.
–
–
VDD1
–
Positive power supply (except ports).
–
–
VSS1
–
Ground potential (except ports).
–
–
VPP
–
Applying high-voltage for program write/verify. Connect to VSS0 or VSS1
in normal operation mode.
–
–
–
Not internally connected. Leave open.
–
–
NC
Note
Note
Connecting crystal resonator for subsystem clock oscillation.
NC is incorporated only in the 73-pin plastic FBGA.
Data Sheet U16369EJ1V0DS
15
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the input/output configuration of each type, refer to Figure 3-1 .
Table 3-1. Types of Pin I/O Circuits (1/2)
Pin Name
P00/INTP0
I/O Circuit Type
I/O
8-C
I/O
Recommended Connection of Unused Pins
Input: Independently connect to VSS0 or VSS1 via a
via a resistor.
P01/INTP1
Output: Leave open.
P02/INTP2
P03/INTP3/ADTRG
P10/ANI0 to P17/ANI7
25
Input
P20/SI30
8-C
I/O
P21/SO30
5-H
P22/SCK30
8-C
Directly connect to VDD0, VDD1, VSS0, or VSS1.
Input: Independently connect to VDD0, VDD1, VSS0, or
VSS1 via a resistor.
Output: Leave open.
P23/RxD0
P24/TxD0
5-H
P25/ASCK0
8-C
P30, P31
13-P
Input: Directly connect to VSS0 or VSS1.
P32/SDA0Note 1
13-R
Output: Leave open at low-level output.
P34/SI31Note 2
8-C
Input: Independently connect to VDD0, VDD1, VSS0 or
P35/SO31Note 2
5-H
P33/SCL0Note 1
VSS1 via a resistor.
Output: Leave open.
P36/SCK31Note 2
8-C
P40/AD0 to P47/AD7
5-H
Input: Independently connect to VDD0 or VDD1 via a
resistor.
Output: Leave open.
P50/A8 to P57/A15
5-H
Input: Independently connect to VDD0, VDD1, VSS0, or
VSS1 via a resistor.
P64/RD
Output: Leave open.
P65/WR
P66/WAIT
P67/ASTB
P70/TI00/TO0
8-C
P71/TI01
P72/TI50/TO50
P73/TI51/TO51
P74/PCL
5-H
P75/BUZ
Notes 1.
2.
16
SDA0 and SCL0 are incorporated only in the µPD78F0034BY and 78F0034BY(A).
SI31, SO31, and SCK31 are incorporated only in the µPD78F0034B and 78F0034B(A).
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Table 3-1. Types of Pin I/O Circuits (2/2)
Pin Name
I/O Circuit Type
I/O
Recommended Connection of Unused Pins
RESET
2
Input
–
XT1
16
XT2
AVDD
AVREF
Directly connect to VDD0 or VDD1.
–
–
Leave open.
Directly connect to VDD0 or VDD1.
Directly connect to VSS0 or VSS1.
AVSS
VPP
Connect to VSS0 or VSS1.
Data Sheet U16369EJ1V0DS
17
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Figure 3-1. Pin I/O Circuits
TYPE 2
TYPE 13-R
IN/OUT
Data
Output disable
N-ch
IN
VSS0
Schmitt-triggered input with hysteresis characteristics
TYPE 5-H
Pullup
enable
Data
TYPE 16
VDD0
Feedback
cut-off
P-ch
P-ch
VDD0
P-ch
IN/OUT
Output
disable
N-ch
VSS0
XT1
XT2
Input
enable
TYPE 25
TYPE 8-C
VDD0
Pullup
enable
Data
P-ch
Comparator
P-ch
–
VDD0
N-ch
VSS0
VREF (threshold voltage)
P-ch
IN/OUT
Output
disable
Input
enable
N-ch
VSS0
TYPE 13-P
Data
Output disable
IN/OUT
N-ch
VSS0
Input
enable
18
+
Data Sheet U16369EJ1V0DS
IN
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
4. DIFFERENCES BETWEEN µPD78F0034B, 78F0034BY, AND MASK ROM VERSIONS
The µPD78F0034B and 78F0034BY are products provided with a flash memory which enables writing, erasing,
and rewriting of programs with device mounted on the target system.
The functions of the µPD78F0034B and 78F0034BY (except the functions specified for flash memory) can be made
the same as those of the mask ROM versions by setting the memory size switching register (IMS).
Tables 4-1 and 4-2 show the differences between the µPD78F0034B, 78F0034BY and the mask ROM versions.
Table 4-1. Differences Between µ PD78F0034B and Mask ROM Versions
Item
µPD78F0034B
Mask ROM Versions
µPD780034A Subseries
µPD780024A SubseriesNote
Internal ROM structure
Flash memory
Mask ROM
Internal ROM capacity
32 KB
µPD780031A:
µPD780032A:
µPD780033A:
µPD780034A:
8 KB
16 KB
24 KB
32 KB
µPD780021A:
µPD780022A:
µPD780023A:
µPD780024A:
8 KB
16 KB
24 KB
32 KB
Internal high-speed RAM capacity
1,024 bytes
µPD780031A:
µPD780032A:
µPD780033A:
µPD780034A:
512 bytes
512 bytes
1,024 bytes
1,024 bytes
µPD780021A:
µPD780022A:
µPD780023A:
µPD780024A:
512 bytes
512 bytes
1,024 bytes
1,024 bytes
Minimum instruction execution time
Minimum instruction execution time variable function incorporated
When main system clock is selected <µPD78F0034B and expanded-specification products of the mask ROM versions>
0.166 µs/0.333 µs/0.666 µs/1.33 µs/2.66 µs (@ 12 MHz operation, VDD = 4.5 to 5.5 V)
<Conventional products of the mask ROM versions>
0.238 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs (@ 8.38 MHz operation, VDD = 4.0 to 5.5 V)
When subsystem clock is selected
122 µs (32.768 kHz)
Clock output
<µPD78F0034B and expanded-specification products of the mask ROM versions>
• 93.75 kHz, 187.5 kHz, 375 kHz, 750 kHz, 1.25 MHz, 3 MHz, 6 MHz, 12 MHz
(@ 12 MHz operation with main system clock)
• 32.768 kHz (@ 32.768 kHz operation with subsystem clock)
<Conventional products of the mask ROM versions>
• 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz
(@ 8.38 MHz operation with main system clock)
• 32.768 kHz (@ 32.768 kHz operation with subsystem clock)
Buzzer output
<µPD78F0034B and expanded-specification products of the mask ROM versions>
1.46 kHz, 2.93 kHz, 5.86 kHz, 11.7 kHz (@ 12 MHz operation with main system clock)
<Conventional products of the mask ROM versions>
• 1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (@ 8.38 MHz operation with main system clock)
A/D converter resolution
10 bits
Mask option specification of on-chip
pull-up resistor for pins P30 to P33
Not available
Available
IC pin
Not provided
Provided
VPP pin
Provided
Not provided
Electrical specifications,
recommended soldering conditions
Refer to the data sheet of individual products.
Note
8 bits
The µPD78F0034B can be used as the flash memory version of the µPD780024A Subseries.
Caution There are differences in noise immunity and noise radiation between the flash memory and mask
ROM versions. When pre-producing an application set with the flash memory version and then mass
producing it with the mask ROM version, be sure to conduct sufficient evaluations on the
commercial samples (CS) (not engineering samples (ES)) of the mask ROM versions.
Data Sheet U16369EJ1V0DS
19
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Table 4-2. Differences Between µPD78F0034BY and Mask ROM Versions
Item
µPD78F0034BY
Mask ROM Versions
µPD780034AY Subseries
Internal ROM structure
Flash memory
Mask ROM
Internal ROM capacity
32 KB
µPD780031AY:
µPD780032AY:
µPD780033AY:
µPD780034AY:
8 KB
16 KB
24 KB
32 KB
µPD780031AY: 512 bytes
µPD780032AY: 512 bytes
µPD780033AY: 1,024 bytes
µPD780034AY: 1,024 bytes
µPD780024AY SubseriesNote
µPD780021AY:
µPD780022AY:
µPD780023AY:
µPD780024AY:
8 KB
16 KB
24 KB
32 KB
µPD780021AY: 512 bytes
µPD780022AY: 512 bytes
µPD780023AY: 1,024 bytes
µPD780024AY: 1,024 bytes
Internal high-speed RAM capacity
1,024 bytes
Minimum instruction execution time
Minimum instruction execution time variable function incorporated
When main system clock is selected 0.238 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs
(operation at 8.38 MHz, VDD = 4.0 to 5.5 V)
When subsystem clock is selected
Clock output
122 µs (32.768 kHz)
• 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz
(@ 8.38 MHz operation with main system clock)
• 32.768 kHz
(@ 32.768 kHz operation with subsystem clock)
Buzzer output
1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz
(@ 8.38 MHz operation with main system clock)
A/D converter resolution
10 bits
Mask option specification of on-chip
Not available
Available
IC pin
Not provided
Provided
VPP pin
Provided
Not provided
Electrical specifications,
recommended soldering conditions
Refer to the data sheet of individual products.
8 bits
pull-up resistor for pins P30 and P31
Note
The µPD78F0034BY can be used as the flash memory version of the µPD780024AY Subseries.
Caution There are differences in noise immunity and noise radiation between the flash memory and mask
ROM versions. When pre-producing an application set with the flash memory version and then mass
producing it with the mask ROM version, be sure to conduct sufficient evaluations on the
commercial samples (CS) (not engineering samples (ES)) of the mask ROM versions.
20
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
5. DIFFERENCES BETWEEN µPD78F0034B, 78F0034BY AND µPD78F0034A, 78F0034AY
Table 5-1 shows the differences between the µPD78F0034B and µPD78F0034A, and Table 5-2 shows differences
between the µPD78F0034BY and 78F0034AY.
Table 5-1. Differences Between µ PD78F0034B and µPD78F0034A
µPD78F0034B
Item
µPD78F0034A
Guaranteed operating speed
4.5 to 5.5 V
12 MHz (0.166 µs)
8.38 MHz (0.238 µs)
(operating frequency)
4.0 to 5.5 V
8.38 MHz (0.238 µs)
8.38 MHz (0.238 µs)
3.0 to 5.5 V
8.38 MHz (0.238 µs)
5 MHz (0.4 µs)
2.7 to 5.5 V
5 MHz (0.4 µs)
5 MHz (0.4 µs)
1.8 to 5.5 V
1.25 MHz (1.6 µs)
1.25 MHz (1.6 µs)
Maximum instruction execution time
Minimum instruction execution time variable function incorporated
When main system clock is selected
0.166 µs/0.333 µs/0.666 µs/1.33 µs/2.66 µs
(@ 12 MHz operation, VDD = 4.5 to 5.5 V)
When subsystem clock is selected
122 µs (32.768 kHz)
0.238 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs
(@ 8.38 MHz operation, VDD = 4.0 to 5.5 V)
Clock output
• 93.75 kHz, 187.5 kHz, 375 kHz, 750 kHz,
1.25 MHz, 3 MHz, 6 MHz, 12 MHz (@ 12
MHz operation with main system clock)
• 32.768 kHz (@ 32.768 kHz operation
with subsystem clock)
• 65.5 kHz, 131 kHz, 262 kHz, 524 kHz,
1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38
MHz (@ 8.38 MHz operation with main
system clock)
• 32.768 kHz (@ 32.768 kHz operation
with subsystem clock)
Buzzer output
1.46 kHz, 2.93 kHz, 5.86 kHz, 11.7 kHz
(@ 12 MHz operation with main system
clock)
1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz
(@ 8.38 MHz operation with main system
clock)
Communication mode of flash memory
programming
• 3-wire serial I/O:
2 channels
• UART:
1 channel
• Pseudo 3-wire serial I/O: 1 channel
Electrical specifications, recommended
soldering conditions
Refer to the data sheet of individual products.
Note
Note
• 3-wire serial I/O:
2 channels
• UART:
1 channel
• Pseudo 3-wire serial I/O: 1 channel
Note
The µPD78F0034B can use one channel (serial interface SIO30) as a handshake mode.
The µPD78F0034A cannot use a handshake mode.
Remark The operating frequency ratings of the µPD78F0034B and the expanded-specification products of the
mask ROM versions of the µPD780024A, 780034A Subseries are the same. The operating frequency
ratings of the µPD78F0034A and the conventional products of the mask ROM versions of the
µPD780024A, 780034A Subseries are the same.
Data Sheet U16369EJ1V0DS
21
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Table 5-2. Differences Between µPD78F0034BY and µPD78F0034AY
µPD78F0034BY
Item
Guaranteed operating speed
4.5 to 5.5 V
8.38 MHz (0.238 µs)
(operating frequency)
4.0 to 5.5 V
8.38 MHz (0.238 µs)
3.0 to 5.5 V
5 MHz (0.4 µs)
2.7 to 5.5 V
5 MHz (0.4 µs)
1.8 to 5.5 V
1.25 MHz (1.6 µs)
Maximum instruction execution time
µPD78F0034AY
Minimum instruction execution time variable function incorporated
When main system clock is selected
0.238 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs (@ 8.38 MHz operation, VDD =
4.0 to 5.5 V)
When subsystem clock is selected
122 µs (32.768 kHz)
Clock output
• 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz,
8.38 MHz (@ 8.38 MHz operation with main system clock)
• 32.768 kHz (@ 32.768 kHz operation with subsystem clock)
Buzzer output
1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (@ 8.38 MHz operation with main
system clock)
Communication mode of flash memory
• 3-wire serial I/O:
2 channels
• UART:
1 channel
• Pseudo 3-wire serial I/O: 1 channel
programming
Electrical specifications, recommended
soldering conditions
Note
Note
• 3-wire serial I/O:
2 channels
• UART:
1 channel
• Pseudo 3-wire serial I/O: 1 channel
Note
Refer to the data sheet of individual products.
The µPD78F0034BY can use one channel (serial interface SIO30) as a handshake mode.
The µPD78F0034AY cannot use a handshake mode.
Remark The operating frequency ratings of the µPD78F0034BY, 78F0034AY and the mask ROM versions of the
µPD780024AY, 780034AY Subseries are the same.
6. DIFFERENCES BETWEEN µPD78F0034B, 78F0034BY AND µPD78F0034B(A), 78F0034BY(A)
The µPD78F0034(A) and 78F0034BY(A) are products to which a quality assurance program more stringent than
that used for the µPD780034B and 780034BY (standard models) is applied (NEC Electronics classifies these products
as "special" quality grade models).
The µPD78F0034B, 78F0034BY and µPD78F0034B(A), 78F0034BY(A) only differ in the quality grade; there are
no differences in functions and electrical specifications.
Table 6-1. Differences Between µPD78F0034B, 78F0034BY and µPD78F0034B(A), 78F0034BY(A)
Item
µPD78F0034B, 78F0034BY
Quality grade
Standard
Functions and electrical specifications
No differences.
22
Data Sheet U16369EJ1V0DS
µPD78F0034B(A), 78F0034BY(A)
Special
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
7. MEMORY SIZE SWITCHING REGISTER (IMS)
IMS is a register that is set by software and is used to specify a part of the internal memory that is not to be used.
By setting memory size switching register (IMS), the internal memory of the µPD78F0034B, 78F0034BY, 78F0034B(A),
and 78F0034BY(A) can be mapped identically to that of a mask ROM version.
IMS is set with an 8-bit memory manipulation instruction.
RESET input sets IMS to CFH.
Caution The initial value of IMS is setting disabled (CFH). Be sure to set C8H or the value of the target
mask ROM version at the moment of initial setting.
Figure 7-1. Format of Memory Size Switching Register
7
IMS
6
5
RAM2 RAM1 RAM0
4
0
3
2
1
0
ROM3 ROM2 ROM1 ROM0
Address
After reset
R/W
FFF0H
CFH
R/W
ROM3 ROM2 ROM1 ROM0 Selection of Internal ROM Capacity
0
0
1
0
8 KB
0
1
0
0
16 KB
0
1
1
0
24 KB
1
0
0
0
32 KB
Other than above
Setting prohibited
RAM2 RAM1 RAM0 Selection of Internal High-Speed RAM Capacity
0
1
0
512 bytes
1
1
0
1,024 bytes
Other than above
Setting prohibited
Table 7-1 shows the IMS set value to make the memory mapping the same as those of mask ROM versions.
Table 7-1. Set Value of Memory Size Switching Register
Target Mask ROM Versions
IMS Set Value
µPD780021A, 780021AY, 780031A, 780031AY
42H
µPD780022A, 780022AY, 780032A, 780032AY
44H
µPD780023A, 780023AY, 780033A, 780033AY
C6H
µPD780024A, 780024AY, 780034A, 780034AY
C8H
Data Sheet U16369EJ1V0DS
23
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
8. FLASH MEMORY PROGRAMMING
Writing to flash memory can be performed without removing the memory from the target system (on board
programming). Writing is performed with the dedicated flash programmer (Flashpro III (part No.: FL-PR3 and PGFP3)/(Flashpro IV (part No.: FL-PR4 and PG-FP4)) connected to the host machine and the target system.
Writing to flash memory can also be performed using flash memory writing adapter connected to Flashpro III/
Flashpro IV.
Remark FL-PR3 and FL-PR4 are products of Naito Densei Machida Mfg. Co., Ltd.
8.1 Selection of Communication Mode
Writing to a flash memory is performed using Flashpro III/Flashpro IV in a serial communication. Select one of
the communication modes in Tables 8-1 and 8-2. The selection of the communication mode is made by using the
format shown in Figure 8-1. Each communication mode is selected by the number of VPP pulses shown in Tables
8-1 and 8-2.
Table 8-1. List of Communication Mode (µ PD78F0034B)
Communication Mode
3-wire serial I/O
Channels
2
Pin Used
VPP Pulses
SI30/P20
SO30/P21
SCK30/P22
0
SI31/P34
SO31/P35
SCK31/P36
1
SI30/P20
SO30/P21
SCK30/P22
3
HS/P25
UART
1
RxD0/P23
TxD0/P24
8
Pseudo 3-wire serial I/O
1
P72/TI50/TO50
(serial clock input)
P71/TI01
(serial data output)
P70/TI00/TO0
(serial data input)
12
Caution Be sure to select a communication mode using the number of VPP pulses shown in Table 8-1.
24
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Table 8-2. List of Communication Mode (µPD78F0034BY)
Communication Mode
3-wire serial I/O
Channels
Pin Used
1
VPP Pulses
SI30/P20
SO30/P21
SCK30/P22
0
SI30/P20
SO30/P21
SCK30/P22
HS/P25
3
I2C bus
1
SDA0/P32
SCL0/P33
4
UART
1
RxD0/P23
TxD0/P24
8
Pseudo 3-wire serial I/O
1
P72/TI50/TO50
(serial clock input)
P71/TI01
(serial data output)
P70/TI00/TO0
(serial data input)
12
Caution Be sure to select a communication mode using the number of VPP pulses shown in Table 8-2.
Figure 8-1. Format of Communication Mode Selection
VPP pulses
10 V
VPP
VDD
1
2
n
VSS
VDD
RESET
VSS
Flash write mode
Data Sheet U16369EJ1V0DS
25
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
8.2 Flash Memory Programming Functions
Operations such as writing to flash memory are performed by various command/data transmission and reception
operations according to the selected communication mode. Table 8-3 shows major functions of flash memory
programming.
Table 8-3. Major Functions of Flash Memory Programming
Function
Description
Reset
Used to stop write operation and detect transmission cycle.
Batch verify
Compares the entire memory contents with the input data.
Batch erase
Erases the entire memory contents.
Batch blank check
Checks the deletion status of the entire memory.
High-speed write
Performs write to the flash memory based on the write start address and the number of data
to be written (number of bytes).
Continuous write
Performs continuous write based on the information input with high-speed write operation.
Status
Used to confirm the current operating mode and operation end.
Oscillation frequency setting
Sets the frequency of the resonator.
Erase time setting
Sets the memory erase time.
Baud rate setting
Sets the communication rate for UART mode
I2C mode setting
Sets standard/high-speed mode for I2C bus mode
Silicon signature read
Outputs the device name and memory capacity, and device block information.
8.3 Connection of Flashpro III/Flashpro IV
The connection of Flashpro III/Flashpro IV and the µPD78F0034B or 78F0034BY differs according to the
communication mode (3-wire serial I/O, UART, pseudo 3-wire serial I/O, and I2C bus). The connection for each
communication mode is shown in Figures 8-2 to 8-6, respectively.
Figure 6-2. Connection of Flashpro III/Flashpro IV in 3-Wire Serial I/O Mode
µ PD78F0034B,
µPD78F0034BY
Flashpro III/Flashpro IV
VPP
VPP
VDD
VDD0/VDD1/AVDD
RESET
RESET
SCK
SCK3n
SO
SI3n
SI
SO3n
VSS0/VSS1/AVSS/AVREF
GND
Remark µPD78F0034B:
n = 0, 1
µPD78F0034BY: n = 0
26
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Figure 8-3. Connection of Flashpro III in 3-Wire Serial I/O Mode (Using Handshake)
Flashpro III/Flashpro IV
VPP
VDD
µ PD78F0034B,
µ PD78F0034BY
VPP
VDD0/VDD1/AVDD
RESET
RESET
SCK
SCK30
SO
SI30
SI
SO30
HS
GND
HS (P25)
VSS0/VSS1/AVSS/AVREF
Figure 8-4. Connection of Flashpro III/Flashpro IV for UART Mode
µ PD78F0034B,
µPD78F0034BY
Flashpro III/Flashpro IV
VPP
VPP
VDD
VDD0/VDD1/AVDD
RESET
RESET
SO
RxD0
SI
TxD0
GND
VSS0/VSS1/AVSS/AVREF
Figure 8-5. Connection of Flashpro III/Flashpro IV for Pseudo 3-Wire Serial I/O Mode
µ PD78F0034B,
µPD78F0034BY
Flashpro III/Flashpro IV
VPP
VPP
VDD
VDD0/VDD1/AVDD
RESET
RESET
SCK
P72
SO
P70
SI
P71
(serial clock input)
(serial data input)
(serial data output)
GND
VSS0/VSS1/AVSS/AVREF
Figure 8-6. Connection of Flashpro III/Flashpro IV for I2C Bus Mode (µPD78F0034BY only)
µ PD78F0034BY
Flashpro III/Flashpro IV
VPP
VPP
VDD
VDD0/VDD1/AVDD
RESET
RESET
SO
SCL0
SI
SDA0
VSS0/VSS1/AVSS/AVREF
GND
Data Sheet U16369EJ1V0DS
27
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
9. ELECTRICAL SPECIFICATIONS
9.1 µPD78F0034B, 78F0034B(A)
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
Conditions
VDD
VPP
Note 2
AVDD
AVREF
Output voltage
VI1
P00 to P03, P10 to P17, P20 to P25, P34 to P36,
P40 to P47, P50 to P57, P64 to P67, P70 to P75,
X1, X2, XT1, XT2, RESET
VI2
P30 to P33
V
–0.3 to +10.5
V
–0.3 to VDD +
V
–0.3 to VDD +
0.3Note 1
V
–0.3 to VDD +
N-ch open drain
VO
P10 to P17
Output current, high
IOH
Analog input pin
V
0.3Note 1
–0.3 to +6.5
–0.3 to VDD +
VAN
IOL
–0.3 to +6.5
–0.3 to +0.3
Analog input voltage
Output current, low
Unit
0.3Note 1
AVSS
Input voltage
Ratings
V
V
0.3Note 1
0.3Note 1
V
AVSS –0.3 to AVREF +
and –0.3 to VDD + 0.3Note 1
V
Per pin
–10
mA
Total for P00 to P03, P40 to P47, P50 to P57,
P64 to P67, P70 to P75
–15
mA
Total for P20 to P25, P30 to P36
–15
mA
Per pin for P00 to P03, P20 to P25, P34 to P36,
P40 to P47, P64 to P67, P70 to P75
20
mA
Per pin for P30 to P33, P50 to P57
30
mA
Total for P00 to P03, P40 to P47, P64 to P67,
50
mA
Total for P20 to P25
20
mA
Total for P30 to P36
100
mA
Total for P50 to P57
100
mA
–40 to +85
°C
–40 to +125
°C
P70 to P75
Operating ambient
TA
During normal operation
temperature
Storage
temperature
Tstg
Notes 1. 6.5 V or below
(Note 2 is explained on the following page.)
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
28
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Notes 2. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
VPP must exceed VDD 10 µs or more after VDD has reached the lower-limit value (1.8 V) of the
operating voltage range (see a in the figure below).
• When supply voltage drops
VDD must be lowered 10 µs or more after VPP falls below the lower-limit value (1.8 V) of the
operating voltage range of VDD (see b in the figure below).
VDD
1.8 V
0V
a
b
VPP
1.8 V
0V
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input
capacitance
CIN
f = 1 MHz
Unmeasured pins returned to 0 V.
15
pF
I/O
CIO
f = 1 MHz
Unmeasured pins
returned to 0 V.
P00 to P03, P20 to P25,
P34 to P36, P40 to P47,
P50 to P57, P64 to P67,
P70 to P75,
15
pF
P30 to P33
20
pF
capacitance
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
Data Sheet U16369EJ1V0DS
29
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Recommended
Circuit
Ceramic
resonator
Parameter
Oscillation
VPP
X2
C2
X1
C1
frequency
(fX)Note 1
Conditions
MIN.
TYP.
stabilization
timeNote 2
Unit
MHz
4.5 V ≤ VDD ≤ 5.5 V
1.0
12.0
3.0 V ≤ VDD < 4.5 V
1.0
8.38
1.8 V ≤ VDD < 3.0 V
1.0
5.0
After VDD reaches
Oscillation
MAX.
4
ms
MHz
oscillation voltage range
MIN.
Crystal
VPP
X2
X1
resonator
frequency
C2
X2
(fX)Note 1
C1
External
clock
Oscillation
X1
4.5 V ≤ VDD ≤ 5.5 V
1.0
12.0
3.0 V ≤ VDD < 4.5 V
1.0
8.38
1.8 V ≤ VDD < 3.0 V
1.0
5.0
Oscillation
4.0 V ≤ VDD ≤ 5.5 V
10
stabilization timeNote 2
1.8 V ≤ VDD < 4.0 V
30
X1 input
4.5 V ≤ VDD ≤ 5.5 V
1.0
12.0
frequency (fX)Note 1
3.0 V ≤ VDD < 4.5 V
1.0
8.38
1.8 V ≤ VDD < 3.0 V
1.0
5.0
X1 input
4.5 V ≤ VDD ≤ 5.5 V
38
500
high-/low-level width
3.0 V ≤ VDD < 4.5 V
50
500
(tXH, tXL)
1.8 V ≤ VDD < 3.0 V
85
500
ms
MHz
ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the system is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
30
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Crystal
resonator
Recommended Circuit
XT2
R2
C4
External
clock
XT1VPP
XT2
C3
XT1
Parameter
Conditions
Oscillation
frequency (fXT)Note 1
Oscillation
stabilization timeNote 2
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.2
2
s
4.0 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 4.0 V
10
X1 input
frequency (fXT)Note 1
32
38.5
kHz
X1 input high-/low-level
width (tXTH, tXTL)
12
15
µs
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillator voltage MIN.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor to the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing power
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
Data Sheet U16369EJ1V0DS
31
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Output current,
Symbol
MIN.
TYP.
MAX.
Unit
mA
IOH
Per pin
–1
All pins
–15
mA
IOL
Per pin for P00 to P03, P20 to P25, P34 to P36,
10
mA
Per pin for P30 to P33, P50 to P57
15
mA
Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75
20
mA
Total for P20 to P25
10
mA
Total for P30 to P36
70
mA
high
Output current,
Conditions
low
P40 to P47, P64 to P67, P70 to P75
Total for P50 to P57
Input voltage,
70
mA
P10 to P17, P21, P24, P35,
2.7 V ≤ VDD ≤ 5.5 V
0.7VDD
VDD
V
P40 to P47, P50 to P57,
1.8 V ≤ VDD < 2.7 V
0.8VDD
VDD
V
P00 to P03, P20, P22, P23, P25,
2.7 V ≤ VDD ≤ 5.5 V
0.8VDD
VDD
V
P34, P36, P70 to P73, RESET
1.8 V ≤ VDD < 2.7 V
0.85VDD
VDD
V
P30 to P33
2.7 V ≤ VDD ≤ 5.5 V
0.7VDD
5.5
V
(N-ch open-drain)
1.8 V ≤ VDD < 2.7 V
0.8VDD
5.5
V
VIH4
X1, X2
2.7 V ≤ VDD ≤ 5.5 V
VDD – 0.5
VDD
V
1.8 V ≤ VDD < 2.7 V
VDD – 0.2
VDD
V
VIH5
XT1, XT2
4.0 V ≤ VDD ≤ 5.5 V
0.8VDD
VDD
V
1.8 V ≤ VDD < 4.0 V
0.9VDD
VDD
V
P10 to P17, P21, P24, P35,
2.7 V ≤ VDD ≤ 5.5 V
0
0.3VDD
V
P40 to P47, P50 to P57,
1.8 V ≤ VDD < 2.7 V
0
0.2VDD
V
2.7 V ≤ VDD ≤ 5.5 V
0
0.2VDD
V
P34, P36, P70 to P73, RESET
1.8 V ≤ VDD < 2.7 V
0
0.15VDD
V
P30 to P33
4.0 V ≤ VDD ≤ 5.5 V
0
0.3VDD
V
2.7 V ≤ VDD < 4.0 V
0
0.2VDD
V
VIH1
high
P64 to P67, P74, P75
VIH2
VIH3
Input voltage,
VIL1
low
P64 to P67, P74, P75
VIL2
VIL3
VIL4
P00 to P03, P20, P22, P23, P25,
X1, X2
1.8 V ≤ VDD < 2.7 V
0
0.1VDD
V
2.7 V ≤ VDD ≤ 5.5 V
0
0.4
V
1.8 V ≤ VDD < 2.7 V
0
0.2
V
4.0 V ≤ VDD ≤ 5.5 V
0
0.2VDD
V
VIL5
XT1, XT2
0
0.1VDD
V
VOH1
4.0 V ≤ VDD ≤ 5.5 V, IOH = –1 mA
VDD – 1.0
VDD
V
1.8 V ≤ VDD < 4.0 V, IOH = –100 µA
VDD – 0.5
VDD
V
1.8 V ≤ VDD < 4.0 V
Output voltage,
high
Output voltage,
VOL1
low
P30 to P33
4.0 V ≤ VDD ≤ 5.5 V,
P50 to P57
IOL = 15 mA
P00 to P03, P20 to P25, P34 to P36, 4.0 V ≤ VDD ≤ 5.5 V,
P40 to P47, P64 to P67, P70 to P75
VOL2
Remark
32
0.4
2.0
V
2.0
V
0.4
V
0.5
V
IOL = 1.6 mA
IOL = 400 µA
Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Input leakage
current, high
Symbol
ILIH1
Conditions
VIN = VDD
ILIH2
Input leakage
current, low
MIN.
TYP.
MAX.
Unit
P00 to P03, P10 to P17, P20 to P25,
P34 to P36, P40 to P47, P50 to P57,
P64 to P67, P70 to P75,
RESET
3
µA
X1, X2, XT1, XT2
20
µA
ILIH3
VIN = 5.5 V
P30 to P33
3
µA
ILIL1
VIN = 0 V
P00 to P03, P10 to P17, P20 to P25,
P34 to P36, P40 to P47, P50 to P57,
P64 to P67, P70 to P75,
RESET
–3
µA
ILIL2
X1, X2, XT1, XT2
–20
µA
ILIL3
P30 to P33
–3
µA
Output leakage
current, high
ILOH
VOUT = VDD
3
µA
Output leakage
current, low
ILOL
VOUT = 0 V
–3
µA
Software pullup resistor
R
VIN = 0 V,
P00 to P03, P20 to P25, P34 to P36, P40 to P47,
P50 to P57, P64 to P67, P70 to P75
90
kΩ
15
30
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
Data Sheet U16369EJ1V0DS
33
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
Power supply
currentNote 1
IDD1Note 2
±10%Note 3
12.0 MHz
VDD = 5.0 V
crystal oscillation
operating mode
MIN.
When A/D converter is
stopped
When A/D converter is
operatingNote 7
MAX.
Unit
16
32
mA
17
34
mA
8.38 MHz
VDD = 5.0 V ±10%Note 3
crystal oscillation
When A/D converter is
stopped
10.5
21
mA
operating mode
When A/D converter is
operatingNote 7
11.5
23
mA
7
14
mA
When A/D converter is
operatingNote 7
8
16
mA
5.00 MHz
VDD = 3.0 V ±10%Note 3
crystal oscillation
When A/D converter is
stopped
4.5
9
mA
operating mode
When A/D converter is
operatingNote 7
5.5
11
mA
When A/D converter is
stopped
1
2
mA
When A/D converter is
operatingNote 7
2
6
mA
12.0 MHz
VDD = 5.0 V ±10%Note 3
crystal oscillation
When peripheral functions
are stopped
2
4
mA
HALT mode
When peripheral functions
are operating
8
mA
8.38 MHz
VDD = 5.0 V ±10%Note 3
crystal oscillation
When peripheral functions
are stopped
2.4
mA
HALT mode
When peripheral functions
are operating
5
mA
1.2
mA
2.4
mA
0.8
mA
1.7
mA
0.4
mA
1.1
mA
VDD = 3.0 V + 10%Notes 3, 6 When A/D converter is
stopped
VDD = 2.0 V ±10%Note 4
IDD2
TYP.
VDD = 3.0 V + 10%Notes 3, 6 When peripheral functions
are stopped
1.2
0.6
When peripheral functions
are operating
5.00 MHz
VDD = 3.0 V ±10%Note 3
crystal oscillation
When peripheral functions
are stopped
HALT mode
When peripheral functions
are operating
VDD = 2.0 V ±10%Note 4
When peripheral functions
are stopped
0.4
0.2
When peripheral functions
are operating
IDD3
32.768 kHz crystal oscillation
VDD = 5.0 V ±10%
115
230
µA
modeNote 5
VDD = 3.0 V ±10%
95
190
µA
VDD = 2.0 V ±10%
75
150
µA
VDD = 5.0 V ±10%
30
60
µA
VDD = 3.0 V ±10%
6
18
µA
VDD = 2.0 V ±10%
2
10
µA
XT1 = VDD STOP mode
VDD = 5.0 V ±10%
0.1
30
µA
When feedback resistor is not used
VDD = 3.0 V ±10%
0.05
10
µA
VDD = 2.0 V ±10%
0.05
10
µA
operating
IDD4
32.768 kHz crystal oscillation
HALT
IDD5
34
modeNote 5
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Notes 1. Total current through the internal power supply (VDD0, VDD1) (except the current through pull-up resistors
of ports).
2. IDD1 includes the peripheral operation current.
3. When the processor clock control register (PCC) is set to 00H.
4. When PCC is set to 02H.
5. When main system clock operation is stopped.
6. The values show the specifications when VDD = 3.0 to 3.3 V. The value in the TYP. column show the
specifications when VDD = 3.0 V.
7. Includes the current through the AVDD pin.
Data Sheet U16369EJ1V0DS
35
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
AC Characteristics
(1) Basic Operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Cycle time
TCY
(Min. instruction
Conditions
MIN.
TYP.
MAX.
Unit
Operating with
4.5 V ≤ VDD ≤ 5.5 V
0.166
16
µs
main system clock
3.0 V ≤ VDD ≤ 4.5 V
0.238
16
µs
2.7 V ≤ VDD ≤ 3.0 V
0.4
16
µs
1.8 V ≤ VDD ≤ 2.7 V
1.6
16
µs
125
µs
execution time)
Operating with subsystem clock
103.9Note 1
122
µs
3.0 V ≤ VDD ≤ 5.5 V
2/fsam+0.1Note 2
high-/low-level
2.7 V ≤ VDD < 3.0 V
2/fsam+0.2Note 2
µs
width
1.8 V ≤ VDD < 2.7 V
2/fsam+0.5Note 2
µs
2.7 V ≤ VDD ≤ 5.5 V
0
4
MHz
1.8 V ≤ VDD < 2.7 V
0
275
kHz
2.7 V ≤ VDD ≤ 5.5 V
100
ns
1.8 V ≤ VDD < 2.7 V
1.8
ns
TI00, TI01 input
TI50, TI51 input
tTIH0, tTIL0
fTI5
frequency
TI50, TI51 input
tTIH5, tTIL5
high-/low-level
width
Interrupt request
tINTH, tINTL
input high-/lowlevel width
RESET
tRSL
low-level width
INTP0 to INTP3,
2.7 V ≤ VDD ≤ 5.5 V
1
µs
P40 to P47
1.8 V ≤ VDD < 2.7 V
2
µs
2.7 V ≤ VDD ≤ 5.5 V
10
µs
1.8 V ≤ VDD < 2.7 V
20
µs
Notes 1. Value when the external clock is used. When a crystal resonator is used, it is 114 µs (MIN.).
2. Selection of fsam = fX, fX/4, fX/64 is possible using bits 0 and 1 (PRM00, PRM01) of prescaler mode
register 0 (PRM0). However, if the TI00 valid edge is selected as the count clock, the value becomes
fsam = fX/8.
36
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
TCY vs. VDD (main system clock operation)
16.0
Cycle time TCY [ µ S]
10.0
5.0
Operation
guaranteed
range
2.0
1.6
1.0
0.4
0.238
0.166
0.1
0
1.0
2.0
1.8
3.0
2.7
4.0
4.5
5.0 5.5 6.0
Supply voltage VDD [V]
Data Sheet U16369EJ1V0DS
37
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(2) Read/write operation (TA = –40 to +85°C, VDD = 4.0 to 5.5 V)
Parameter
Symbol
Conditions
(1/3)
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.3tCY
ns
Address setup time
tADS
20
ns
Address hold time
tADH
6
ns
Input time from address to data
tADD1
(2 + 2n)tCY – 54
ns
tADD2
(3 + 2n)tCY – 60
ns
100
ns
Output time from RD↓ to address
tRDAD
0
Input time from RD↓ to data
tRDD1
(2 + 2n)tCY – 87
ns
tRDD2
(3 + 2n)tCY – 93
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 33
ns
tRDL2
(2.5 + 2n)tCY – 33
ns
Input time from RD↓ to WAIT↓
Input time from WR↓ to WAIT↓
tRDWT1
tCY – 43
ns
tRDWT2
tCY – 43
ns
tWRWT
tCY – 25
ns
(2 + 2n)tCY
ns
WAIT low-level width
tWTL
(0.5 + n)tCY + 10
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
6
ns
WR low-level width
tWRL1
(1.5 + 2n)tCY – 15
ns
Delay time from ASTB↓ to RD↓
tASTRD
6
ns
Delay time from ASTB↓ to WR↓
tASTWR
2tCY – 15
ns
Delay time from RD↑ to ASTB↑ in
external fetch
tRDAST
0.8tCY – 15
1.2tCY
ns
Hold time from RD↑ to address in
tRDADH
0.8tCY – 15
1.2tCY + 30
ns
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
10
60
ns
Hold time from WR↑ to address
tWRADH
0.8tCY – 15
1.2tCY + 30
ns
Delay time from WAIT↑ to RD↑
tWTRD
0.8tCY
2.5tCY + 25
ns
Delay time from WAIT↑ to WR↑
tWTWR
0.8tCY
2.5tCY + 25
ns
external fetch
ns
Caution TCY can only be used when the MIN. value is 0.238 µ s.
Remarks 1. tCY = TCY/4
2. n indicates the number of waits.
3. CL = 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB
pins.)
38
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(2) Read/write operation (TA = –40 to +85°C, VDD = 2.7 to 4.0 V)
Parameter
Symbol
Conditions
(2/3)
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.3tCY
ns
Address setup time
tADS
30
ns
Address hold time
tADH
10
ns
Input time from address to data
tADD1
(2 + 2n)tCY – 108
ns
tADD2
(3 + 2n)tCY – 120
ns
200
ns
Output time from RD↓ to address
tRDAD
0
Input time from RD↓ to data
tRDD1
(2 + 2n)tCY – 148
ns
tRDD2
(3 + 2n)tCY – 162
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 40
ns
tRDL2
(2.5 + 2n)tCY – 40
ns
Input time from RD↓ to WAIT↓
Input time from WR↓ to WAIT↓
tRDWT1
tCY – 75
ns
tRDWT2
tCY – 60
ns
tWRWT
tCY – 50
ns
(2 + 2n)tCY
ns
WAIT low-level width
tWTL
(0.5 + 2n)tCY + 10
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
10
ns
WR low-level width
tWRL1
(1.5 + 2n)tCY – 30
ns
Delay time from ASTB↓ to RD↓
tASTRD
10
ns
Delay time from ASTB↓ to WR↓
tASTWR
2tCY – 30
ns
Delay time from RD↑ to ASTB↑ in
external fetch
tRDAST
0.8tCY – 30
1.2tCY
ns
Hold time from RD↑ to address in
tRDADH
0.8tCY – 30
1.2tCY + 60
ns
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
20
120
ns
Hold time from WR↑ to address
tWRADH
0.8tCY – 30
1.2tCY + 60
ns
Delay time from WAIT↑ to RD↑
tWTRD
0.5tCY
2.5tCY + 50
ns
Delay time from WAIT↑ to WR↑
tWTWR
0.5tCY
2.5tCY + 50
ns
external fetch
ns
Caution TCY can only be used when the MIN. value is 0.4 µs.
Remarks 1. tCY = TCY/4
2. n indicates the number of waits.
3. CL = 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB
pins.)
Data Sheet U16369EJ1V0DS
39
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(2) Read/write operation (TA = –40 to +85°C, VDD = 1.8 to 2.7 V)
Parameter
Symbol
Conditions
(3/3)
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.3tCY
ns
Address setup time
tADS
120
ns
Address hold time
tADH
20
ns
Input time from address to data
tADD1
(2 + 2n)tCY – 233
ns
tADD2
(3 + 2n)tCY – 240
ns
400
ns
Output time from RD↓ to address
tRDAD
0
Input time from RD↓ to data
tRDD1
(2 + 2n)tCY – 325
ns
tRDD2
(3 + 2n)tCY – 332
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 92
ns
tRDL2
(2.5 + 2n)tCY – 92
ns
Input time from RD↓ to WAIT↓
Input time from WR↓ to WAIT↓
tRDWT1
tCY – 350
ns
tRDWT2
tCY – 132
ns
tWRWT
tCY – 100
ns
(2 + 2n)tCY
ns
WAIT low-level width
tWTL
(0.5 + 2n)tCY + 10
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
20
ns
WR low-level width
tWRL1
(1.5 + 2n)tCY – 60
ns
Delay time from ASTB↓ to RD↓
tASTRD
20
ns
Delay time from ASTB↓ to WR↓
tASTWR
2tCY – 60
ns
Delay time from RD↑ to ASTB↑ in
external fetch
tRDAST
0.8tCY – 60
1.2tCY
ns
Hold time from RD↑ to address in
tRDADH
0.8tCY – 60
1.2tCY + 120
ns
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
40
240
ns
Hold time from WR↑ to address
tWRADH
0.8tCY – 60
1.2tCY + 120
ns
Delay time from WAIT↑ to RD↑
tWTRD
0.5tCY
2.5tCY + 100
ns
Delay time from WAIT↑ to WR↑
tWTWR
0.5tCY
2.5tCY + 100
ns
external fetch
ns
Caution TCY can only be used when the MIN. value is 1.6 µs.
Remarks 1. tCY = TCY/4
2. n indicates the number of waits.
3. CL = 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB
pins.)
40
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(3) Serial Interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(a) 3-wire serial I/O mode (SCK3n... Internal clock output)
Parameter
SCK3n
Symbol
tKCY1
cycle time
SCK3n high-/
tKH1, tKL1
low-level width
SI3n setup time
tSIK1
(to SCK3n↑)
SI3n hold time
tKSI1
(from SCK3n↑)
Delay time from
tKSO1
Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
666
ns
3.0 V ≤ VDD < 4.5 V
954
ns
2.7 V ≤ VDD < 3.0 V
1600
ns
1.8 V ≤ VDD < 2.7 V
3200
ns
3.0 V ≤ VDD ≤ 5.5 V
tKCY1/2 – 50
ns
1.8 V ≤ VDD < 3.0 V
tKCY1/2 – 100
ns
3.0 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 3.0 V
150
ns
1.8 V ≤ VDD < 2.7 V
300
ns
4.5 V ≤ VDD ≤ 5.5 V
300
ns
1.8 V ≤ VDD < 4.5 V
400
ns
C = 100 pF
Note
SCK3n↓ to SO3n
4.5 V ≤ VDD ≤ 5.5 V
200
ns
1.8 V ≤ VDD < 4.5 V
300
ns
MAX.
Unit
output
Note C is the load capacitance of the SCK3n and SO3n output lines.
(b) 3-wire serial I/O mode (SCK3n... External clock input)
Parameter
SCK3n
Symbol
tKCY2
cycle time
SCK3n high-/
tKH2, tKL2
low-level width
SI3n setup time
Conditions
MIN.
TYP.
4.5 V ≤ VDD ≤ 5.5 V
666
ns
3.0 V ≤ VDD < 4.5 V
800
ns
2.7 V ≤ VDD < 3.0 V
1600
ns
1.8 V ≤ VDD < 2.7 V
3200
ns
4.5 V ≤ VDD ≤ 5.5 V
333
ns
3.0 V ≤ VDD < 4.5 V
400
ns
2.7 V ≤ VDD < 3.0 V
800
ns
1.8 V ≤ VDD < 2.7 V
1600
ns
100
ns
4.5 V ≤ VDD ≤ 5.5 V
300
ns
1.8 V ≤ VDD < 4.5 V
400
ns
tSIK2
(to SCK3n↑)
SI3n hold time
tKSI2
(from SCK3n↑)
Delay time from
SCK3n↓ to SO3n
tKSO2
C = 100 pF
Note
4.5 V ≤ VDD ≤ 5.5 V
200
ns
1.8 V ≤ VDD < 4.5 V
300
ns
output
Note C is the load capacitance of the SO3n output line.
Remark n = 0, 1
Data Sheet U16369EJ1V0DS
41
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(c) UART mode (dedicated baud-rate generator output)
Parameter
Symbol
Transfer rate
Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
187500
bps
3.0 V ≤ VDD < 4.5 V
131031
bps
2.7 V ≤ VDD < 3.0 V
78125
bps
1.8 V ≤ VDD < 2.7 V
39063
bps
MAX.
Unit
(d) UART mode (external clock input)
Parameter
ASCK0 cycle time
ASCK0 high-/low-level width
Symbol
tKCY3
Conditions
MIN.
TYP.
4.0 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.0 V
1600
ns
1.8 V ≤ VDD < 2.7 V
3200
ns
tKH3,
4.0 V ≤ VDD ≤ 5.5 V
400
ns
tKL3
2.7 V ≤ VDD < 4.0 V
800
ns
1.8 V ≤ VDD < 2.7 V
1600
ns
Transfer rate
4.0 V ≤ VDD ≤ 5.5 V
39063
bps
2.7 V ≤ VDD < 4.0 V
19531
bps
1.8 V ≤ VDD < 2.7 V
9766
bps
MAX.
Unit
(e) UART mode (infrared data transfer mode)
Parameter
Symbol
Conditions
MIN.
Transfer rate
4.0 V ≤ VDD ≤ 5.5 V
131031
bps
Allowable bit rate error
4.0 V ≤ VDD ≤ 5.5 V
±0.87
%
Output pulse width
4.0 V ≤ VDD ≤ 5.5 V
1.2
0.24/fbrNote
µs
Input pulse width
4.0 V ≤ VDD ≤ 5.5 V
4/fX
Note fbr: Specified baud rate
42
Data Sheet U16369EJ1V0DS
µs
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
10
10
10
bit
4.0 V ≤ AVREF ≤ 5.5 V
±0.2
±0.4
%FSR
2.7 V ≤ AVREF < 4.0 V
±0.3
±0.6
%FSR
1.8 V ≤ AVREF < 2.7 V
±0.6
±1.2
%FSR
Resolution
Overall
errorNote
Conversion time
Zero-scale
Full-scale
tCONV
errorNotes 1, 2
errorNotes 1, 2
Integral linearity
errorNote 1
Differential linearity error
Analog input voltage
VIAN
Reference voltage
AVREF
Resistance between AVREF and AVSS
RREF
4.5 V ≤ AVDD ≤ 5.5 V
12
96
µs
4.0 V ≤ AVDD < 4.5 V
14
96
µs
2.7 V ≤ AVDD < 4.0 V
17
96
µs
1.8 V ≤ AVDD < 2.7 V
28
96
µs
4.0 V ≤ AVREF ≤ 5.5 V
±0.4
%FSR
2.7 V ≤ AVREF < 4.0 V
±0.6
%FSR
1.8 V ≤ AVREF < 2.7 V
±1.2
%FSR
4.0 V ≤ AVREF ≤ 5.5 V
±0.4
%FSR
2.7 V ≤ AVREF < 4.0 V
±0.6
%FSR
1.8 V ≤ AVREF < 2.7 V
±1.2
%FSR
4.0 V ≤ AVREF ≤ 5.5 V
±2.5
LSB
2.7 V ≤ AVREF < 4.0 V
±4.5
LSB
1.8 V ≤ AVREF < 2.7 V
±8.5
LSB
4.0 V ≤ AVREF ≤ 5.5 V
±1.5
LSB
2.7 V ≤ AVREF ≤ 4.0 V
±2.0
LSB
1.8 V ≤ AVREF < 2.7 V
±3.5
LSB
0
AVREF
V
1.8
AVDD
V
During A/D conversion operation
20
40
kΩ
Notes 1. Excluding quantization error (±1/2 LSB).
2. Indicated as a ratio to the full-scale value (%FSR).
Remark When the µPD78F0034B is used as an 8-bit resolution A/D converter, the specifications are the same
as for the µPD780024A Subseries A/D converter.
Data Sheet U16369EJ1V0DS
43
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Remark The impedance of the analog input pins is shown below.
[Equivalent circuit]
R1
R2
ANIn
(n = 0 to 3)
C1
C2
C3
[Parameter value]
(TYP.)
AVDD
R1
R2
C1
C2
C3
2.7 V
12 kΩ
8.0 kΩ
3.0 pF
3.0 pF
2.0 pF
4.5 V
4 kΩ
2.7 kΩ
3.0 pF
1.4 pF
2.0 pF
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Data retention supply voltage
VDDDR
Data retention supply current
IDDDR
Release signal set time
tSREL
Oscillation stabilization wait time
Note
tWAIT
Conditions
TYP.
1.6
Subsystem clock stop (XT1 = VDD)
and feed-back resistor disconnected
0.1
MAX.
Unit
5.5
V
30
µA
µs
0
Release by RESET
217/fX
s
Release by interrupt request
Note
s
Selection of 212/fX and 214/fX to 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
44
MIN.
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Flash Memory Programming Characteristics (TA = +10 to +40°C, VDD = 1.8 to 5.5 V, VSS = AVSS = 0 V)
(1) Write erase characteristics
Parameter
Symbol
Operating frequency
fX
VPP supply voltage
VPP2
VDD supply current
IDD
VPP supply current
Step erase time
Overall erase time
Writeback time
IPP
Note 1
Tera
Cwb
Number of erases/writebacks
Cerwb
Note 5
Number of rewrites per chip
Note 7
MAX.
Unit
1.0
10.0
MHz
3.0 V ≤ VDD < 4.5 V
1.0
8.38
MHz
1.8 V ≤ VDD < 3.0 V
1.0
1.25
MHz
During flash memory programming
9.7
10.3
V
VDD = 5.0 V±10%
30
mA
8.38 MHz crystal VDD = 5.0 V±10%
24
mA
oscillation
operating mode
17
mA
100
mA
When
10 MHz crystal
VPP = VPP2 oscillation
operating mode
10.0
VDD = 3.0 V±10%
When VPP = VPP2
0.199
0.2
0.201
s
20
s/chip
49.4
50
50.6
ms
60
Times
16
Times
52
µs
520
µs
20
Times
When step erase time = 0.2 s
When writeback time = 50 ms
Twr
Note 6
TYP.
4.5 V ≤ VDD ≤ 5.5 V
Twb
Number of writebacks per
Note 4
writeback command
Overall write time per word
MIN.
Ter
Note 2
Note 3
Step write time
Conditions
48
Twrw
When step write time = 50 µs (1 word = 1 byte)
Cerwb
1 erase + 1 write after erase = 1 rewrite
50
48
Notes 1.
2.
3.
4.
The recommended setting value of the step erase time is 0.2 s.
The prewrite time before erasure and the erase verify time (writeback time) are not included.
The recommended setting value of the writeback time is 50 ms.
Writeback is executed once by the issuance of the writeback command. Therefore, the number of retries
must be the maximum value minus the number of commands issued.
5. The recommended setting value of the step write time is 50 µs.
6. The actual write time per word is 100 µs longer. The internal verify time during or after a write is not
included.
7. When a product is first written after shipment, "erase → write" and "write only" are both taken as one
rewrite.
Example:
P: Write, E: Erase
Shipped product
→P→E→P→E→P: 3 rewrites
Shipped product →E→P→E→P→E→P: 3 rewrites
(2) Serial write operation characteristics
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VPP set time
tPSRON
VPP high voltage
1.0
µs
Set time from VDD↑ to VPP↑
tDRPSR
VPP high voltage
10
µs
Set time from VPP↑ to RESET↑
tPSRRF
VPP high voltage
1.0
µs
VPP count start time from RESET↑
tRFCF
1.0
µs
Count execution time
tCOUNT
VPP counter high-level width
tCH
8.0
µs
VPP counter low-level width
tCL
8.0
µs
VPP counter noise elimination width
tNFW
2.0
40
Data Sheet U16369EJ1V0DS
ms
ns
45
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
9.2 µ PD78F0034BY, 78F0034BY(A)
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
Conditions
VDD
VPP
Note 2
AVDD
AVREF
VI1
Unit
–0.3 to +6.5
V
–0.3 to +10.5
V
–0.3 to VDD +
0.3Note 1
V
–0.3 to VDD +
0.3Note 1
V
AVSS
Input voltage
Ratings
–0.3 to +0.3
P00 to P03, P10 to P17, P20 to P25, P34 to P36,
P40 to P47, P50 to P57, P64 to P67, P70 to P75,
–0.3 to VDD +
V
0.3Note 1
V
X1, X2, XT1, XT2, RESET
VI2
Output voltage
P30 to P33
N-ch open drain
VO
–0.3 to +6.5
–0.3 to VDD +
V
0.3Note 1
0.3Note 1
V
Analog input voltage
VAN
P10 to P17
Output current, high
IOH
Per pin
–10
mA
Total for P00 to P03, P40 to P47, P50 to P57,
–15
mA
Total for P20 to P25, P30 to P36
–15
mA
Per pin for P00 to P03, P20 to P25, P34 to P36,
P40 to P47, P64 to P67, P70 to P75
20
mA
Per pin for P30 to P33, P50 to P57
30
mA
Total for P00 to P03, P40 to P47, P64 to P67,
P70 to P75
50
mA
Total for P20 to P25
20
mA
Total for P30 to P36
100
mA
Total for P50 to P57
100
mA
–40 to +85
°C
–40 to +125
°C
Analog input pin
AVSS –0.3 to AVREF +
and –0.3 to VDD + 0.3Note 1
V
P64 to P67, P70 to P75
Output current, low
Operating ambient
IOL
TA
During normal operation
temperature
Storage
temperature
Tstg
Notes 1. 6.5 V or below
(Note 2 is explained on the following page.)
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
46
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Notes 2. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
VPP must exceed VDD 10 µs or more after VDD has reached the lower-limit value (1.8 V) of the
operating voltage range (see a in the figure below).
• When supply voltage drops
VDD must be lowered 10 µs or more after VPP falls below the lower-limit value (1.8 V) of the
operating voltage range of VDD (see b in the figure below).
VDD
1.8 V
0V
a
b
VPP
1.8 V
0V
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input
capacitance
CIN
f = 1 MHz
Unmeasured pins returned to 0 V.
15
pF
I/O
CIO
f = 1 MHz
Unmeasured pins
returned to 0 V.
P00 to P03, P20 to P25,
P34 to P36, P40 to P47,
P50 to P57, P64 to P67,
P70 to P75,
15
pF
P30 to P33
20
pF
capacitance
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
Data Sheet U16369EJ1V0DS
47
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Ceramic
resonator
Recommended
Circuit
Parameter
Conditions
Oscillation
VPP
X2
X1
R1
C2
C1
frequency
(fX)Note 1
Oscillation
MIN.
TYP.
stabilization time
Unit
MHz
4.0 V ≤ VDD ≤ 5.5 V
1.0
8.38
1.8 V ≤ VDD < 4.0 V
1.0
5.0
After VDD reaches
Note 2
MAX.
4
ms
MHz
oscillation voltage range
MIN.
Crystal
VPP
X2
X1
resonator
C2
C1
Oscillation
4.0 V ≤ VDD ≤ 5.5 V
1.0
8.38
frequency (fX)Note 1
1.8 V ≤ VDD < 4.0 V
1.0
5.0
Oscillation
4.0 V ≤ VDD ≤ 5.5 V
stabilization
External
clock
timeNote 2
X1 input
X2
X1
10
1.8 V ≤ VDD < 4.0 V
30
4.0 V ≤ VDD ≤ 5.5 V
1.0
8.38
1.8 V ≤ VDD < 4.0 V
1.0
5.0
X1 input
4.0 V ≤ VDD ≤ 5.5 V
50
500
high-/low-level width
1.8 V ≤ VDD < 4.0 V
85
500
frequency
(fX)Note 1
ms
MHz
ns
(tXH, tXL)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the system is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacture for evaluation.
48
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Crystal
resonator
Recommended Circuit
XT2
R2
C4
External
clock
XT1VPP
XT2
C3
XT1
Parameter
Conditions
Oscillation
frequency (fXT)Note 1
Oscillation
stabilization timeNote 2
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.2
2
s
4.0 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 4.0 V
10
X1 input
frequency (fXT)Note 1
32
38.5
kHz
X1 input high-/low-level
width (tXTH, tXTL)
12
15
µs
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillator voltage MIN.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor to the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing power
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
Data Sheet U16369EJ1V0DS
49
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Output current,
Symbol
MIN.
TYP.
MAX.
Unit
mA
IOH
Per pin
–1
All pins
–15
mA
IOL
Per pin for P00 to P03, P20 to P25, P34 to P36,
10
mA
15
mA
high
Output current,
Conditions
low
P40 to P47, P64 to P67, P70 to P75
Per pin for P30 to P33, P50 to P57
Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75
20
mA
Total for P20 to P25
10
mA
Total for P30 to P36
70
mA
Total for P50 to P57
Input voltage,
VIH1
high
70
mA
P10 to P17, P21, P24, P35,
2.7 V ≤ VDD ≤ 5.5 V
0.7VDD
VDD
V
P40 to P47, P50 to P57,
1.8 V ≤ VDD < 2.7 V
0.8VDD
VDD
V
P00 to P03, P20, P22, P23, P25,
2.7 V ≤ VDD ≤ 5.5 V
0.8VDD
VDD
V
P34, P36, P70 to P73, RESET
1.8 V ≤ VDD < 2.7 V
0.85VDD
VDD
V
P30 to P33
2.7 V ≤ VDD ≤ 5.5 V
0.7VDD
5.5
V
(N-ch open-drain)
1.8 V ≤ VDD < 2.7 V
0.8VDD
5.5
V
X1, X2
2.7 V ≤ VDD ≤ 5.5 V
VDD – 0.5
VDD
V
1.8 V ≤ VDD < 2.7 V
VDD – 0.2
VDD
V
4.0 V ≤ VDD ≤ 5.5 V
0.8VDD
VDD
V
1.8 V ≤ VDD < 4.0 V
0.9VDD
VDD
V
P10 to P17, P21, P24, P35,
2.7 V ≤ VDD ≤ 5.5 V
0
0.3VDD
V
P40 to P47, P50 to P57,
1.8 V ≤ VDD < 2.7 V
0
0.2VDD
V
2.7 V ≤ VDD ≤ 5.5 V
0
0.2VDD
V
P34, P36, P70 to P73, RESET
1.8 V ≤ VDD < 2.7 V
0
0.15VDD
V
P30 to P33
4.0 V ≤ VDD ≤ 5.5 V
0
0.3VDD
V
2.7 V ≤ VDD < 4.0 V
0
0.2VDD
V
1.8 V ≤ VDD < 2.7 V
0
0.1VDD
V
2.7 V ≤ VDD ≤ 5.5 V
0
0.4
V
1.8 V ≤ VDD < 2.7 V
0
0.2
V
4.0 V ≤ VDD ≤ 5.5 V
0
0.2VDD
V
P64 to P67, P74, P75
VIH2
VIH3
VIH4
VIH5
Input voltage,
VIL1
low
XT1, XT2
P64 to P67, P74, P75
VIL2
VIL3
VIL4
P00 to P03, P20, P22, P23, P25,
X1, X2
VIL5
XT1, XT2
0
0.1VDD
V
VOH1
4.0 V ≤ VDD ≤ 5.5 V, IOH = –1 mA
VDD – 1.0
VDD
V
1.8 V ≤ V DD < 4.0 V, IOH = –100 µA
VDD – 0.5
VDD
V
1.8 V ≤ VDD < 4.0 V
Output voltage,
high
Output voltage,
VOL1
low
P30 to P33
4.0 V ≤ VDD ≤ 5.5 V,
P50 to P57
IOL = 15 mA
P00 to P03, P20 to P25, P34 to P36, 4.0 V ≤ VDD ≤ 5.5 V,
P40 to P47, P64 to P67, P70 to P75
VOL2
Remark
50
0.4
2.0
V
2.0
V
0.4
V
0.5
V
IOL = 1.6 mA
IOL = 400 µA
Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Input leakage
current, high
Symbol
ILIH1
Conditions
VIN = VDD
ILIH2
Input leakage
current, low
MIN.
TYP.
MAX.
Unit
P00 to P03, P10 to P17, P20 to P25,
P34 to P36, P40 to P47, P50 to P57,
P64 to P67, P70 to P75,
RESET
3
µA
X1, X2, XT1, XT2
20
µA
ILIH3
VIN = 5.5 V
P30 to P33
3
µA
ILIL1
VIN = 0 V
P00 to P03, P10 to P17, P20 to P25,
P34 to P36, P40 to P47, P50 to P57,
P64 to P67, P70 to P75,
RESET
–3
µA
ILIL2
X1, X2, XT1, XT2
–20
µA
ILIL3
P30 to P33
–3
µA
Output leakage
current, high
ILOH
VOUT = VDD
3
µA
Output leakage
ILOL
VOUT = 0 V
–3
µA
R
VIN = 0 V,
P00 to P03, P20 to P25, P34 to P36, P40 to P47,
P50 to P57, P64 to P67, P70 to P75
90
kΩ
current, low
Software pullup resistor
15
30
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
Data Sheet U16369EJ1V0DS
51
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Power supply
currentNote 1
Symbol
Conditions
IDD1Note 2 8.38 MHz
VDD = 5.0 V ±10%Note 3
crystal oscillation
operating mode
IDD2
MIN.
TYP.
10.5
MAX.
21
Unit
mA
When A/D converter is
operatingNote 6
11.5
23
mA
5.00 MHz
VDD = 3.0 V ±10%Note 3
crystal oscillation
operating mode
When A/D converter is
stopped
4.5
9
mA
When A/D converter is
operatingNote 6
5.5
11
mA
VDD = 2.0 V ±10%Note 4
When A/D converter is
stopped
1
2
mA
When A/D converter is
operatingNote 6
2
6
mA
1.2
2.4
mA
5
mA
0.8
mA
1.7
mA
0.4
mA
1.1
mA
When A/D converter is
stopped
8.38 MHz
VDD = 5.0 V ±10%Note 3
crystal oscillation
When peripheral functions
are stopped
HALT mode
When peripheral functions
are operating
5.00 MHz
VDD = 3.0 V ±10%Note 3
crystal oscillation
HALT mode
When peripheral functions
are stopped
VDD = 2.0 V ±10%Note 4
When peripheral functions
are stopped
0.4
When peripheral functions
are operating
0.2
When peripheral functions
are operating
IDD3
IDD4
IDD5
32.768 kHz crystal oscillation
VDD = 5.0 V ±10%
Note 2
115
230
µA
operating modeNote 5
VDD = 3.0 V ±10%
Note 2
95
190
µA
VDD = 2.0 V ±10%
Note 3
75
150
µA
32.768 kHz crystal oscillation
VDD = 5.0 V ±10%
Note 2
30
60
µA
HALT modeNote 5
VDD = 3.0 V ±10%
Note 2
6
18
µA
VDD = 2.0 V ±10%
Note 3
2
10
µA
XT1 = VDD STOP mode
VDD = 5.0 V ±10%
Note 2
0.1
30
µA
When feedback resistor is not used
VDD = 3.0 V ±10%
Note 2
0.05
10
µA
VDD = 2.0 V ±10%
Note 3
0.05
10
µA
Notes 1. Total current through the internal power supply (VDD0, VDD1) (except the current through pull-up resistors
of ports).
2. IDD1 includes the peripheral operation current.
3. When the processor clock control register (PCC) is set to 00H.
4. When PCC is set to 02H.
5. When main system clock operation is stopped.
6. Includes the current through the AVDD pin.
52
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
AC Characteristics
(1) Basic Operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Cycle time
Symbol
TCY
(Min. instruction
Conditions
Operating with
main system clock
execution time)
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V
0.238
MIN.
16
µs
2.7 V ≤ VDD < 4.0 V
0.4
16
µs
1.8 V ≤ VDD < 2.7 V
1.6
16
µs
125
µs
Operating with subsystem clock
103.9Note 1
TYP.
122
4.0 V ≤ VDD ≤ 5.5 V
2/fsam+0.1Note 2
µs
high-/low-level
2.7 V ≤ VDD < 4.0 V
2/fsam+0.2Note 2
µs
width
1.8 V ≤ VDD < 2.7 V
2/fsam+0.5Note 2
µs
2.7 V ≤ VDD ≤ 5.5 V
0
4
MHz
1.8 V ≤ VDD < 2.7 V
0
275
kHz
2.7 V ≤ VDD ≤ 5.5 V
100
ns
1.8 V ≤ VDD < 2.7 V
1.8
ns
TI00, TI01 input
TI50, TI51 input
tTIH0, tTIL0
fTI5
frequency
TI50, TI51 input
tTIH5, tTIL5
high-/low-level
width
Interrupt request
tINTH, tINTL
input high-/low-
INTP0 to INTP3,
2.7 V ≤ VDD ≤ 5.5 V
1
µs
P40 to P47
1.8 V ≤ VDD < 2.7 V
2
µs
2.7 V ≤ VDD ≤ 5.5 V
10
µs
1.8 V ≤ VDD < 2.7 V
20
µs
level width
RESET
tRSL
low-level width
Notes 1. Value when the external clock is used. When a crystal resonator is used, it is 114 µs (MIN.).
2. Selection of fsam = fX, fX/4, fX/64 is possible using bits 0 and 1 (PRM00, PRM01) of prescaler mode register
0 (PRM0). However, if the TI00 valid edge is selected as the count clock, the value becomes fsam = fX/8.
Data Sheet U16369EJ1V0DS
53
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
TCY vs. VDD (main system clock operation)
16.0
Cycle time TCY [ µ S]
10.0
5.0
Operation
guaranteed
range
2.0
1.6
1.0
0.4
0.238
0.1
0
1.0
2.0
1.8
3.0
4.0
2.7
Supply voltage VDD [V]
54
Data Sheet U16369EJ1V0DS
5.0 5.5 6.0
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(2) Read/write operation (TA = –40 to +85°C, VDD = 4.0 to 5.5 V)
Parameter
Symbol
Conditions
(1/3)
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.3tCY
ns
Address setup time
tADS
20
ns
Address hold time
tADH
6
ns
Input time from address to data
tADD1
(2 + 2n)tCY – 54
ns
tADD2
(3 + 2n)tCY – 60
ns
100
ns
Output time from RD↓ to address
tRDAD
0
Input time from RD↓ to data
tRDD1
(2 + 2n)tCY – 87
ns
tRDD2
(3 + 2n)tCY – 93
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 33
ns
tRDL2
(2.5 + 2n)tCY – 33
ns
Input time from RD↓ to WAIT↓
Input time from WR↓ to WAIT↓
tRDWT1
tCY – 43
ns
tRDWT2
tCY – 43
ns
tWRWT
tCY – 25
ns
(2 + 2n)tCY
ns
WAIT low-level width
tWTL
(0.5 + n)tCY + 10
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
6
ns
WR low-level width
tWRL1
(1.5 + 2n)tCY – 15
ns
Delay time from ASTB↓ to RD↓
tASTRD
6
ns
Delay time from ASTB↓ to WR↓
tASTWR
2tCY – 15
ns
Delay time from RD↑ to ASTB↑ in
external fetch
tRDAST
0.8tCY – 15
1.2tCY
ns
Hold time from RD↑ to address in
tRDADH
0.8tCY – 15
1.2tCY + 30
ns
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
10
60
ns
Hold time from WR↑ to address
tWRADH
0.8tCY – 15
1.2tCY + 30
ns
Delay time from WAIT↑ to RD↑
tWTRD
0.8tCY
2.5tCY + 25
ns
Delay time from WAIT↑ to WR↑
tWTWR
0.8tCY
2.5tCY + 25
ns
external fetch
ns
Caution TCY can only be used when the MIN. value is 0.238 µs.
Remarks 1. tCY = TCY/4
2. n indicates the number of waits.
3. CL = 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB
pins.)
Data Sheet U16369EJ1V0DS
55
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(2) Read/write operation (TA = –40 to +85°C, VDD = 2.7 to 4.0 V)
Parameter
Symbol
Conditions
(2/3)
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.3tCY
ns
Address setup time
tADS
30
ns
Address hold time
tADH
10
ns
Input time from address to data
tADD1
(2 + 2n)tCY – 108
ns
tADD2
(3 + 2n)tCY – 120
ns
200
ns
Output time from RD↓ to address
tRDAD
0
Input time from RD↓ to data
tRDD1
(2 + 2n)tCY – 148
ns
tRDD2
(3 + 2n)tCY – 162
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 40
ns
tRDL2
(2.5 + 2n)tCY – 40
ns
Input time from RD↓ to WAIT↓
Input time from WR↓ to WAIT↓
tRDWT1
tCY – 75
ns
tRDWT2
tCY – 60
ns
tWRWT
tCY – 50
ns
(2 + 2n)tCY
ns
WAIT low-level width
tWTL
(0.5 + 2n)tCY + 10
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
10
ns
WR low-level width
tWRL1
(1.5 + 2n)tCY – 30
ns
Delay time from ASTB↓ to RD↓
tASTRD
10
ns
Delay time from ASTB↓ to WR↓
tASTWR
2tCY – 30
ns
Delay time from RD↑ to ASTB↑ in
tRDAST
0.8tCY – 30
1.2tCY
ns
Hold time from RD↑ to address in
external fetch
tRDADH
0.8tCY – 30
1.2tCY + 60
ns
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
20
120
ns
Hold time from WR↑ to address
tWRADH
0.8tCY – 30
1.2tCY + 60
ns
Delay time from WAIT↑ to RD↑
tWTRD
0.5tCY
2.5tCY + 50
ns
Delay time from WAIT↑ to WR↑
tWTWR
0.5tCY
2.5tCY + 50
ns
external fetch
ns
Caution TCY can only be used when the MIN. value is 0.4 µs.
Remarks 1. tCY = TCY/4
2. n indicates the number of waits.
3. CL = 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB
pins.)
56
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(2) Read/write operation (TA = –40 to +85°C, VDD = 1.8 to 2.7 V)
Parameter
Symbol
Conditions
(3/3)
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.3tCY
ns
Address setup time
tADS
120
ns
Address hold time
tADH
20
ns
Input time from address to data
tADD1
(2 + 2n)tCY – 233
ns
tADD2
(3 + 2n)tCY – 240
ns
400
ns
Output time from RD↓ to address
tRDAD
0
Input time from RD↓ to data
tRDD1
(2 + 2n)tCY – 325
ns
tRDD2
(3 + 2n)tCY – 332
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 92
ns
tRDL2
(2.5 + 2n)tCY – 92
ns
Input time from RD↓ to WAIT↓
Input time from WR↓ to WAIT↓
tRDWT1
tCY – 350
ns
tRDWT2
tCY – 132
ns
tWRWT
tCY – 100
ns
(2 + 2n)tCY
ns
WAIT low-level width
tWTL
(0.5 + 2n)tCY + 10
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
20
ns
WR low-level width
tWRL1
(1.5 + 2n)tCY – 60
ns
Delay time from ASTB↓ to RD↓
tASTRD
20
ns
Delay time from ASTB↓ to WR↓
tASTWR
2tCY – 60
ns
Delay time from RD↑ to ASTB↑ in
tRDAST
0.8tCY – 60
1.2tCY
ns
Hold time from RD↑ to address in
external fetch
tRDADH
0.8tCY – 60
1.2tCY + 120
ns
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
40
240
ns
Hold time from WR↑ to address
tWRADH
0.8tCY – 60
1.2tCY + 120
ns
Delay time from WAIT↑ to RD↑
tWTRD
0.5tCY
2.5tCY + 100
ns
Delay time from WAIT↑ to WR↑
tWTWR
0.5tCY
2.5tCY + 100
ns
external fetch
ns
Caution TCY can only be used when the MIN. value is 1.6 µs.
Remarks 1. tCY = TCY/4
2. n indicates the number of waits.
3. CL = 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB
pins.)
Data Sheet U16369EJ1V0DS
57
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(3) Serial Interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(a) 3-wire serial I/O mode (SCK30... Internal clock output)
Parameter
SCK30
Symbol
tKCY1
cycle time
SCK30 high-/
tKH1, tKL1
low-level width
SI30 setup time
tSIK1
(to SCK30↑)
SI3n hold time
Conditions
MIN.
TYP.
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V
954
ns
2.7 V ≤ VDD < 4.0 V
1600
ns
1.8 V ≤ VDD < 2.7 V
3200
ns
4.0 V ≤ VDD ≤ 5.5 V
tKCY1/2 – 50
ns
1.8 V ≤ VDD < 4.0 V
tKCY1/2 – 100
ns
4.0 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 4.0 V
150
ns
1.8 V ≤ VDD < 2.7 V
300
ns
400
ns
tKSI1
(from SCK30↑)
Delay time from
SCK30↓ to SO30
output
tKSO1
C = 100 pF
Note
300
ns
MAX.
Unit
Note C is the load capacitance of the SCK30 and SO30 output lines.
(b) 3-wire serial I/O mode (SCK30... External clock input)
Parameter
Symbol
Conditions
MIN.
TYP.
4.0 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.0 V
1600
ns
1.8 V ≤ VDD < 2.7 V
3200
ns
4.0 V ≤ VDD ≤ 5.5 V
400
ns
2.7 V ≤ VDD < 4.0 V
800
ns
1.8 V ≤ VDD < 2.7 V
1600
ns
tSIK2
100
ns
SI30 hold time
(from SCK30↑)
tKSI2
400
ns
Delay time from
SCK30↓ to SO30
output
tKSO2
SCK30
tKCY2
cycle time
SCK30 high-/
tKH2, tKL2
low-level width
SI30 setup time
(to SCK30↑)
C = 100 pF
Note
Note C is the load capacitance of the SO30 output line.
58
Data Sheet U16369EJ1V0DS
300
ns
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(c)
UART mode (dedicated baud-rate generator output)
Parameter
Symbol
Transfer rate
(d)
Conditions
MIN.
TYP.
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V
131031
bps
2.7 V ≤ VDD < 4.0 V
78125
bps
1.8 V ≤ VDD < 2.7 V
39063
bps
MAX.
Unit
UART mode (external clock input)
Parameter
ASCK0 cycle time
ASCK0 high-/low-level width
Symbol
tKCY3
Conditions
MIN.
TYP.
4.0 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.0 V
1600
ns
1.8 V ≤ VDD < 2.7 V
3200
ns
tKH3,
4.0 V ≤ VDD ≤ 5.5 V
400
ns
tKL3
2.7 V ≤ VDD < 4.0 V
800
ns
1.8 V ≤ VDD < 2.7 V
1600
ns
Transfer rate
4.0 V ≤ VDD ≤ 5.5 V
39063
bps
2.7 V ≤ VDD < 4.0 V
19531
bps
1.8 V ≤ VDD < 2.7 V
9766
bps
MAX.
Unit
131031
bps
(e) UART mode (infrared data transfer mode)
Parameter
Transfer rate
Symbol
Conditions
MIN.
4.0 V ≤ VDD ≤ 5.5 V
Allowable bit rate error
4.0 V ≤ VDD ≤ 5.5 V
Output pulse width
4.0 V ≤ VDD ≤ 5.5 V
1.2
Input pulse width
4.0 V ≤ VDD ≤ 5.5 V
4/fX
Note
±0.87
%
0.24/fbrNote
µs
µs
fbr: Specified baud rate
Data Sheet U16369EJ1V0DS
59
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(f) I2C bus mode
Parameter
Symbol
Standard Mode
High-Speed Mode
MIN.
MAX.
MIN.
MAX.
Unit
SCL0 clock frequency
fCLK
0
100
0
400
kHz
Bus free time
(between stop and start condition)
tBUF
4.7
–
1.3
–
µs
Hold timeNote 1
tHD:STA
4.0
–
0.6
–
µs
SCL0 clock low-level width
tLOW
4.7
–
1.3
–
µs
SCL0 clock high-level width
tHIGH
4.0
–
0.6
–
µs
Start/restart condition setup time
tSU:STA
4.7
–
0.6
–
µs
Data hold time
tHD:DAT
5.0
–
–
–
µs
0Note 2
–
0Note 2
0.9Note 3
µs
250
–
100Note 4
–
ns
CBUS compatible master
I2C bus
Data setup time
tSU:DAT
SDA0 and SCL0 signal rise time
tR
–
1,000
20 + 0.1CbNote 5
300
ns
SDA0 and SCL0 signal fall time
tF
–
300
20 + 0.1CbNote 5
300
ns
Stop condition setup time
tSU:STO
4.0
–
0.6
–
µs
Spike pulse width controlled by input filter
tSP
–
–
0
50
ns
Capacitive load per each bus line
Cb
–
400
–
400
pF
Notes 1. In the start condition, the first clock pulse is generated after this hold time.
2. To fill in the undefined area of the SCL0 falling edge, it is necessary for the device to internally provide
at least 300 ns of hold time for the SDA0 signal (which is VIHmin. of the SCL0 signal).
3. If the device does not extend the SCL0 signal low hold time (tLOW), only maximum data hold time tHD:DAT
needs to be fulfilled.
4. The high-speed mode I2C bus is available in a standard mode I2C bus system. At this time, the
conditions described below must be satisfied.
• If the device does not extend the SCL0 signal low state hold time
tSU:DAT ≥ 250 ns
• If the device extends the SCL0 signal low state hold time
Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU:DAT
= 1,000 + 250 = 1,250 ns by standard mode I2C bus specification).
5. Cb: Total capacitance per one bus line (unit: pF)
60
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
10
10
10
bit
4.0 V ≤ AVREF ≤ 5.5 V
±0.2
±0.4
%FSR
2.7 V ≤ AVREF < 4.0 V
±0.3
±0.6
%FSR
1.8 V ≤ AVREF < 2.7 V
±0.6
±1.2
%FSR
Resolution
Overall
errorNote
Conversion time
Zero-scale
Full-scale
tCONV
errorNotes 1, 2
errorNotes 1, 2
Integral linearity
errorNote 1
Differential linearity error
Analog input voltage
VIAN
Reference voltage
AVREF
Resistance between AVREF and AVSS
RREF
4.5 V ≤ AVDD ≤ 5.5 V
12
96
µs
4.0 V ≤ AVDD < 4.5 V
14
96
µs
2.7 V ≤ AVDD < 4.0 V
17
96
µs
1.8 V ≤ AVDD < 2.7 V
28
96
µs
4.0 V ≤ AVREF ≤ 5.5 V
±0.4
%FSR
2.7 V ≤ AVREF < 4.0 V
±0.6
%FSR
1.8 V ≤ AVREF < 2.7 V
±1.2
%FSR
4.0 V ≤ AVREF ≤ 5.5 V
±0.4
%FSR
2.7 V ≤ AVREF < 4.0 V
±0.6
%FSR
1.8 V ≤ AVREF < 2.7 V
±1.2
%FSR
4.0 V ≤ AVREF ≤ 5.5 V
±2.5
LSB
2.7 V ≤ AVREF < 4.0 V
±4.5
LSB
1.8 V ≤ AVREF < 2.7 V
±8.5
LSB
4.0 V ≤ AVREF ≤ 5.5 V
±1.5
LSB
2.7 V ≤ AVREF ≤ 4.0 V
±2.0
LSB
1.8 V ≤ AVREF < 2.7 V
±3.5
LSB
0
AVREF
V
1.8
AVDD
V
During A/D conversion operation
20
40
kΩ
Notes 1. Excluding quantization error (±1/2 LSB).
2. Indicated as a ratio to the full-scale value (%FSR).
Remark When the µPD78F0034BY is used as an 8-bit resolution A/D converter, the specifications are the same
as for the µPD780024AY Subseries A/D converter.
Data Sheet U16369EJ1V0DS
61
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Remark The impedance of the analog input pins is shown below.
[Equivalent circuit]
R1
R2
ANIn
(n = 0 to 3)
C1
C2
C3
[Parameter value]
(TYP.)
AVDD
R1
R2
C1
C2
C3
2.7 V
12 kΩ
8.0 kΩ
3.0 pF
3.0 pF
2.0 pF
4.5 V
4 kΩ
2.7 kΩ
3.0 pF
1.4 pF
2.0 pF
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Data retention supply voltage
VDDDR
Data retention supply current
IDDDR
Release signal set time
tSREL
Oscillation stabilization wait time
Note
tWAIT
Conditions
TYP.
1.6
Subsystem clock stop (XT1 = VDD)
and feed-back resistor disconnected
0.1
MAX.
Unit
5.5
V
30
µA
µs
0
Release by RESET
217/fX
s
Release by interrupt request
Note
s
Selection of 212/fX and 214/fX to 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
62
MIN.
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Flash Memory Programming Characteristics (TA = +10 to +40°C, VDD = 1.8 to 5.5 V, VSS = AVSS = 0 V)
(1) Write erase characteristics
Parameter
Symbol
Operating frequency
fX
VPP supply voltage
VPP2
VDD supply current
IDD
VPP supply current
Step erase time
Overall erase time
Writeback time
IPP
Note 1
Tera
Cwb
Number of erases/writebacks
Cerwb
Note 5
Number of rewrites per chip
Note 7
MAX.
Unit
1.0
10.0
MHz
3.0 V ≤ VDD < 4.5 V
1.0
8.38
MHz
1.8 V ≤ VDD < 3.0 V
1.0
1.25
MHz
During flash memory programming
9.7
10.3
V
VDD = 5.0 V±10%
30
mA
8.38 MHz crystal VDD = 5.0 V±10%
24
mA
oscillation
operating mode
17
mA
100
mA
When
10 MHz crystal
VPP = VPP2 oscillation
operating mode
10.0
VDD = 3.0 V±10%
When VPP = VPP2
0.199
0.2
0.201
s
20
s/chip
49.4
50
50.6
ms
60
Times
16
Times
52
µs
520
µs
20
Times
When step erase time = 0.2 s
When writeback time = 50 ms
Twr
Note 6
TYP.
4.5 V ≤ VDD ≤ 5.5 V
Twb
Number of writebacks per
Note 4
writeback command
Overall write time per word
MIN.
Ter
Note 2
Note 3
Step write time
Conditions
48
Twrw
When step write time = 50 µs (1 word = 1 byte)
Cerwb
1 erase + 1 write after erase = 1 rewrite
50
48
Notes 1.
2.
3.
4.
The recommended setting value of the step erase time is 0.2 s.
The prewrite time before erasure and the erase verify time (writeback time) are not included.
The recommended setting value of the writeback time is 50 ms.
Writeback is executed once by the issuance of the writeback command. Therefore, the number of retries
must be the maximum value minus the number of commands issued.
5. The recommended setting value of the step write time is 50 µs.
6. The actual write time per word is 100 µs longer. The internal verify time during or after a write is not
included.
7. When a product is first written after shipment, "erase → write" and "write only" are both taken as one
rewrite.
Example:
P: Write, E: Erase
Shipped product
→P→E→P→E→P: 3 rewrites
Shipped product →E→P→E→P→E→P: 3 rewrites
(2) Serial write operation characteristics
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VPP set time
tPSRON
VPP high voltage
1.0
µs
Set time from VDD↑ to VPP↑
tDRPSR
VPP high voltage
10
µs
Set time from VPP↑ to RESET↑
tPSRRF
VPP high voltage
1.0
µs
VPP count start time from RESET↑
tRFCF
1.0
µs
Count execution time
tCOUNT
VPP counter high-level width
tCH
8.0
µs
VPP counter low-level width
tCL
8.0
µs
VPP counter noise elimination width
tNFW
2.0
40
Data Sheet U16369EJ1V0DS
ms
ns
63
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
9.3 Timing Chart
AC Timing Test Point (Excluding X1, XT1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Point of test
Clock Timing
1/fX
tXL
tXH
VIH4 (MIN.)
VIL4 (MAX.)
X1 input
1/fXT
tXTL
tXTH
VIH5 (MIN.)
VIL5 (MAX.)
XT1 input
TI Timing
tTIL0
tTIH0
TI00, TI01
1/fTI5
tTIL5
TI50, TI51
64
Data Sheet U16369EJ1V0DS
tTIH5
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Interrupt Request Input Timing
tINTL
tINTH
INTP0 to INTP3
RESET Input Timing
tRSL
RESET
Data Sheet U16369EJ1V0DS
65
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Read/Write Operation
External fetch (no wait):
A8 to A15
Higher 8-bit address
tADD1
Hi-Z
Lower 8-bit
address
AD0 to AD7
tADS
Instruction code
tRDAD
tRDD1
tADH
tRDADH
tASTH
tRDAST
ASTB
RD
tASTRD
tRDL1
tRDH
External fetch (wait insertion):
A8 to A15
Higher 8-bit address
tADD1
AD0 to AD7
Hi-Z
Lower 8-bit
address
tADS
tADH
tRDAD
Instruction code
tRDADH
tRDD1
tASTH
tRDAST
ASTB
RD
tASTRD
tRDL1
tRDH
WAIT
tRDWT1
66
tWTL
Data Sheet U16369EJ1V0DS
tWTRD
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
External data access (no wait):
A8 to A15
Higher 8-bit address
tADD2
AD0 to AD7
Hi-Z
tRDAD
tRDD2
Lower 8-bit
address
tADS
tADH
Read data
tASTH
Hi-Z
Write data
tRDH
ASTB
RD
tASTRD
tRDWD
tRDL2
tWDS
tWDH
tWRADH
tWRWD
WR
tASTWR
tWRL1
External data access (wait insertion):
A8 to A15
Higher 8-bit address
tADD2
AD0 to AD7
Lower 8-bit
address
tADS tADH
tASTH
Hi-Z
Read data
Hi-Z
Write data
tRDAD
tRDH
tRDD2
ASTB
tASTRD
RD
tRDWD
tRDL2
tWDS
tWDH
tWRWD
WR
tASTWR
tWRL1
tWRADH
WAIT
tRDWT2
tWTL
tWTRD
tWTL
tWRWT
Data Sheet U16369EJ1V0DS
tWTWR
67
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Serial Transfer Timing
3-wire serial I/O mode:
tKCYm
tKLm
tKHm
SCK3n
tSIKm
SI3n
tKSIm
Input data
tKSOm
SO3n
Output data
Remarks 1. m = 1, 2
2. µPD78F0034B and 78F0034B(A):
n = 0, 1
3. µPD78F0034BY and 78F0034BY(A): n = 0
UART mode (external clock input):
t KCY3
t KL3
t KH3
ASCK0
I2C bus mode (µPD78F0034BY only):
tLOW
tR
SCL0
tHD:DAT
tHD:STA
tHIGH
tF
tSU:STA
tHD:STA
tSP
tSU:STO
tSU:DAT
SDA0
tBUF
Stop
condition
68
Start
condition
Restart
condition
Data Sheet U16369EJ1V0DS
Stop
condition
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
Operating mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
HALT mode
Operating mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
Standby release signal
(Interrupt request)
tWAIT
Data Sheet U16369EJ1V0DS
69
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Flash Memory Write Mode Set Timing
VDD
VDD
0V
tDRPSR
tRFCF
tCH
VPPH
VPP VPPL
tCL
0V
tPSRON tPSRRF
tCOUNT
VDD
RESET (input)
0V
70
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
10. PACKAGE DRAWINGS
64-PIN PLASTIC LQFP (10x10)
A
B
48
detail of lead end
33
32
49
S
P
C
T
D
R
64
U
17
Q
16
1
L
F
G
J
H
I
M
ITEM
A
K
B
S
N
S
M
MILLIMETERS
12.0±0.2
10.0±0.2
C
10.0±0.2
D
12.0±0.2
F
1.25
G
1.25
H
0.22±0.05
I
0.08
J
0.5 (T.P.)
NOTE
K
1.0±0.2
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
L
0.5
M
0.17 +0.03
−0.07
N
0.08
P
1.4
Q
0.1±0.05
R
3° +4°
−3°
S
1.5±0.10
T
0.25
U
0.6±0.15
S64GB-50-8EU-2
Remark The package and material of ES products are the same as mass produced products.
Data Sheet U16369EJ1V0DS
71
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
64-PIN PLASTIC LQFP (14x14)
A
B
48
49
33
32
detail of lead end
S
P
C
D
T
R
64
1
L
17
16
U
Q
F
G
J
H
I
M
ITEM
K
S
N
M
S
MILLIMETERS
A
17.2±0.2
B
14.0±0.2
C
14.0±0.2
D
17.2±0.2
F
1.0
G
1.0
H
0.37 +0.08
−0.07
I
0.20
J
K
0.8 (T.P.)
NOTE
L
0.8
Each lead centerline is located within 0.20 mm of
its true position (T.P.) at maximum material condition.
M
0.17 +0.03
−0.06
N
0.10
1.6±0.2
P
1.4±0.1
Q
0.127±0.075
+4°
3° −3°
R
S
T
U
1.7 MAX.
0.25
0.886±0.15
P64GC-80-8BS
Remark The package and material of ES products are the same as mass produced products.
72
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
64-PIN PLASTIC TQFP (12x12)
A
B
48
detail of lead end
33
32
49
S
P
T
C
D
R
L
U
64
Q
17
16
1
F
G
J
H
I
M
ITEM
K
S
M
N
S
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
B
14.0±0.2
12.0±0.2
C
12.0±0.2
D
F
14.0±0.2
1.125
G
1.125
H
0.32 +0.06
−0.10
I
0.13
J
0.65 (T.P.)
K
1.0±0.2
L
0.5
M
0.17 +0.03
−0.07
N
0.10
P
1.0
Q
0.1±0.05
R
3° +4°
−3°
S
1.1±0.1
T
0.25
U
0.6±0.15
P64GK-65-9ET-3
Remark The package and material of ES products are the same as mass produced products.
Data Sheet U16369EJ1V0DS
73
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
73-PIN PLASTIC FBGA (9x9)
D
w S A
ZE
ZD
A
9
8
7
6
5
4
3
2
1
B
E
J H G F E D C B A
w S B
INDEX MARK
A
y1
A2
S
(UNIT:mm)
S
y
S
e
φb
A1
φx
M
S AB
ITEM
D
DIMENSIONS
9.00±0.10
E
9.00±0.10
w
0.20
A
1.28±0.10
A1
0.35±0.06
A2
0.93
e
0.80
b
0.50 +0.05
–0.10
x
0.08
y
0.10
y1
0.20
ZD
1.30
ZE
1.30
P73F1-80-CN3
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced
version.
74
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
11. RECOMMENDED SOLDERING CONDITIONS
The µPD78F0034B, 78F0034BY, 78F0034B(A), and 78F0034BY(A) should be soldered and mounted under
the following recommended conditions.
For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
Table 11-1. Surface Mounting Type Soldering Conditions (1/2)
(1) µPD78F0034BGB-8EU:
µPD78F0034BGB(A)-8EU:
64-pin plastic LQFP (10 x 10)
64-pin plastic LQFP (10 x 10)
µPD78F0034BYGB-8EU:
64-pin plastic LQFP (10 x 10)
µPD78F0034BYGB(A)-8EU: 64-pin plastic LQFP (10 x 10)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Two times or less,
Exposure limit: 7 daysNote (after 7 days, prebake at 125°C for 10 hours)
IR35-107-2
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Two times or less,
Exposure limit: 7 daysNote (after 7 days, prebake at 125°C for 10 hours)
VP15-107-2
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Note
–
After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
(2) µPD78F0034BGC-8BS:
µPD78F0034BGC(A)-8BS:
µPD78F0034BYGC-8BS:
64-pin plastic LQFP (14 x 14)
64-pin plastic LQFP (14 x 14)
64-pin plastic LQFP (14 x 14)
µPD78F0034BYGC(A)-8BS: 64-pin plastic LQFP (14 x 14)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Two times or less
IR35-00-2
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Two times or less
VP15-00-2
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,
Preheating temperature: 120°C max. (package surface temperature)
WS60-00-1
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
–
Caution Do not use different soldering methods together (except for partial heating).
Data Sheet U16369EJ1V0DS
75
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Table 11-1. Surface Mounting Type Soldering Conditions (2/2)
(3) µPD78F0034BGK-9ET:
64-pin plastic TQFP (12 x 12)
µPD78F0034BGK(A)-9ET:
64-pin plastic TQFP (12 x 12)
µPD78F0034BYGK-9ET:
64-pin plastic TQFP (12 x 12)
µPD78F0034BYGK(A)-9ET: 64-pin plastic TQFP (12 x 12)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Two times or less,
Exposure limit: 7 daysNote (after 7 days, prebake at 125°C for 10 hours)
IR35-107-2
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Two times or less,
Exposure limit: 7 daysNote (after 7 days, prebake at 125°C for 10 hours)
VP15-107-2
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max.,
Count: Once, Preheating temperature: 120°C max. (package surface temperature),
Exposure limit: 7 daysNote (after 7 days, prebake at 125°C for 10 hours)
WS60-107-1
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Note
–
After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
(4) µPD78F0034BF1-CN3:
73-pin plastic FBGA (9 x 9)
µPD78F0034BYF1-CN3: 73-pin plastic FBGA (9 x 9)
Soldering Method
Soldering Conditions
Recommended
ConditionSymbol
Infrared reflow
Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher),
Count: Three times or less,
Exposure limit: 3 daysNote (after that, prebake at 125°C for 20 hours)
IR60-203-3
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Three times or less,
Exposure limit: 3 daysNote (after that, prebake at 125°C for 20 hours)
VP15-203-3
Note
After opening the dry pack, store it at 25°C or less and 65%RH or less for the allowable storage period.
Caution Do not use different soldering methods together.
76
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD780034B, 780034BY.
Also refer to (6) Cautions on Using Development Tools.
(1) Software Package
SP78K0
CD-ROM in which various software tools for 78K/0 development are integrated in one
package
(2) Language Processing Software
RA78K0
Assembler package common to 78K/0 Series
CC78K0
C compiler package common to 78K/0 Series
DF780034
Device file for µPD780034A, 780034AY Subseries
CC78K0-L
C compiler library source file common to 78K/0 Series
(3) Flash Memory Writing Tools
Flashpro III (FL-PR3, PG-FP3)
Flash programmer dedicated to microcontrollers with on-chip flash memory
Flashpro IV (FL-PR4, PG-FP4)
FA-64GB-8EU
FA-64GC-8BS-A
FA-64GK-9ET
FA-73F1-CN3-A
Adapter for flash memory writing used connected to the Flashpro III/Flashpro IV.
• FA-64GB-8EU: 64-pin plastic LQFP (GB-8EU type)
• FA-64GC-8BS-A: 64-pin plastic LQFP (GC-8BS type)
• FA-64GK-9ET:
64-pin plastic TQFP (GK-9ET type)
• FA-73F1-CN3-A: 73-pin plastic FBGA (F1-CN3 type)
Data Sheet U16369EJ1V0DS
77
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(4) Debugging Tools
• When using in-circuit emulator IE-78K0-NS
IE-78K0-NS
In-circuit emulator common to 78K/0 Series
IE-70000-MC-PS-B
Power supply unit for IE-78K0-NS
IE-78K0-NS-PA
Performance board to enhance and expand the functions of IE-78K0-NS
IE-70000-98-IF-C
Adapter required when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported)
IE-70000-CD-IF-A
PC card and interface cable when using notebook PC as host machine (PCMCIA socket supported)
IE-70000-PC-IF-C
Adapter required when using IBM PC/ATTM or compatible as host machine (ISA bus supported)
IE-70000-PCI-IF-A
Adapter required when using PC in which PCI bus is incorporated as host machine
IE-780034-NS-EM1
Emulation board to emulate µPD780034A, 780034AY Subseries
NP-64GC
Emulation probe for 64-pin plastic LQFP (GC-8BS type)
NP-64GC-TQ
NP-H64GC-TQ
NP-64GK
Emulation probe for 64-pin plastic TQFP (GK-9ET type)
NP-H64GK-TQ
NP-H64GB-TQ
Emulation probe for 64-pin plastic LQFP (GB-8EU type)
NP-73F1-CN3Note
Emulation probe for 73-pin plastic FBGA (F1-CN3 type)
EV-9200GC-64
Conversion socket to connect the NP64GC and a target system board on which a 64-pin plastic LQFP
(GC-8BS type) can be mounted.
TGC-064SAP
Conversion adapter to connect the NP-64GC-TQ or NP-H64GC-TQ and a target system board on
which a 64-pin plastic LQFP (GC-8BS type) can be mounted
TGK-064SBW
Conversion adapter to connect the NP-64GK or NP-H64GK-TQ and a target system on which a 64pin plastic TQFP (GK-9ET type) can be mounted
TGB-064SDP
Conversion socket to connect the NP-H64GB-TQ and a target system board on which a 64-pin
plastic LQFP (GB-8EU type) can be mounted
CSICE73A0909N01,
Conversion socket to connect the NP-73F1-CN3 and a target system board on which a 73-pin plastic
LSPACK73A0909N01,
FBGA (F1-CN3 type) can be mounted
CSSOCKET73A0909N01
ID78K0-NS
Integrated debugger for IE-78K0-NS
SM78K0
System simulator common to 78K/0 Series
DF780034
Device file for µPD780034A, 780034AY Subseries
Note
The conversion socket (CSICE73A0909N01, LSPACK73A0909N01, or CSSOCKET73A0909N01) is supplied
with the emulation probe (NP-73F1-CN3).
78
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
• When using in-circuit emulator IE-78001-R-A
IE-78001-R-A
In-circuit emulator common to 78K/0 Series
IE-70000-98-IF-C
Adapter required when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported)
IE-70000-PC-IF-C
Interface adapter when using IBM PC/AT or compatible as host machine (ISA bus supported)
IE-70000-PCI-IF-A
Adapter required when using PC in which PCI bus is incorporated as host machine
IE-780034-NS-EM1
Emulation board to emulate µPD780034A, 780034AY Subseries
IE-78K0-R-EX1
Emulation probe conversion board necessary when using IE-780034-NS-EM1 on IE-78001-R-A
EP-78240GC-R
Emulation probe for 64-pin plastic LQFP (GC-8BS type)
EP-78012GK-R
Emulation probe for 64-pin plastic TQFP (GK-9ET type)
EV-9200GC-64
Conversion socket to connect the EP-78240GC-R and a target system board on which a 64-pin
plastic LQFP (GC-8BS type) can be mounted
TGK-064SBW
Conversion adapter to connect the EP-78012GK-R and a target system board on which a 64-pin plastic
TQFP (GK-9ET type) can be mounted
ID78K0
Integrated debugger for IE-78001-R-A
SM78K0
System simulator common to 78K/0 Series
DF780034
Device file for µPD780034A, 780034AY Subseries
(5) Real-Time OS
RX78K0
Real-time OS for 78K/0 Series
Caution The 64-pin plastic LQFP (GB-8EU type) and 73-pin plastic FBGA (F1-CN3 type) do not support
the IE-78001-R-A.
Data Sheet U16369EJ1V0DS
79
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(6) Cautions on Using Development Tools
• The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780034.
• The CC78K0 and RX78K0 are used in combination with the RA78K0 and the DF780034.
• FL-PR3, FL-PR4, FA-64GC-8BS-A, FA-64GB-8EU, FA-64GK-9ET, FA-73F1-CN3-A, NP-64GC, NP-64GCTQ, NP-H64GC-TQ, NP-64GK, NP-H64GK-TQ, NP-H64GB-TQ, and NP-73F1-CN3 are products made by
Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4191).
• TGC-064SAP, TGK-064SBW, TGB-064SDP, CSICE73A0909N01, LSPACK73A0909N01, and
CSSOCKET73A0909N01 are products made by TOKYO ELETECH CORPORATION.
Contact: Daimaru Kogyo, Ltd.
Tokyo Electronic Division (+81-3-3820-7112)
Osaka Electronic Division (+81-6-6244-6672)
• For third-party development tools, see the Single-chip Microcontroller Development Tool Selection Guide
(U11069E).
• The host machines and OSs supporting each software are as follows.
Host Machine
PC
EWS
HP9000 series 700TM [HP-UXTM]
SPARCstationTM [SunOSTM, SolarisTM]
Software
PC-9800 series [Japanese WindowsTM]
IBM PC/AT and compatibles
[Japanese/English Windows]
RA78K0
√ Note
√
CC78K0
√
Note
√
ID78K0-NS
√
–
ID78K0
√
–
SM78K0
√
–
RX78K0
√ Note
√
[OS]
Note
80
DOS-based software
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Conversion Socket Drawing (EV-9200GC-64) and Footprints
Figure A-1. EV-9200GC-64 Drawing (For Reference Only)
A
N
O
L
K
T
J
C
D
S
F
Q
M
R
B
E
EV-9200GC-64
1
P
No.1 pin index
G
H
I
EV-9200GC-64-G0
ITEM
MILLIMETERS
INCHES
A
18.8
0.74
B
14.1
0.555
C
14.1
0.555
D
18.8
0.74
E
4-C 3.0
4-C 0.118
F
0.8
0.031
G
6.0
0.236
H
15.8
0.622
I
18.5
0.728
J
6.0
0.236
K
15.8
0.622
L
18.5
0.728
M
8.0
0.315
N
7.8
0.307
O
2.5
0.098
P
2.0
0.079
Q
1.35
0.053
R
0.35 ± 0.1
0.014 +0.004
–0.005
S
φ 2.3
φ 0.091
T
φ 1.5
φ 0.059
Data Sheet U16369EJ1V0DS
81
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Figure A-2. EV-9200GC-64 Footprints (For Reference Only)
G
J
H
D
E
F
K
I
L
C
B
A
EV-9200GC-64-P1E
ITEM
MILLIMETERS
A
19.5
0.768
B
14.8
0.583
C
+0.003
0.8±0.02 × 15=12.0±0.05 0.031+0.002
–0.001 × 0.591=0.472 –0.002
D
+0.003
0.8±0.02 × 15=12.0±0.05 0.031+0.002
–0.001 × 0.591=0.472 –0.002
E
14.8
0.583
F
19.5
0.768
G
6.00 ± 0.08
0.236 +0.004
–0.003
H
6.00 ± 0.08
0.236 +0.004
–0.003
I
0.5 ± 0.02
0.197 +0.001
–0.002
J
φ 2.36 ± 0.03
φ 0.093 +0.001
–0.002
K
φ 2.2 ± 0.1
φ 0.087 +0.004
–0.005
L
φ 1.57 ± 0.03
φ 0.062 +0.001
–0.002
Caution
82
INCHES
DimensionsofmountpadforEV-9200andthatfortargetdevice
(QFP) may be different in some parts. For the recommended
mount pad dimensions for QFP, refer to "SEMICONDUCTOR
DEVICE MOUNTING TECHNOLOGY MANUAL"
(C10535E).
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Conversion Adapter Drawing (TGC-064SAP)
Figure A-3. TGC-064SAP Drawing (For Reference Only)
I
C
A
B
J
K
S
Protrusion height
D
T
E F G H
Q R
M
N
L
O
P
V
W
d
XZ
U
j
i
c
Y b
ITEM
a
e g
f
h
MILLIMETERS
INCHES
ITEM
MILLIMETERS
14.12
0.556
a
B
0.8x15=12.0
0.031x0.591=0.472
b
3.5
0.138
C
D
0.8
0.031
2.0
6.0
0.079
0.236
E
F
G
20.65
10.0
12.4
14.8
c
d
0.394
0.488
0.583
e
f
g
0.25
13.6
1.2
0.010
0.535
0.047
H
I
17.2
C 2.0
0.677
C 0.079
h
i
j
1.2
2.4
2.7
0.047
0.094
0.106
0.813
J
9.05
0.356
K
5.0
0.197
L
M
13.35
0.526
1.325
0.052
N
1.325
0.052
0.630
O
16.0
P
20.65
0.813
Q
12.5
0.492
R
17.5
0.689
S
4- φ 1.3
4-φ 0.051
T
U
V
1.8
φ 3.55
φ 0.9
W
X
φ 0.3
φ 0.140
φ 0.035
φ 0.012
(19.65)
(0.667)
Y
Z
7.35
1.2
0.289
0.047
1.85
INCHES
A
0.073
TGC-064SAP-G0E
0.071
note: Product by TOKYO ELETECH CORPORATION.
Data Sheet U16369EJ1V0DS
83
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Conversion Adapter Drawing (TGK-064SBW)
Figure A-4. TGK-064SBW Drawing (For Reference Only) (Unit: mm)
A
B
K
L
X
M
C
T
G F E D
H I
J
Protrusion height
U
S
V
Q
W
R
N
O
P
a
Z
e
Y
d
k
j
h
i
c
b
f
g
ITEM
MILLIMETERS
INCHES
ITEM
A
B
18.4
0.65x15=9.75
0.724
0.026x0.591=0.384
a
b
C
D
0.65
0.026
7.75
0.305
c
d
E
F
G
10.15
12.55
14.95
0.400
0.494
0.589
H
I
0.65x15=9.75
11.85
0.026x0.591=0.384
0.467
J
18.4
0.724
K
C 2.0
C 0.079
L
M
12.45
10.25
0.490
0.404
N
O
7.7
10.02
0.394
P
14.92
0.587
Q
R
11.1
1.45
0.437
0.057
S
1.45
0.057
T
U
4- φ 1.3
1.8
4-φ 0.051
V
5.0
0.197
φ 5.3
φ 0.209
W
X
Y
Z
0.071
4-C 1.0
4-C 0.039
φ 3.55
φ 0.9
φ 0.140
φ 0.035
note: Product by TOKYO ELETECH CORPORATION.
84
0.303
Data Sheet U16369EJ1V0DS
MILLIMETERS
INCHES
φ 0.3
φ 0.012
1.85
0.073
3.5
2.0
0.138
0.079
e
f
3.9
1.325
0.154
0.052
g
1.325
0.052
h
i
5.9
0.8
0.232
0.031
j
k
2.4
2.7
0.094
0.106
TGK-064SBW-G1E
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
APPENDIX B. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
µPD780024A, 780034A, 780024AY, 780034AY Subseries User’s Manual
U14046E
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY Data Sheet
U14042E
µPD780021A(A), 780022A(A), 780023A(A), 780024A(A), 780021AY(A), 780022AY(A), 780023AY(A),
U15131E
780024AY(A) Data Sheet
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY Data Sheet
U14044E
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A),
U15132E
780034AY(A) Data Sheet
µPD78F0034A, 78F0034AY Data Sheet
U14040E
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A) Data Sheet
This document
78K/0 Series User’s Manual Instruction
U12326E
Documents Related to Development Software Tools (User’s Manuals)
Document Name
RA78K0 Assembler Package
Document No.
Operation
U14445E
Language
U14446E
Structured Assembly Language
U11789E
Operation
U14297E
Language
U14298E
Operation (Windows Based)
U15373E
External Part User Open Interface Specifications
U15802E
ID78K Series Integrated Debugger Ver. 2.30 or Later
Operation (Windows Based)
U15185E
RX78K0 Real-time OS
Fundamentals
U11537E
Installation
U11536E
CC78K0 C Compiler
SM78K Series System Simulator Ver. 2.30 or Later
Project Manager Ver. 3.12 or Later (Windows Based)
Caution
U14610E
The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
Data Sheet U16369EJ1V0DS
85
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Documents Related to Development Hardware Tools (User’s Manuals)
Document Name
Document No.
IE-78K0-NS In-Circuit Emulator
U13731E
IE-78K0-NS-A In-Circuit Emulator
U14889E
IE-780034-NS-EM1 Emulation Board
U14642E
IE-78001-R-A In-Circuit Emulator
U14142E
IE-78K0-R-EX1 In-Circuit Emulator
To be prepared
Documents Related to Flash Memory Writing
Document Name
Document No.
PG-FP3 Flash Memory Programmer User’s Manual
U13502E
PG-FP4 Flash Memory Programmer User’s Manual
U15260E
Other Related Documents
Document Name
Document No.
SEMICONDUCTORS SELECTION GUIDE - Products & Packages -
X13769E
Semiconductor Device Mounting Technology Manual
C10535E
Quality Grades on NEC Semiconductor Devices
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892E
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
86
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
[MEMO]
Data Sheet U16369EJ1V0DS
87
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Note: Purchase of NEC Electronics I2C components conveys a license under the Philips I2C Patent Rights to
use these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
FIP and IEBus are trademarks of NEC Electronics Corporation.
Windows is either a registered trademark or trademark of Microsoft Corporation in the United States and/or
other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
88
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 01
Fax: 0211-65 03 327
• Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Fax: 091-504 28 60
• Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
• Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Hong Kong Ltd.
• Branch The Netherlands
Eindhoven, The Netherlands
Tel: 040-244 58 45
Fax: 040-244 45 80
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
• Tyskland Filial
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics Shanghai, Ltd.
• United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Taiwan Ltd.
Shanghai, P.R. China
Tel: 021-6841-1138
Fax: 021-6841-1137
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
Fax: 6250-3583
J02.11
Data Sheet U16369EJ1V0DS
89
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
• The information in this document is current as of September, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
• NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1