FUJITSU SEMICONDUCTOR DATA SHEET DS07-12507-2E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89810A Series MB89816A/P817A ■ DESCRIPTION The MB89810A series is a line of single-chip microcontrollers based on the F2MC*-8L CPU core which can operate at low voltage but at high speed. The microcontrollers contain peripheral function such as timer, serial interface, a UART, and an external interrupt. The MB89810A series is applicable to a wide range of applications from welfare products to industrial equipment, including portable devices. *: F2MC stands for FUJITSU Flexible Microcontroller. ■ FEATURES High speed processing at low voltage Minimum execution time: 0.8 µs/3.0 V, 1.33 µs/2.2 V • F2MC-8L family CPU core Instruction set optimized for controllers Multiplication and division instructions 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc. • Four types of timers 8-bit PWM timer: 2 channels (also serve as reload timers) 16-bit timer/counter 21-bit time-base timer • Two serial interface 8-bit synchronous serial (Switchable transfer direction allows communication with various equipment.) UART (5-, 7-, or 8-bit transfer capable) (Continued) ■ PACKAGE 64-pin Plastic QFP (FPT-64P-M06) MB89810A Series (Continued) • External interrupt: 8 channels Eight channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). • Low-power consumption modes Stop mode (Oscillation stops to minimize the current consumption) Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal) ■ PRODUCT LINEUP Part number Parameter Classification ROM size MB89816A MB89P817A Mass-production product (mask ROM products) One-time PROM product (for evaluation and development) 24 K × 8 bits (internal mask ROM) 32 K × 8 bits (internal PROM, programming with general-purpose EPROM programmer) 2048 × 8 bits RAM size CPU functions Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.8 µs/5 MHz 7.2 µs/5 MHz Ports Input ports: Output ports: I/O ports (N-ch open-drain): I/O ports (CMOS): Total: 8 (All also serve as peripherals.) 8 5 (for LED driving) 32 (14 ports also serve as peripherals.) 53 8-bit PWM timer Two internal channels 8-bit reload timer operation (toggled output capable, operating clock cycle: 3 different cycles) 8-bit resolution PWM operation (conversion cycle: 3 different cycles) 8-bit timer/counter UART 8-bit Serial I/O External interrupt 16-bit timer operation 16-bit event counter operation 5-, 7-, or 8-bit transfer capable Built-in baud rate generator Clock synchronous/asynchronous data transfer capable 8-bits LSB-first/MSB first selectability One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks) 8 independent channels (edge selection, interrupt vector, source flag) 4 channels: Level detection (level selectable) 4 channels: Edge detection (edge selectable) Used also for wake-up from the stop/sleep mode. (Edge detection is also permitted in stop mode.) (Continued) 2 MB89810A Series (Continued) Part number MB89816A Parameter Watch interrupt MB89P817A Interrupt cycles: 4 different cycles (subclock) Watchdog timer reset Reset occurrence cycle: 839 ms/5 MHz Standby mode Sleep mode, stop mode Process CMOS Package FPT-64P-M06 Operating voltage 2.2 V to 6.0 V* 2.7 V to 6.0 V* * : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”) ■ PIN ASSIGNMENT 64 63 62 61 60 59 58 57 56 55 54 53 52 P47/SCL2 P46/RXD2 P45/TXD2 P44/SCL1 P43/RXD1 P42/TXD1 P41/EC VCC P40 P54 P53 P52 P51 (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 P50 VSS P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RST MOD0 MOD1 X0 X1 VSS P27 P26 P25 P24 P23 P22 P21 P30/PWE P31/SCK P32/SO P33/SI P34/PWO P35/PWI P36/PTO1 P37/PTO2 P60/INT0 P61/INT1 P62/INT2 VCC P63/INT3 P64/INT4 P65/INT5 P66/INT6 P67/INT7 X0A X1A (FPT-64P-M06) 3 MB89810A Series ■ PIN DESCRIPTION Pin no. Pin name 23 X0 24 X1 18 X0A 19 X1A 21 MOD0 22 MOD1 20 Circuit type Function A Main clock oscillator pins I Subclock crystal oscillator pins B Operating mode selection pins Connect directly these pins directly to VSS. RST C Reset I/O pin This pin is an N-ch open-drain output type with a pull-up resistor and a hysteresis input type. “L” is output from this pin by an internal reset source. The internal circuit is initialized by the input of “L”. 49 to 42 P00 to P07 D General-purpose I/O ports A pull-up resistor option is provided. These ports have the port output inverting function. 41 to 34 P10 to P17 D General-purpose I/O ports A pull-up resistor option is provided. These ports have the port output inverting function. 33 to 30 P20 to P23 F General-purpose output ports These ports have the port output inverting function. 29 to 26 P24 to P27 F General-purpose output ports 1 P30 /PWE E General-purpose I/O port A pull-up resistor option is provided. Also serves as a pulse width detection enable input (PWE). PWE input is hysteresis input. 2 P31/SCK E General-purpose I/O port A pull-up resistor option is provided. Also serves as the clock I/O for the 8-bit serial I/O (SCK). SCK input is hysteresis input. 3 P32/SO D General-purpose I/O port A pull-up resistor option is provided. Also serves as the data output for the 8-bit serial I/O (SO). 4 P33/SI E General-purpose I/O port A pull-up resistor option is provided. Also serves as the data input for the 8-bit serial I/O (SI). SI input is hysteresis input. 5 P34/PWO D General-purpose I/O port A pull-up resistor option is provided. Also serves as a pulse width detection output (PWO). 6 P35/PWI E General-purpose I/O port A pull-up resistor option is provided. Also serves as a pulse width detection input (PWI). PWI input is hysteresis input. 7 P36/PTO1 D General-purpose I/O port A pull-up resistor option is provided. Also serves as the toggle output for the 8-bit PWM timer 1 (PTO1). (Continued) 4 MB89810A Series (Continued) Pin no. Pin name Circuit type Function 8 P37/PTO2 D General-purpose I/O port A pull-up resistor option is provided. Also serves as the toggle output for the 8-bit PWM timer 2 (PTO2). 56 P40 D General-purpose I/O port A pull-up resistor option is provided. 58 P41/EC E General-purpose I/O port A pull-up resistor option is provided. Also serves as a 16-bit timer/counter input (EC). EC input is hysteresis input. 59 P42/TXD1 D General-purpose I/O port A pull-up resistor option is provided. Also serves as the data output 1 for the UART (TXD1). 60 P43/RXD1 E General-purpose I/O port A pull-up resistor option is provided. Also serves as the data input 1 for the UART (RXD1). RXD1 input is hysteresis input. 61 P44/SCL1 E General-purpose I/O port A pull-up resistor option is provided. Also serves as the clock I/O 1 for the UART (SCL1). SCL1 input is hysteresis input. 62 P45/TXD2 D General-purpose I/O port A pull-up resistor option is provided. Also serves as the data output 2 for the UART (TXD2). 63 P46/RXD2 E General-purpose I/O port A pull-up resistor option is provided. Also serves as the data input 2 for the UART (RXD2). RXD2 input is hysteresis input. 64 P47/SCL2 E General-purpose I/O port A pull-up resistor option is provided. Also serves as the clock I/O 2 for the UART (SCL2). SCL2 input is hysteresis input. 51 to 55 P50 to P54 G N-channel open-drain I/O ports A pull-up resistor option is provided only for the MB89816A. 9 to 11 P60/INT0 to P62/INT2 H General-purpose I/O ports A pull-up resistor option is provided. Also serve as an external interrupt input (INT0 to INT2). These ports are a hysteresis input type. 13 to 17 P63/INT3 to P67/INT7 H General-purpose I/O ports A pull-up resistor option is provided. Also serve as an external interrupt input (INT3 to INT7). These ports are a hysteresis input type. 12, 57 VCC – Power supply pin 25, 50 VSS – Power supply (GND) pin 5 MB89810A Series ■ I/O CIRCUIT TYPE Type A Circuit Remarks • Main clock • At an oscillation feedback resistor of approximately 2 MΩ (1 to 5 MHz) • CR oscillator circuit selectability X1 X0 Standby control signal B C R P-ch • At an output pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V • Hysteresis input N-ch D • CMOS output • CMOS input R P-ch P-ch N-ch • Pull-up resistor optional E • CMOS output • CMOS input • Hysteresis input (resource input) R P-ch P-ch N-ch • Pull-up resistor optional (Continued) 6 MB89810A Series (Continued) Type Circuit Remarks F • CMOS output P-ch N-ch G • N-ch open-drain output • CMOS input R P-ch N-ch • Pull-up resistor optional (only for the MB89816A) H • Hysteresis input • Pull-up resistor optional I X1A • Subclock (30 to 40 kHz) • At an oscillation feedback resistor of approximately 4.5 MΩ X0A 7 MB89810A Series ■ HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 4. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode. 8 MB89810A Series ■ PROGRAMMING TO THE EPROM ON THE MB89P817A In EPROM mode, the MB89P817A functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. • Writing Procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0007H to 7FFFH (note that addresses 8007H to FFFFH while operating as operating mode assign to 0007H to 7FFFH in EPROM mode). Load option data into addresses 0000H to 0006H of the EPROM programmer. (For information about each corresponding option, see “• Setting OTPROM Option Bit Map.”) (3) Program with the EPROM programmer. • Memory Space Memory space is diagrammed below. 0000H Option area 0007H Program area (PROM) 7FFFH 9 MB89810A Series • Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM (one-time PROM) microcomputer program. Program, verify Aging +150°C, 48 Hrs. Data verification Assembly • Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. • EPROM Programmer Socket Adapter Package FPT-64P-M06 Compatible socket adapter ROM-64QF-28DP-8L Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760 Note: Connect the jumper pin to VSS when using. Depending on the EPROM programmer, inserting a capacitor of approx. 0.1 µF between VPP and VSS or VCC and VSS can stabilize programming operations. 10 MB89810A Series • OTPROM Option Bit Map Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Readable and writable Single-clock Reset pin setting output 1: Dual-clock 1: Enabled 0: Single-clock 0: Disabled Power-on Oscillation stabilization time reset 4 14 1: Enabled 00 217/FCH 01 218/FCH 0: Disabled 10 2 /FCH 11 2 /FCH P06 Pull-up 1: No 0: Yes P05 Pull-up 1: No 0: Yes P04 Pull-up 1: No 0: Yes P03 Pull-up 1: No 0: Yes P02 Pull-up 1: No 0: Yes P01 Pull-up 1: No 0: Yes P00 Pull-up 1: No 0: Yes 0002H P17 Pull-up 1: No 0: Yes P16 Pull-up 1: No 0: Yes P15 Pull-up 1: No 0: Yes P14 Pull-up 1: No 0: Yes P13 Pull-up 1: No 0: Yes P12 Pull-up 1: No 0: Yes P11 Pull-up 1: No 0: Yes P10 Pull-up 1: No 0: Yes 0003H P37 Pull-up 1: No 0: Yes P36 Pull-up 1: No 0: Yes P35 Pull-up 1: No 0: Yes P34 Pull-up 1: No 0: Yes P33 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes 0004H P47 Pull-up 1: No 0: Yes P46 Pull-up 1: No 0: Yes P45 Pull-up 1: No 0: Yes P44 Pull-up 1: No 0: Yes P43 Pull-up 1: No 0: Yes P42 Pull-up 1: No 0: Yes P41 Pull-up 1: No 0: Yes P40 Pull-up 1: No 0: Yes Vacancy Vacancy Vacancy Readable and writable Readable and writable Readable and writable P64 Pull-up 1: No 0: Yes P63 Pull-up 1: No 0: Yes P62 Pull-up 1: No 0: Yes P61 Pull-up 1: No 0: Yes P60 Pull-up 1: No 0: Yes Vacancy Vacancy Vacancy Vacancy Oscillator type Readable and writable Readable and writable Readable and writable Readable and writables 1: Crystal 0: CR P67 Pull-up 1: No 0: Yes P66 Pull-up 1: No 0: Yes P65 Pull-up 1: No 0: Yes Vacancy Vacancy Vacancy Readable and writable Readable and writable 0001H P07 Pull-up 1: No 0: Yes 0000H 0005H 0006H Note: Each bit defaults to 1. 11 MB89810A Series ■ BLOCK DIAGRAM Time-base timer Main clock oscillator Clock controlletr X0A X1A 8-bit PWM timer 1 P36/PTO1 Port 0 and port 1 CMOS I/O port 8 P1 0 t o P17 8 Port 2 CMOS output port 8-bit serial I/O 1 P31/SCK P33/SI P32/SO Pulse width detection P 3 0 / P WE P 3 5 / P WI P 3 4 / P WO CMOS I/O port UART RAM (2048 × 8 bits) F2MC-8L CPU ROM (24 K × 8 bits) Other pins 16-bit timer/counter P41/EC CMOS I/O port P40 Port 5 N-ch open-drain I/O port External interrupt VCC × 2, VSS × 2 MOD0, MOD1 Input port 12 P44/SCL1 P47/SCL2 P43/RXD1 P46/RXD2 P42/TXD1 P45/TXD2 Port 4 8 P0 0 t o P07 Internal bus Reset circuit (WDT) RST P2 0 t o P27 P37/PTO2 Port 3 Subclock oscillator 8-bit PWM timer 2 5 P50 to P54 8 8 Port 6 X0 X1 P60/INT0 to P67/INT7 MB89810A Series ■ CPU CORE 1. Memory Space The microcontrollers of the MB89810A series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89810A series is structured as illustrated below. Memory Space MB89816A 0000H MB89P817A 0000H I/O I/O 0080H 0080H 0100H 0100H Register 0200H Register 0200H RAM 2 KB RAM 2 KB 0880H 0880H Not available Not available 8000H Optional PROM 8007H A000H PROM 32 KB ROM 24 KB FFFFH FFFFH 13 MB89810A Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): A 16-bit register for indicating instruction storage positions Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX): A 16-bit register for index modification Extra pointer (EP): A 16-bit pointer for indicating a memory address Stack pointer (SP): A 16-bit register for indicating a stack area Program status (PS): A 16-bit register for storing a register pointer, a condition code 16 bits Initial value : Program counter PC FFFDH A : Accumulator Undefined T : Temporary accumulator Undefined IX : Index register Undefined EP : Extra pointer Undefined SP : Stack pointer Undefined PS : Program status I-flag = 0, IL1, 0 = 11 Other bits are undefined. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) Structure of the Program Status Register 15 PS 14 13 12 RP 10 9 8 Vacancy Vacancy Vacancy RP 14 11 7 6 H I 5 4 IL1, 0 3 2 1 0 N Z V C CCR MB89810A Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area Lower OP codes RP “0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ b1 b0 ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level 0 0 0 1 1 0 2 1 1 3 1 High-low High Low = no interrupt N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise. V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction. 15 MB89810A Series The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 32 banks can be used on the MB89816A. The bank currently in use is indicated by the register bank pointer (RP). Register Bank Configuration This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area 16 MB89810A Series ■ I/O MAP Address Read/write Register name Register description 00H (R/W) PDR0 Port 0 data register 01H (W) DDR0 Port 0 data direction register 02H (R/W) PDR1 Port 1 data register 03H (W) DDR1 Port 1 data direction register 04H (R/W) PDR2 Port 2 data register 05H Vacancy 06H Vacancy 07H (R/W) SYCC System clock control register 08H (R/W) STBC Standby control register 09H (R/W) WDTC Watchdog timer control register 0AH (R/W) TBCR Time-base timer control register 0BH (R/W) WPCR Watch prescaler control register 0CH (R/W) PDR3 Port 3 data register 0DH (W) DDR3 Port 3 data direction register 0EH (R/W) PDR4 Port 4 data register 0FH (W) DDR4 Port 4 data direction register 10H (R/W) PDR5 Port 5 data register 11H (R) PDR6 Port 6 data register 12H Vacancy 13H Vacancy 14H Vacancy 15H Vacancy 16H Vacancy 17H (R/W) PIVE 18H (R/W) TMCR 16-bit timer count register 19H (R/W) TCHR 16-bit timer count register (H) 1AH (R/W) TCLR 16-bit timer count register (L) Port inverting operation enable register Vacancy 1BH 1CH (R/W) SMR Serial I/O mode register 1DH (R/W) SDR Serial I/O data register 1EH Vacancy 1FH Vacancy (Continued) 17 MB89810A Series (Continued) Address Read/write Register name 20H (R/W) SMC1 21H (R/W) SRC UART serial I/O rate control register 22H (R/W) SSD UART serial I/O status/data control register 23H (R/W) SIDR/SODR 24H (R/W) SMC2 UART serial I/O mode control register 1 UART serial I/O data control register UART serial I/O mode control register 2 25H Vacancy 26H Vacancy 27H Vacancy 28H (R/W) CNTR1 PWM timer control register 1 29H (R/W) CNTR2 PWM timer control register 2 2AH (R/W) CNTR3 PWM timer control register 3 2BH (W) COMR2 PWM timer compare register 2 2CH (W) COMR1 PWM timer compare register 1 2DH Vacancy 2EH Vacancy 2FH (R/W) PWCR Pulse width detection control register 30H (R/W) EIC1 External interrupt 1 control register 1 31H (R/W) EIC2 External interrupt 1 control register 2 32H (R/W) EI2E External interrupt 2 enable register 33H (R/W) EI2F External interrupt 2 flag register 34H Vacancy 35H to 7AH Vacancy 7BH Vacancy 7CH (W) ILR1 Interrupt level register 1 7DH (W) ILR2 Interrupt level register 2 7EH (W) ILR3 Interrupt level register 3 7FH Not available ITR Interrupt test register Note: Do not use vacancies. 18 Register description MB89810A Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = 0.0 V) Parameter Symbol Value Unit Remarks Min. Max. VCC VSS – 0.3 VSS + 7.0 V VI1 VSS – 0.3 VCC + 0.3 V Except P50 to P54 VI2 VSS – 0.3 VSS + 7.0 V P50 to P54 VO1 VSS – 0.3 VCC + 0.3 V Except P50 to P54 VO2 VSS – 0.3 VSS + 7.0 V P50 to P54 IOL — 20 mA Peak value IOLAV1 — 4 mA Average value except pins other than P50 to P54 IOLAV2 — 10 mA Average value for P50 to P54 “L” level total maximum output current ∑IOL — 100 mA Peak value “L” level total average output current ∑IOLAV — 40 mA Average value “H” level maximum output current IOH — –20 mA Peak value “H” level average output current IOHAV — –4 mA Average value “H” level total maximum output current ∑IOH — –50 mA Peak value “H” level total average output current ∑IOHAV — –20 mA Average value Power consumption PD — 300 mW Operating temperature TA –40 +85 °C Storage temperature Tstg –55 +150 °C Power supply voltage Input voltage Output voltage “L” level maximum output current “L” level average output current Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 19 MB89810A Series 2. Recommended Operating Conditions (VSS = 0.0 V) Symbol Parameter Value Unit Remarks Min. Max. 2.2* 6.0 V Normal operation assurance range MB89816A 2.7* 6.0 V Normal operation assurance range MB89P817A 1.5 6.0 V Retains the RAM state in stop mode VIH 0.7 VCC VCC + 0.3 V P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P54 (with pull-up resistor) VIHS 0.8 VCC VCC + 0.3 V RST, MOD0, MOD1, P60 to P67, Pheripheral input for port 3 and port 4 VIHS2 0.8 VCC VSS + 6.0 V P50 to P54 (without pull-up resistor) VIL VSS – 0.3 0.3 VCC V P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P54 VILS VSS – 0.3 0.2 VCC V RST, MOD0, MOD1, P60 to P67, Pheripheral input for port 3 and port4 Open-drain output pin application voltage VD VSS – 0.3 VSS + 6.0 V P50 to P54 (without pull-up resistor) Operating temperature TA –40 +85 °C Power supply voltage VCC “H” level voltage “L” level voltage * : These values vary with the operating frequency. See Figure 1. Operating voltage (V) 6 5 Operating assurance range 4 3 2 1 2.0 5.0 4.0 Main clock operating frequency (MHz) (at an instruction cycle of 4/FCH) 1.0 3.0 Note: The shaded area is assured only for the MB89816A Figure 1 20 Operating Voltage vs. Main Clock Operating Frequency (for MB89816A) MB89810A Series 3. DC Characteristics (VCC = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C) Value Parameter “H” level output voltage Pin Symbol Condition Unit Min. Typ. Max. IOH = –2.0 mA 2.4 — — V IOL = 1.8 mA — — 0.4 V Remarks P00 to P07, P10 to P17, VOH P20 to P27, P30 to P37, P40 to P47 P00 to P07, P10 to P17, VOL1 P20 to P27, P30 to P37, P40 to P47, P50 to P54 P60 to P67 “L” level output voltage VOL2 P50 to P54 IOL = 6 mA VCC = 3 V — — 0.5 V VOL3 RST IOL = 4.0 mA — — 0.4 V 0.45 V < VI < VCC — — ±5 µA Without pull-up resistor VI = 0.0 V 25 50 100 kΩ With pull-up resistor FCH = 5 MHz VCC = 5.0 V tinst = 0.8 µs — 4 6 mA MB89816A — 4.8 7.5 mA MB89P817A FCH = 5 MHz VCC = 3.0 V tinst = 6.4 µs — 0.4 0.6 mA MB89816A — 1.0 1.5 mA MB89P817A — 1.2 1.8 mA P00 to P07, P10 to P17, P20 to P27, P30 to P37, Input leakage current (Hi-z output leakage ILI1 P40 to P47, P50 to P54, P60 to P67, current) MOD0, MOD1 P00 to P07, P10 to P17, Pull-up resistance RPULL P30 to P37, P40 to P47, P50 to P54, P60 to P67, RST ICC1 ICC2 Power supply current* ICCS1 VCC FCH = 5 MHz VCC = 5.0 V tinst = 0.8 µs Sleep mode ICCS2 ICCL FCH = 5 MHz VCC = 3.0 V tinst = 12.8 µs FCL = 32.768 kHz VCC = 3.0 V — 0.3 0.5 mA — 50 100 µA Subclock mode — 500 700 µA MB89P817A (Continued) 21 MB89810A Series (Continued) (VCC = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C) Value Parameter Pin Symbol Condition ICCLS FCL = 32.768 kHz VCC = 3.0 V ICCT FCL = 32.768 kHz VCC = 3.0 V Min. Typ. Max. — 15 50 Unit Remarks µA Subclock sleep mode Watch mode Power supply current* — — 15 µA VCC Main clock stop mode at dualclock system Subclock stop mode Main clock FCL = 32.768 kHz VCC = 3.0 V ICCH — — 10 µA stop mode at single-clock system Input capacitance CIN Other than VCC and VSS f = 1 MHz — 10 — pF * : The measurement conditions of power supply current are as follows: the external clock and TA = +25°C. 22 MB89810A Series 4. AC Characteristics (1) Reset Timing (VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol Parameter RST “L” pulse width Value Condition tZLZH — Min. Max. 16 tCH — Unit Remarks ns Note: tCH is the cycle time of the main clock. tZLZH RST 0.2 VCC 0.2 VCC (2) Power-on Reset (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Power supply rising time tR Power supply cut-off time tOFF Condition — Value Unit Remarks Min. Max. — 50 ms Power-on reset function only 1 — ms Due to repeated operations Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR tOFF 2.0 V VCC 0.2 V 0.2 V 0.2 V Note that a sudden increase in supply voltage may result in a power-on reset. When increasing the supply voltage during operation, voltage variation should be within twice the intended increment so that the voltage rises as smoothly as possible. 23 MB89810A Series (3) Clock Timing (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time Pin Condition Value Min. Typ. Max. FCH X0, X1 1 — 5 MHz FCL X0A, X1A — 32.768 — kHz tCH X0, X1 200 — 1000 ns tCL X0A, X1A — 30.5 — µs PWH PWL X0 20 — — ns PWHL PWLL X0A — 15.2 — µs tCR tCF X0 — — 10 ns — X0 and X1 Timing and Conditions tCH PWH PWL tCR 0.8 VCC tCF 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC Main Clock Conditions When a crystal or ceramic resonator is used X0 X1 when an external clock is used X0 X1 Open When a CR oscillator is used X0 24 Unit X1 Remarks External clock External clock MB89810A Series X0A and X1A Timings and Conditions tCL PWHL PWLL tCR tCF 0.8 VCC 0.8 VCC X0A 0.2 VCC 0.2 VCC 0.2 VCC Subclock Conditions When a crystal or ceramic resonator is used X0A when an external clock is used X1A X0A X1A Open (4) Serial I/O Timings (VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin Serial clock cycle time tSCYC1 SCK SCK ↓ → SO time tSLOV1 SCK, SO Valid SI → SCK ↑ tIVSH1 SI, SCK SCK ↑ → valid SI hold time tSHIX1 SCK, SI Serial clock “H” pulse width tSHSL Serial clock “L” pulse width tSLSH Condition Internal shift clock mode SCK External shift clock mode Value Unit Remarks Min. Max. 2 tinst — ns –200 200 ns 1/2 tinst — ns 1/2 tinst — ns 1 tinst — ns 1 tinst — ns 0 200 ns SCK ↓ → SO time tSLOV2 SCK, SO Valid SI → SCK ↑ tIVSH2 SI, SCK 1/2 tinst — ns SCK ↑ → valid SI hold time tSHIX2 SCK, SI 1/2 tinst — ns * : tinst represents the minimum instruction execution time. It varies with the selected system clock and operating mode. 25 MB89810A Series (5) UART Timings (VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin Condition Serial clock cycle time tSCYC SCL1, SCL2 SCL ↓ → TXDx time tSLOV1 SCLx, TXDx Valid RXDx → SCLx ↑ tIVSH1 RXDx, SCLx SCLx ↑ → valid RXDx hold time tSHIX1 SCL1, RXD2 Serial clock “H” pulse width Internal shift clock mode tSHSL Value Unit Remarks Min. Max. 2 tinst — ns –200 200 ns 1/2 tinst — ns 1/2 tinst — ns 1 tinst — ns 1 tinst — ns 0 200 ns SCL1, SCL2 Serial clock “L” pulse width tSLSH External shift clock mode SCLx ↓ → TXDx time tSLOV2 SCLx, TXDx Valid RXDx → SCLx ↑ tIVSH2 RXDx, SCLx 1/2 tinst — ns SCLx ↑ → valid RXDx hold time tSHIX2 SCL1, RXD2 1/2 tinst — ns Notes: • • tinst represents the minimum instruction execution time. It varies with the selected system clock and operating mode. The edge polarity for the SLCx input is assumed when LSEL bit = 0 for SMC2. The polarity is inverted when LSEL = 1. Internal Shift Clock Mode tSCYC SCK/SCLx 2.4 V 0.8 V 0.8 V t SLOV1 2.4 V SO/TXDx 0.8 V tIVSH1 SI/RXDx tSHIX1 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC External Shift Clock Mode tSLSH SCK/SCLx tSHSL 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV2 SO/TXDx 2.4 V 0.8 V tIVSH2 SI/RXDx 26 tSHIX2 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC MB89810A Series (6) Peripheral Input Timings (VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Pin Condition Peripheral input “H” pulse tILIH width EC, INT0 to INT7 Peripheral input “L” pulse width tIHIL EC, INT0 to INT7 “H” input pulse width of pulse width detection enable signal tPWEH “L” input pulse width of pulse width detection enable signal tPWEL Parameter Notes: • • • Symbol Value Unit Remarks Min. Max. — 2 tinst — ns — 2 tinst — ns — 512 tCL + 200 or 480 tCL + 200 — ns — 512 tCL + 200 or 480 tCL + 200 — ns PWE tinst represents the minimum instruction execution time. It varies with the selected system clock and operating mode. tCL represents the subclock cycle time. The PWE pulse width value varies with the first divider selection bit of the watch prescaler. The pulse width is “512 tCL + 200” when divide by 16 is selected; or "480 tCL + 200" when divide by 15 is selected. tIHIL EC, INT0 to INT7 tILIH 0.8 VCC 0.2 VCC 0.2 VCC tPWEH tPWEL 0.8 VCC PWE 0.2 VCC 0.8 VCC 0.8 VCC 0.2 VCC 27 MB89810A Series ■ INSTRUCTIONS Execution instructions can be divided into the following four groups: • • • • Transfer Arithmetic operation Branch Others Table 1 lists symbols used for notation of instructions. Table 1 Instruction Symbols Symbol Meaning dir Direct address (8 bits) off Offset (8 bits) ext Extended address (16 bits) #vct Vector table number (3 bits) #d8 Immediate data (8 bits) #d16 Immediate data (16 bits) dir: b Bit direct address (8:3 bits) rel Branch relative address (8 bits) @ Register indirect (Example: @A, @IX, @EP) A Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) AH Upper 8 bits of accumulator A (8 bits) AL Lower 8 bits of accumulator A (8 bits) T Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) TH Upper 8 bits of temporary accumulator T (8 bits) TL Lower 8 bits of temporary accumulator T (8 bits) IX Index register IX (16 bits) (Continued) 28 MB89810A Series (Continued) Symbol Meaning EP Extra pointer EP (16 bits) PC Program counter PC (16 bits) SP Stack pointer SP (16 bits) PS Program status PS (16 bits) dr Accumulator A or index register IX (16 bits) CCR Condition code register CCR (8 bits) RP Register bank pointer RP (5 bits) Ri General-purpose register Ri (8 bits, i = 0 to 7) × Indicates that the very × is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (×) Indicates that the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (( × )) The address indicated by the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: Number of instructions #: Number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: • “–” indicates no change. • dH is the 8 upper bits of operation description data. • AL and AH must become the contents of AL and AH immediately before the instruction is executed. • 00 becomes 00. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ← This indicates 48, 49, ... 4F. 29 MB89810A Series Table 2 Transfer Instructions (48 instructions) Mnemonic ~ # Operation TL TH AH NZVC OP code MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 – – – – – AL AL AL AL AL AL AL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –––– –––– –––– –––– –––– ++–– ++–– ++–– ++–– ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off 5 4 2 3 4 5 3 1 1 3 2 2 – – – AL AL AL – – – AH AH AH – – – dH dH dH –––– –––– –––– ++–– ++–– ++–– D4 D7 E3 E4 C5 C6 MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ← (A) ( (IX) +off ) ← (A) (ext) ← (A) ( (EP) ) ← (A) (Ri) ← (A) (A) ← d8 (A) ← (dir) (A) ← ( (IX) +off) (A) ← (ext) (A) ← ( (A) ) (A) ← ( (EP) ) (A) ← (Ri) (dir) ← d8 ( (IX) +off ) ← d8 ( (EP) ) ← d8 (Ri) ← d8 (dir) ← (AH),(dir + 1) ← (AL) ( (IX) +off) ← (AH), ( (IX) +off + 1) ← (AL) (ext) ← (AH), (ext + 1) ← (AL) ( (EP) ) ← (AH),( (EP) + 1) ← (AL) (EP) ← (A) (A) ← d16 (AH) ← (dir), (AL) ← (dir + 1) (AH) ← ( (IX) +off), (AL) ← ( (IX) +off + 1) (AH) ← (ext), (AL) ← (ext + 1) (AH) ← ( (A) ), (AL) ← ( (A) ) + 1) (AH) ← ( (EP) ), (AL) ← ( (EP) + 1) (A) ← (EP) (EP) ← d16 (IX) ← (A) (A) ← (IX) (SP) ← (A) (A) ← (SP) ( (A) ) ← (T) ( (A) ) ← (TH),( (A) + 1) ← (TL) (IX) ← d16 (A) ← (PS) (PS) ← (A) (SP) ← d16 (AH) ↔ (AL) (dir): b ← 1 (dir): b ← 0 (AL) ↔ (TL) (A) ↔ (T) (A) ↔ (EP) (A) ↔ (IX) (A) ↔ (SP) (A) ← (PC) AL AL AL – – – – – – – – – – – – – – – AL AL – – – – AH AH AH – – – – – – – – – – – – – – – – AH – – – – dH dH dH dH – – dH – dH – – – dH – – AL – – – dH dH dH dH dH ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– ++++ –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0 Notes: • During byte transfer to A, T ← A is restricted to low bytes. •Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) 30 MB89810A Series Table 3 Mnemonic ~ # ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ROLC A 2 1 CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation TL TH AH NZVC OP code (A) ← (A) + (Ri) + C (A) ← (A) + d8 + C (A) ← (A) + (dir) + C (A) ← (A) + ( (IX) +off) + C (A) ← (A) + ( (EP) ) + C (A) ← (A) + (T) + C (AL) ← (AL) + (TL) + C (A) ← (A) − (Ri) − C (A) ← (A) − d8 − C (A) ← (A) − (dir) − C (A) ← (A) − ( (IX) +off) − C (A) ← (A) − ( (EP) ) − C (A) ← (T) − (A) − C (AL) ← (TL) − (AL) − C (Ri) ← (Ri) + 1 (EP) ← (EP) + 1 (IX) ← (IX) + 1 (A) ← (A) + 1 (Ri) ← (Ri) − 1 (EP) ← (EP) − 1 (IX) ← (IX) − 1 (A) ← (A) − 1 (A) ← (AL) × (TL) (A) ← (T) / (AL),MOD → (T) (A) ← (A) ∧ (T) (A) ← (A) ∨ (T) (A) ← (A) ∀ (T) (TL) − (AL) (T) − (A) → C→A – – – – – – – – – – – – – – – – – – – – – – – dL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 00 – – – – – – – – – – – dH – – – – – – dH – – – – dH – – – dH dH 00 dH dH dH – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++– –––– –––– ++–– +++– –––– –––– ++–– –––– –––– ++R– ++R– ++R– ++++ ++++ ++–+ 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 C ← A← – – – ++–+ 02 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65 (A) − d8 (A) − (dir) (A) − ( (EP) ) (A) − ( (IX) +off) (A) − (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) ← (AL) ∀ (TL) (A) ← (AL) ∀ d8 (A) ← (AL) ∀ (dir) (A) ← (AL) ∀ ( (EP) ) (A) ← (AL) ∀ ( (IX) +off) (A) ← (AL) ∀ (Ri) (A) ← (AL) ∧ (TL) (A) ← (AL) ∧ d8 (A) ← (AL) ∧ (dir) (Continued) 31 MB89810A Series (Continued) Mnemonic ~ # AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 Operation (A) ← (AL) ∧ ( (EP) ) (A) ← (AL) ∧ ( (IX) +off) (A) ← (AL) ∧ (Ri) (A) ← (AL) ∨ (TL) (A) ← (AL) ∨ d8 (A) ← (AL) ∨ (dir) (A) ← (AL) ∨ ( (EP) ) (A) ← (AL) ∨ ( (IX) +off) (A) ← (AL) ∨ (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) + off) – d8 (Ri) – d8 (SP) ← (SP) + 1 (SP) ← (SP) – 1 Table 4 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ # 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI 32 ~ # 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++++ ++++ ++++ ++++ –––– –––– 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1 Branch Instructions (17 instructions) Operation If Z = 1 then PC ← PC + rel If Z = 0 then PC ← PC + rel If C = 1 then PC ← PC + rel If C = 0 then PC ← PC + rel If N = 1 then PC ← PC + rel If N = 0 then PC ← PC + rel If V ∀ N = 1 then PC ← PC + rel If V ∀ N = 0 then PC ← PC + reI If (dir: b) = 0 then PC ← PC + rel If (dir: b) = 1 then PC ← PC + rel (PC) ← (A) (PC) ← ext Vector call Subroutine call (PC) ← (A),(A) ← (PC) + 1 Return from subrountine Return form interrupt Table 5 TL TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – dH – – –––– –––– –––– –––– –––– –––– –––– –––– –+–– –+–– –––– –––– –––– –––– –––– –––– Restore FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30 Other Instructions (9 instructions) Operation TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – dH – – – – – – – –––– –––– –––– –––– –––– –––R –––S –––– –––– 40 50 41 51 00 81 91 80 90 L B C D E F MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP 5 A SUBC A XCH XOR AND OR A, T A A A MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX AND CMP MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BZ A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel R5 R5 #5 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BGE A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel R6 R6 #6 rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BLT A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel R7 R7 #7 rel D E F rel rel rel rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BNZ A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel R4 R4 #4 rel MOVW XCHW IX,#d16 A,IX C @IX +d,A MOVW MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BN A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel R3 R3 #3 A,@IX +d MOVW CLRB BBC MOVW MOVW MOVW XCHW dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP CLRB BBC dir: 6 dir: 6,rel B @EP,#d8 CMP @IX +d,#d8 @IX +d,#d8 MOV MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BP A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel R2 R2 #2 A,@IX +d OR A A,@IX +d A,@IX +d XOR MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel R1 R1 #1 +d,A MOV @IX 9 A,@IX +d SUBC MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BNC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel R0 R0 #0 rel A,@IX +d ADDC CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC 8 A,@IX +d A,@IX +d DAS MOV CMP ADDC SUBC MOV XOR AND OR MOV A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 CMP MOV XOR AND OR DAA A,#d8 A,#d8 A,#d8 7 6 MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8 ADDC CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP MOVW MOVW CLRB BBC INCW DECW MOVW MOVW CMPW ADDCW SUBCW XCHW XORW ANDW ORW A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP A A SETC 4 A CMP PUSHW POPW MOV JMP CALL MOVW CLRC IX addr16 addr16 IX ext,A PS,A RORC A DIVU 3 CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC A ROLC A SETI 7 PUSHW POPW MOV MOVW CLRI A A A,ext A,PS 6 9 5 8 4 2 A RETI 3 MULU RET 2 1 SWAP 1 NOP 0 0 H MB89810A Series ■ INSTRUCTION MAP 33 MB89810A Series ■ MASK OPTIONS No. Part number MB89816A MB89P817A Specifying procedure Specify when ordering masking Set with EPROM programmer 1 Pull-up resistors P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P54, P60 to P67 Specify by pin 2 Power-on reset selection With power-on reset Without power-on reset Selectable Setting possible Selectable Setting possible Can be set per pin. (P50 to P54 are available only for without a pull-up resistor.) Main clock oscillation (5 MHz) stabilization time selection approx. 218/FCH (approx. 52.4 ms) 3 approx. 217/FCH (approx. 26.2 ms) approx. 214/FCH (approx. 3.2 ms) approx. 24/FCH (approx. 0 ms) 4 Reset pin ouotput selection With reset output Without reset output Selectable Setting possible 5 Selection either single- or dualclock system Single clock Dual clock Selectable Setting possible 6 Main clock oscillator type selection Crystal or ceramic oscillator CR Selectable Setting possible FCH: Main clock frequency * : The main clock oscillation setting time is generated by dividing the main clock frequency. Note that the oscillation cycle is not stable immediately after oscillation is started. The settling time value in this data sheet should be used as a reference. ■ ORDERING INFORMATION Part number MB89816APF MB89P817APF 34 Package 64-pin Plastic QFP (FPT-64P-M06) Remarks MB89810A Series ■ PACKAGE DIMENSIONS 64-pin Plastic QFP (FPT-64P-M06) 24.70±0.40(.972±.016) 3.35(.132)MAX 20.00±0.20(.787±.008) 51 0.05(.002)MIN (STAND OFF) 33 52 32 14.00±0.20 (.551±.008) 18.70±0.40 (.736±.016) 12.00(.472) REF 16.30±0.40 (.642±.016) INDEX 20 64 "A" LEAD No. 19 1 0.40±0.10 (.016±.004) 1.00(.0394) TYP 0.15±0.05(.006±.002) 0.20(.008) M Details of "A" part 0.25(.010) Details of "B" part "B" 0.10(.004) 18.00(.709)REF 22.30±0.40(.878±.016) C 1994 FUJITSU LIMITED F64013S-3C-2 0.30(.012) 0.18(.007)MAX 0.63(.025)MAX 0 10° 1.20±0.20 (.047±.008) Dimensions in mm (inches) 35 MB89810A Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 1015, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211, Japan Tel: (044) 754-3753 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED No. 51 Bras Basah Road, Plaza By The Park, #06-04 to #06-07 Singapore 189554 Tel: 336-1600 Fax: 336-1609 All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. The information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support. F9606 FUJITSU LIMITED Printed in Japan 36