L4902A DUAL 5V REGULATOR WITH RESET AND DISABLE .. . . . . . .. .. .. DOUBLE BATTERY OPERATING OUTPUT CURRENTS : I01 = 300 mA I02 = 300 mA FIXED PRECISION OUTPUT VOLTAGE 5V± 2% RESET FUNCTION CONTROLLED BY INPUT VOLTAGE AND OUTPUT 1 VOLTAGE RESET FUNCTION EXTERNALLY PROGRAMMABLE TIMING RESET OUTPUT LEVEL RELATED TO OUTPUT 2 OUTPUT 2 INTERNALLY SWITCHED WITH ACTIVE DISCHARGING OUTPUT 2 DISABLE LOGICAL INPUT LOW LEAKAGE CURRENT, LESS THAN 1µA AT OUTPUT 1 RESET OUTPUT NORMALLY HIGH INPUT OVERVOLTAGE PROTECTION UP TO 60V OUTPUT TRANSISTORS SOA PROTECTION SHORT CIRCUIT AND THERMAL OVERLOAD PROTECTION HEPTAWATT (Vertical) ORDERING NUMBER : L4902A DESCRIPTION The L4902A is a monolithic low drop dual 5V regulator designed mainly for supplying microprocessor systems. Reset and data save functions and remote switch on/off control can be realized. PIN CONNECTION June 2000 1/9 L4902A PIN FUNCTIONS N° 1 2 Name 3 4 5 Input 1 Timing Capacitor Disable Input GND Reset Output 6 Output 2 7 Output 1 Function Regulators Common Input If Reg. 2 is switched-ON the delay capacitor is charged with a 5µA constant current. When Reg. 2 is switched-OFF the delay capacitor is discharged. A high level (> VDT) disable output Reg. 2. Common Ground When pin 2 reaches 5V the reset output is switched high. 5V ) ; tRD (ms) = Ct (nF) Therefore tRD = Ct ( 10µA 5V – 300mA Regulator Output. Enabled if Vo 1 > VRT. DISABLE INPUT < VDT and VIN > VIT. If Reg. 2 is switched-OFF the C02 capacitor is discharged. 5V – 300mA. Low leakage (in switch-OFF condition) output BLOCK DIAGRAM SCHEMATIC DIAGRAM 2/9 L4902A ABSOLUTE MAXIMUM RATINGS Symbol V IN Io Tstg, Tj Parameter Value Unit 28 60 V V DC Input Voltage Transient Input Overvoltage (t = 40ms) Output Current Internally Limited Storage and Junction Temperature – 40 to 150 °C Value Unit 4 °C/W THERMAL DATA Symbol Rth j-case Parameter Thermal Resistance Junction-case Max ELECTRICAL CHARACTERISTICS (VIN = 14.4V, Tamb = 25oC unless otherwise specified)) Symbol Vi V01 Parameter DC Operating Input Voltage Output Voltage 1 Test Conditions Min. Typ. Max. 24 Unit V R Load 1kΩ 4.95 R Load 1kΩ I02 = – 5mA V01 –0.1 5.05 5 5.15 V01 V V V02 H Output Voltage 2 HIGH V02 L I01 Output Voltage 2 LOW Output Current 1 max. IL01 Leakage Output 1 Current VIN = 0, V01 ≤ 3V I02 Output Current 2 max. Vi01 Output 1 Dropout Voltage (*) ∆V02 = – 100mV I01 = 10mA I01 = 100mA I01 = 300mA VIT ViTH ∆V01 Input Threshold Voltage Input Threshold Voltage Hyst. Line Regulation 1 7V < VIN < 24V, I 01 = 5mA 0.7 0.8 1.1 6.4 250 5 ∆V02 Line Regulation 2 7V < VIN < 24V, I 02 = 5mA 5 50 mV ∆V01 Load Regulation 1 5mA < I01 < 300mA 40 80 mV ∆V02 IQ Load Regulation 2 5mA < I02 < 300mA 50 80 Quiescent Current I01 = I02 ≤ 5mA 0 < VIN < 13V 7V < VIN < 13V V02 LOW 7V < VIN < 13V V02 HIGH VRT VRTH VRH ∆V01 = – 100mV 0.1 V mA 300 1 µA mA 0.8 1 1.4 V01 + 1.7 V V V V mV mV 300 V01 + 1.2 50 mV mA 4.5 2.7 1.6 6.5 4.5 3.5 V 02 – 0.15 30 V02 – 1 4.9 50 4.12 V02 – 0.05 80 V02 V mV V 3 0.25 5 0.4 11 20 V ms 2.4 VD ≤ 0.4V VD ≥ 2.4V 1.25 – 150 – 30 Reset Threshold Voltage Reset Threshold Hysteresis Reset Output Voltage HIGH VRL tRD td IR = 500µA Reset Output Voltage LOW IR = – 1mA Reset Pulse Delay C t = 10nF Timing Capacitor Discharge Time Ct = 10nF VDT ID V02 Disable Threshold Voltage V02 Disable Input Current ∆V01 ∆T Thermal Drift – 20°C ≤ Tamb ≤ 125°C 0.3 – 0.8 mV/°C Thermal Drift – 20°C ≤ Tamb ≤ 125°C 0.3 – 0.8 mV/°C Supply Voltage Rejection f = 100Hz VR = 0.5V Io = 100mA 50 84 dB 50 80 dB ∆V02 ∆T SVR1 SVR2 Supply Voltage Rejection µs V µA µA * The dropout voltage is defined as the difference between the input and the output voltage when the output voltage is lowered of 25 mV under constant output current condition. 3/9 L4902A TEST CIRCUIT APPLICATION INFORMATION In power supplies for µP systems it is necessary to provide power continuously to avoid loss of information in memories and in time of day clocks, or to save datawhen the primary supply is removed.The L4902A makes it very easy to supply such equipments ; it provides two voltage regulators (both 5V high precision) with common inputs plus a reset output for the data save function and a Reg. 2 disable input. CIRCUIT OPERATION (see Figure 1) After switch on Reg. 1 saturates until V 01 rises to the nominal value. When the input reaches VIT and the output 1 is higher than VRT the output 2 (V02) switches on and the reset output (VR) also goes high after a proFigure 1 4/9 grammable time TRD (timing capacitor). V02 and VR are switched togetherat low level when one of the following conditions occurs : - a high level ( VDT) is applied on pin 3 ; - an input overvoltage ; - an overload on the output 1 (V01 VRT) ; - a switch off (VIN VIT - VITH) ; and they start again as before when the condition is removed. An overload on output 2 does not switch Reg. 2, and does not influence Reg. 1. The V01 output features : - 5V internal reference without voltage divider between the output and the error comparator - very low drop series regulator element utilizing current mirrors permit high output impedance and then very low leakage current even in power down condition. L4902A This output may thereforebe usedto supply circuits continuously, such as volatile RAMs, allowing the use of a back-up battery. The V02 output can supply other non essential 5 V circuits which may be powered down when the system is inactive, or that must be powered down to prevent uncorrect operation for supply voltages below the minimum value. The reset output can be usedas a ”POWERDOWN INTERRUPT”, permitting RAM access only in correct power conditions, or as a ”BACK-UP ENABLE” to transfer data into in a NV SHADOW MEMORY when the supply is interrupted. The disable function can be used for remote on/off control of circuits connected to the V 02 output. APPLICATION SUGGESTIONS Figure 2 illustrate how the L4902A’s disable input may be used in a CMOS µComputer application. TheV01 regulator(low consumption)supply permanently a CMOS time of day clock and a CMOS µcomputer chip with volatile memory. V02 output, supplying non-essential circuits, is turned OFF under control of a µP unit. Figure 2 Figure 3 : P.C. Board Component Layout of Figure 2 5/9 L4902A Configurations of this type are used in products where the OFF switch is part of a keyboard scanned by a micro which operates continuously even in the OFF state. Another application for the L4902A is supplying a shadow-ram microcomputer chip (SGS M38SH72 for example)where a fast NV memory is backedup on chip by a EEPROMwhen a low level on the reset output occurs. By adding two CMOS-SCHMIDT-TRIGGER and few external components, also a watch dog funcFigure 4 Figure 5 6/9 tion may be realized (see Figure 5). During normal operation the microsystem supplies a periodical pulse waveform;if an anomalousconditionoccours (in the program or in the system), the pulses will be absent and the disable input will be activated after a settling time determined by R1 C1. In this condition all the circuitry connected to V02 will be disabled, the system will be restarted with a new reset front. The disable of V02 prevent spurious operation during microprocessor malfunctioning. L4902A Figure 6 : Quiescent Current versus Output ICurrent Figure 8 : Supply Voltage Rejection Regulators 1 and 2 versus Input Ripple Frequence Figure 7 : Quiescent Current versus Input Voltage 7/9 L4902A DIM. A C D D1 E E1 F F1 G G1 G2 H2 H3 L L1 L2 L3 L4 L5 L6 L7 L9 M M1 V4 Dia MIN. mm TYP. 2.4 1.2 0.35 0.7 0.6 2.34 4.88 7.42 10.05 16.7 21.24 22.27 2.6 15.1 6 2.55 4.83 2.54 5.08 7.62 16.9 14.92 21.54 22.52 2.8 15.5 6.35 0.2 2.8 5.08 3.65 MAX. 4.8 1.37 2.8 1.35 0.55 0.97 0.8 0.9 2.74 5.28 7.82 10.4 10.4 17.1 inch TYP. MIN. 0.094 0.047 0.014 0.028 0.024 0.095 0.193 0.295 0.396 0.657 21.84 22.77 1.29 3 15.8 6.6 0.386 0.877 0.102 0.594 0.236 3.05 5.33 40° 3.85 0.100 0.190 (typ.) 0.144 0.100 0.200 0.300 0.668 0.587 0.848 0.891 0.110 0.610 0.250 0.008 0.110 0.200 OUTLINE AND MECHANICAL DATA MAX. 0.189 0.054 0.110 0.053 0.022 0.038 0.031 0.035 0.105 0.205 0.307 0.409 0.409 0.673 0.860 0.896 0.051 0.118 0.622 0.260 0.120 0.210 Heptawatt V 0.152 V L V E L1 M1 A M D C D1 L5 H2 L2 L3 F E E1 V4 L9 H3 H1 G G1 G2 Dia. F L7 L4 L6 8/9 H2 F1 HEPTAMEC L4902A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent right s of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as criticalcomp onents in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 9/9