L4904A DUAL 5V REGULATOR WITH RESET . . . . . . . .. .. . OUTPUT CURRENTS : I01 = 50mA I 02 = 100mA FIXED PRECISION OUTPUT VOLTAGE 5V ± 2 % RESET FUNCTION CONTROLLED BY INPUT VOLTAGE AND OUTPUT 1 VOLTAGE RESET FUNCTION EXTERNALLY PROGRAMMABLE TIMING RESET OUTPUT LEVEL RELATED TO OUTPUT 2 OUTPUT 2 INTERNALLY SWITCHED WITH ACTIVE DISCHARGING LOW LEAKAGE CURRENT, LESS THAN 1µA AT OUTPUT 1 LOW QUIESCENT CURRENT (Input 1) INPUT OVERVOLTAGE PROTECTION UP TO 60V RESET OUTPUT NORMALLY HIGH OUTPUT TRANSISTORS SOA PROTECTION SHORT CIRCUIT AND THERMAL OVERLOAD PROTECTION Minidip ORDERING NUMBER : L4904A DESCRIPTION The L4904A is a monolithic low drop dual 5V regulator designed mainly for supplying microprocessor systems. Reset and data save functions during switch on/off can be realized. PIN CONNECTION June 2000 1/9 L4904A PIN FUNCTIONS N° 1 2 3 Name Input 1 Input 2 Timing Capacitor 4 5 6 GND N.C. Reset Output 7 Output 2 8 Output 1 Function Low Quiescent Current 50mA Regulator Input. 100mA Regulator Input. If Reg. 2 is switching-ON the delay capacitor is charged with a 10µA constant current. When Reg. 2 is switched-OFF the delay capacitor is discharged. Common Ground. Not connected. When pin 3 reaches 5V the reset output is switched high. 5V Therefore tRD = Ct ( ); tRD (ms) = Ct (nF). 10µA 5V – 100mA Regulator Output. Enabled if Vo 1 > VRT and VIN 2 > VIT. If Reg. 2 is switched-OFF the Co2 capacitor is discharged. 5V – 50mA regulator output with low leakage in switch-OFF condition. BLOCK DIAGRAM SCHEMATIC DIAGRAM 2/9 L4904A ABSOLUTE MAXIMUM RATINGS Symbol V IN Io Ptot Tj Parameter DC Input Voltage Transient Input Overvoltage (t = 40ms) Output Current Power Dissipation at Tamb = 50°C Storage and Junction Temperature Value 24 60 Internally Limited 1 Unit V V – 40 to 150 °C Value Unit 100 °C/W W THERMAL DATA Symbol Rth j-amb Parameter Thermal Resistance Junction-ambient Max ELECTRICAL CHARACTERISTICS (VIN = 14.4V, Tamb = 25oC unless otherwise specified) Symbol Parameter Vi DC Operating Input Voltage V01 Output Voltage 1 V02 H Output Voltage 2 HIGH V02 L I01 Output Voltage 2 LOW Output Current 1 IL01 Leakage Output 1 Current I02 Output Current 2 VI01 Output 1 Dropout Voltage (*) VIT VITH ∆V01 Input Threshold Voltage Input Threshold Voltage Hyst. Line Regulation ∆V02 Line Regulation 2 ∆V01 Load Regulation 1 ∆V02 IQ IQ1 Test Conditions R Load 1kΩ R Load 1kΩ I02 = – 5mA ∆V01 = – 100mV Typ. 5.05 Max. 20 5.15 Unit V V 4.95 V01 –0.1 5 V01 V 0.1 V mA 50 1 µA mA 0.8 0.9 V01 + 1.7 7V < VIN < 18V, I01 = 5mA 0.7 0.75 6.4 250 5 50 V V V mV mV 7V < VIN < 18V, I02 = 5mA 5 50 mV VIN = 8V, 5mA < I01 < 50mA 5 20 mV Load Regulation 2 VIN = 8V, 5mA < I02 < 100mA 10 50 mV Quiescent Current I02 = I01 ≤ 5mA 0 < VIN < 13V 7V < VIN < 13V 6.3V < VIN1 < 13V, VIN2 = 0 I01 ≤ 5mA, I02 = 0 4.5 1.6 6.5 3.5 0.6 0.9 mA 4.9 50 4.12 V02 – 0.05 80 V02 V mV V 0.25 0.4 11 20 V ms Quiescent Current 1 VIN = 0, V01 ≤ 3V ∆V02 = – 100mV Min. 100 I01 = 10mA I01 = 50mA V01 + 1.2 mA VRT VRTH VRH Reset Threshold Voltage Reset Threshold Hysteresis Reset Output Voltage HIGH VRL tRD td Reset Output Voltage LOW Reset Pulse Delay Timing Capacitor Discharge Time ∆V01 ∆T Thermal Drift – 20°C ≤<0>Tamb ≤ 125°C 0.3 –0.8 mV/°C ∆V02 ∆T Thermal Drift – 20°C ≤<0>Tamb ≤ 125°C 0.3 – 0.8 mV/°C SVR1 SVR2 Supply Voltage Rejection Supply Voltage Rejection f = 100Hz, VR = 0.5V, Io = 50mA f = 100Hz, VR = 0.5V, Io = 100mA 84 80 dB dB IR = 500µA IR = – 5mA Ct = 10nF Ct = 10nF V02 –0.15 30 V02 – 1 3 50 50 µs * The dropout voltage is defined as the difference between the input and the output voltage when the output voltage is lowered of 25 mV under constant output current condition. 3/9 L4904A TEST CIRCUIT Figure 1 : P.C. Board and Components Layout of the Test Circuit (1:1 scale) APPLICATION INFORMATION In power supplies for µP systems it is necessary to provide power continuously to avoid loss of information in memories and in time of day clocks, or to save datawhen the primary supply is removed.The L4904A makes it very easy to supply such equipments ; it provides two voltage regulators (booth 5V high precision) with separate inputs plus a reset output for the data save function. CIRCUIT OPERATION (see Figure 2) After switch on Reg. 1 saturates until V 01 rises to the nominal value. When the input 2 reaches VIT and the output 1 is higher than VRT the output 2 (V02) switches on and the reset output (VR) also goes high after a programmable time TRD (timing capacitor). V02 and VR are switched together at low level when one of the following conditions occurs : - an input overvoltage - an overload on the output 1 (V01 < VRT) ; - a switch off (VIN < VIT - VITH ) ; and they start again as before when the condition is removed. 4/9 An overload on output 2 does not switch Reg. 2, and does not influence Reg. 1. The V01 output features : - 5 V internal reference without voltage divider between the output and the error comparator ; - very low drop series regulator element utilizing mirrors ; permit high output impedance and then very low leakage current even in power down conditions. This output may thereforebe used to supply circuits continuously, such as volatile RAMs, allowing the use of a back-up battery. The V01 regulator also features low consumption (0.6 mA typ.)to minimize battery drain in applicationswhere the V1 regulator is permanently connected to a battery supply. The V02 output can supply other non essential 5 V circuits which may be powered down when the system is inactive, or that must be powered down to prevent uncorrect operation for supply voltages below the minimum value. Thereset output can be usedas a ”POWER DOWN INTERRUPT”, permitting RAM access only in correct powerconditions,or as a ”BACK-UPENABLE” to transfer data into in a NV SHADOW MEMORY when the supply is interrupted. L4904A Figure 2 APPLICATION SUGGESTIONS Figure 3 shows an application circuit for a µP system. Reg. 1 is permanently connected to a battery and supplies a CMOS time-of-day clock and a CMOS microcomputer chip with volatile memory. Reg. 2 may be switched OFF when the system is inactive. Figure 4 shows the L4904A with a back up battery on the V01 output to maintain a CMOS time-of-day clock and a stand by type C-MOS µP. The reset output makes sure that the RAM is forced into the low consumption stand by state, so the access to memory is inhibit and the back up battery voltage cannot drop so low that memory contents are corrupted. In this casethe main on-off switch disconnects both regulators from the supply battery. Application Circuits of a Microprocessor system (Figure 3) or with data save battery (Figure 4). The reset output provide delayed rising front at the Figure 3 5/9 L4904A Figure 4 6/9 L4904A Figure 5 : Quiescent Current (reg. 1) versus Output Current Figure 6 : Quiescent Current (reg. 1 versus Input Voltage Figure 7 : Total Quiescent Current versus Input Voltage Figure 8 : Supply Voltage Rejection Regulators 1 and 2 versus Input Ripple Frequence 7/9 L4904A mm DIM. MIN. A TYP. MAX. MIN. 3.32 TYP. MAX. 0.51 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 E 0.020 10.92 7.95 9.75 0.430 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0.260 I 5.08 0.200 L Z 3.18 OUTLINE AND MECHANICAL DATA 0.131 a1 D 8/9 inch 3.81 1.52 0.125 0.150 0.060 Minidip L4904A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent right s of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as criticalcomp onents in life support devices or systems without express written approval of STMicroelectronics. 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