L6238S 12V SENSORLESS SPINDLE MOTOR CONTROLLER PRODUCT PREVIEW 12V OPERATION 3A, THREE-PHASE DMOS OUTPUT (TOTAL Rdson 0.52Ω) NO HALL SENSORS REQUIRED DIGITAL BEMF PROCESSING LINEAR OR PWM CONTROL STAND ALONE OR EXT. DRIVER SHOOT-THROUGH PROTECTION THERMAL SHUTDOWN PLCC44 PQFP44 DESCRIPTION The L6238S is a Three-Phase, D.C. Brushless Spindle Motor Driver system. This device features both the Power and Sequence Sections. Higher Power Applications can be activied with the addition of an external Linear Driver, or by operating the Internal Drivers in PWM. Motor Start-Up, without the use of Hall Sensors, can be achieved either by an internal start-up algorithm or by manually sequencing the Output Drivers, using a variety of User-Defined Start-UP Algorithms. TQFP64 ORDERING NUMBERS: L6238S (PLCC44) L6238SQA (PQFP44) L6238SQT (TQFP64) Protection features include Stuck Rotor\Backward Rotation Detection and Automatic Thermal Shutdown. BLOCK DIAGRAM VL FALIGN OUTPUT ENABLE RUN/ BRAKE PWM/ SLEW PWM COMP PWM LIN PWM TIM CHARGE PUMP VANALOG BIAS ONE-SHOT SLEW-CTRL SYSTEM CLOCK VPOWER ALIGN + GO START-UP BRAKE DELAY SEQ INCR MONO/SEQ CTRL SEQUENCER TDLY(0) TDLY(1) DIGITAL DELAY TDLY(2) MONO DET ZERO CROSSING DETECTOR + OUT A BEMF + SENSE + OUT B OUT C - MASK DLY SPIN SENSE CPUMP2 CPUMP3 POWER STAGE SYS CLOCK CPUMP1 RSENSE1 DIVIDE BY N TOGGLE CTR TAP + RSENSE2 - OT-WARN DRV CNTL THERMAL SHUTDOWM GND AV=4V/V CSA SEL POL October 1995 FMTR VCTRL GM COMP GATE DRIVE CSA INPUT D95IN232 1/31 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. L6238S ABSOLUTE MAXIMUM RATINGS Symbol Value Unit BVdss Output Brakdown Voltage 17 V VPower Motor Supply Voltage 15 V VLogic Logic Supply Voltage 7 V VAnalog Analog Supply Voltage 15 V -0.3 to 7 V Vin Parameter Input Voltage Charge Pump Storage Capacitor 4.7 µF Imdc Motor Current (DC) (TQFP64 only) (PLCC44 and PQFP44) 3 2.5 A A Impk Peak Motor Current (Pulsed: Ton = 5ms, d.c. = 10%) Ptot Power Dissipation at Tamb = 50 °C (PLCC44) (TQFP64) (PQFP44) Ts Storage and Junction Temperature C storage 5 A 2.3 1.7 1.3 W W W -40 to 150 °C THERMAL DATA Symbol R th (j-amb) Parameter PLCC44 PQFP44 TQFP64 Unit 34 45 45 °C/W Thermal Resistance Junction-Ambient Those Thermal Data are valid if the package is mounted on Mlayer board in stillair OUTPUT B 2 1 44 43 42 41 40 GND SPIN SENSE 3 MASK DELAY BRAKE DELAY 4 VPOWER RSENSE 1 5 CENTER TAP CHARGE PUMP 2 6 PWM/SLEW GND PIN CONNECTION PLCC44 (Top view) GND 7 39 GND CHARGE PUMP 1 8 38 GATE DRIVE CHARGE PUMP 3 9 37 GM COMP OUTPUT A 10 36 OUTPUT C VPOWER 11 35 RSENSE 2 VANALOG 12 34 CSA INPUT N.C. 13 33 VCONTROL TDLY(0) 14 32 N.C. TDLY(1) 15 31 FMOTOR TDLY(2) 16 30 VLOGIC GND 17 29 GND PWM COMP FALIGN MONO/SEQINC CTRL SYSTEM CLOCK SEQ. INCREMENT RUN/BRAKE OUTPUT ENABLE PWM/LINEAR PWM LIMIT TMR OTWARN 2/31 SELECT POLE 18 19 20 21 22 23 24 25 26 27 28 D95IN245 L6238S TDLY(1) TDLY(0) N.C. VANALOG VPOWER OUTPUT A CHARGE PUMP 3 CHARGE PUMP 1 GND 11 10 9 8 7 6 5 4 3 2 1 GND TDLY(2) PIN CONNECTION PQFP44 (10x10) (Top view) OTWARN 12 44 GND SELECT POLE 13 43 CHARGE PUMP 2 PWM LIMIT TIMER 14 42 RSENSE 1 PWM/LINEAR 15 41 BRAKE DELAY OUTPUT ENABLE 16 40 SPIN SENSE RUN/BRAKE 17 39 OUTPUT B SEQ. INCREMENT 18 38 PWM/SLEW SYSTEM CLOCK 19 37 CENTER TAP MONO/SEQINC CTRL 20 36 VPOWER FALING 21 35 MASK/DELAY PWM COMP. 22 34 GND OUTPUT C GM COMP OUTPUT A OUTPUT A CHARGE PUMP 3 CHARGE PUMP 1 GND GND GND 3 2 1 GND GATE DRIVE RSENSE 2 N.C. 4 CSA INPUT VPOWER 5 N.C. 6 FMOTOR 7 TDLY(0) 8 GND 9 VLOGIC 16 15 14 13 12 11 10 TDLY(1) VPOWER VCONTROL 23 24 25 26 27 28 29 30 31 32 33 D95IN243 VANALOG TDLY(2) GND GND PIN CONNECTION TQFP64 (Top view) GND 17 64 GND N.C. 18 63 GND N.C. 19 62 CHARGE PUMP 2 OTWARN 20 61 RSENSE 1 SELECT POLE 21 60 RSENSE 1 PWM LIMIT TMR 22 59 BRAKE DELAY PWM/LINEAR 23 58 SPIN SENSE OUTPUT ENABLE 24 57 OUTPUT B RUN/BRAKE 25 56 OUTPUT B SEQ. INCREMENT 26 55 PWM/SLEW SYSTEM CLOCK 27 54 CENTER TAP MONO/SEQINC CTRL 28 53 VPOWER FALIGN 29 52 VPOWER PWM COMP 30 51 MASK DELAY N.C. 31 50 GND GND 32 49 GND GND GND GND GATE DRIVE GM COMP OUTPUT C N.C. OUTPUT C RSENSE 2 RSENSE 2 CSA INPUT VCONTROL FMOTOR VLOGIC GND GND 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 D95IN244 3/31 L6238S PIN FUNCTIONS PLCC44 PQFP44 TQFP64 Name I/O Function 1 39 56, 57 OUTPUT B I/O DMOS Half Bridge Output and Input B for Bemf sensing. 2 40 58 SPIN SENSE O Toggless at each Zero Crossing of the Bemf. 3 41 59 BRAKE DELAY I Energy Recovery time constant, defined by external R-C to ground. 4 42 60, 61 R sense 1 O Outputs A+B connections for the Motor Current Sense Resistor to ground 5 43 62 CHARGE PUMP 2 I Negative Terminal of Pump Capacitor. 6, 7, 17, 29, 39, 40 1, 11, 23, 33, 34, 44 * GROUND S Ground terminals. 8 2 4 CHARGE PUMP 1 I Positive terminal of Pump Capacitor. 9 3 5 CHARGE PUMP 3 O Positive terminal of Storage Capacitor. 10 4 6, 7 OUTPUT A I/O DMOS Half Bridge Output and Input A for Bemf sensing. 11, 42 5, 36 9, 10, 52, 53 Vpower S Power Section Supply Terminal. 12 6 11 Vanalog S 12V supply. 13, 32 7, 26 8, 18, 19, 31, 41 N.C N.C 14 8 12 Tdly(0) I 15 9 13 Tdly(1) I 16 10 14 Tdly(2) I 18 12 20 OTWARN O Overtemperature Warning Output 19 13 21 SELECT POLE I Selects # of Motor Poles. A zero selects 8, while a one selects 4 poles. 20 14 22 PWM TIMER I Capacitor connected to this pin sets the maximum time allowed for 100% duty cycle during PWM operation 21 15 23 PWM/LINEAR I Selects PWM or Linear Output Current Control 22 16 24 OUTPUT ENABLE I Tristates Power Output Stage when a logic zero. 23 17 25 SEQUENCE I Rising edge will initiate start-up. A Braking rountine is started when this input is brought low. 24 18 26 SEQ INCREMENT I A low to high transition on this pin increments the Output State Sequencer. 25 19 27 SYSTEM CLK I Clock Frequency for the system timer/counters. 26 20 28 MONO/SEQ. INC. CONTROL I A logic one will disable the Monotonicity Detector and Sequence Increment functions. 27 21 29 Falign I Reference Frequency for the opt. Auto-Start Algorithm. If int. start up is not used, this pin must be connected to the System Clock. 28 22 30 PWM COMP O Output of the PWM Comparator 30 24 35 Vlogic S 5V Logic Supply Voltage. 31 25 36 Fmotor O Motor Once-per-Revolution signal. 33 27 37 Vcontrol I Voltage at this input controls he Motor Current 34 28 38 CSA INPUT I Input to the Current Sense Amplifier. 35 29 39, 40 Rsense 2 O Output C connection for the Motor Current Sense Resistor to ground. 36 30 42, 43 OUTPUT C I/O 37 31 44 gm COMP I 4/31 Open Terminal Three bits that set the Delay between the detection of the Bemf zero crossing, and the commutation of the next Phase. DMOS Half Bridge Output and Input C for Bemf sensing. A series RC network to ground that defines the compensation of the Transconductance Loop. L6238S PIN FUNCTIONS PLCC44 PQFP44 TQFP64 Name I/O Function 38 32 45 GATE DRIVER I/O Drivers the Ext. PFET Gate Driver for Higher Power applications. This pin must be grounded if an external driver is not used. 41 35 51 MASK/DELAY O Internal Logic Signals used for production Testing 43 37 54 CENTER TAP I Motor Center Tap used for differential BEMF sensing. 44 38 55 PWM/SLEW I R/C at this input set the Linear Slew Rate and PWM OFF-Time Figure 1: Brake Delay Timeout vs Cbrake (Rbrake = 1Meg) TBD (s) Figure 2: Linear Slew Rate vs Rslew D95IN274 SVR (V/µs) 3.0 3.0 1.0 1.0 0.3 0.3 0.0 0.0 0.0 0.3 1.0 3.0 Cb(µF) Figure 3: PWM Off - Time vs Rslew/Coff PWM (µs) 10 D95IN275 30 100 300 Rs(KΩ) Figure 4: PWM Limit Time - Out vs Ctimer D95IN276 PWM (µs) D95IN277 30 10 30 3 1 100 300 Coff(pF) 10 100 300 Ctimer(pF) 5/31 L6238S ELECTRICAL CHARACTERISTICS (Tamb = 0 to 70°C; VA = VPwr = 12V; Vlogic = 5V; unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit 13.5 V GENERAL Vanalog Analog Supply Voltage Ianalog Analog Supply Current 10.5 Run Mode VA = 13.5V 1.5 2.7 4.5 mA 280 800 µA 4.5 5.0 5.5 V 1 2 3.2 mA 100 500 1000 µA 180 °C Brake Mode VA = 13.5V Vlogic Logic Supply Voltage Ilog ic Logic Supply Current Run Mode Vlogic = 5.5V Brake Mode THERMAL SHUTDOWN * Tsd Shut Down Temperature * Thys Recovery Temperature Hysteresis * Tew Early Warning Temperature 150 30 °C Tsd-25 °C POWER STAGE RDS(on) Output ON Resistance per FET Tj = 25°C; VA = 10.5V Tj = 125°C; VA = 10.5V Io(leak) 0.20 Output Leakage Current Vpwr = 15V VF Body Diode Forward Drop Im = 2.0A dVo/dt Output Slew Rate (Linear) Rslew = 100KΩ 0.15 Vcontrol = 1V; Vsns = 0V; VA = 10.5V 4.5 Output Slew Rate (PWM) Igt Gate Drive for Ext. Power DMOS VGate-Drive Ext Driver Disable Voltage VCtrl-Range Voltage Control Input Range Iin(VCtrl) Voltage Control Input Current 0.30 10 0.26 0.40 Ω Ω 1 mA 1.5 V 0.45 V/µs 150 V/µs mA 0.7 0 V 5.0 V 10 µA PWM OFF-TIME CONTROLLER (Rslew = 100KΩ, Coff = 120pF) Toff OFF Time Vchrg Capacitor Charge Voltage Vtrip Lower Trip Threshold VA = 10.5V 9 11 14 µs 2.31 2.65 3.1 V 1.25 V PWM LIMIT TIMER Ichrg Capacitor Charge Current VPWM Timer = 0V; VA = 10.5V 10.0 Vchrg Capacitor Charge Voltage VA = 10.5V 3.0 Vtrip Lower Trip Threshold 20.0 30 µA 3.5 4.0 mV 100 400 V 30 40 BEMF AMPLIFIER ZinCT Center Tap Imput Impedance 20 VBemf Minimum Bemf (Pk-Pk) 60 KΩ mV CURRENT SENSE AMPLIFIER Isnsin 6/31 Input Bias Current VA = 13.5V Gv Voltage Gain 3.8 4.0 SR Slew Rate 0.33 0.8 10 µA 4.2 V/V V/µs L6238S ELECTRICAL CHARACTERISTICS (Continued) Symbol Parameter Test Condition Min. Typ. Max. Unit 8.8 9.6 10.5 V 500 nA BRAKE DELAY Vchrg Iin Iout3 Capacitor Charge Voltage RT = 50K Input Current Vin = 5.0V Source Current VA = 10.5V Delay Timer Low Trip Threshold VThres 0.5 1.2 mA 1.8 2.8 V CHARGE PUMP Vout Storage Capacitor Output Voltage VA = 10.5V; Iout = 500µA Fcp Charge Pump Frequency Iin Vstorage Input Current (Run Mode) Vstorage = 12V; VA = Vlogic = 0 Ibrkdly Vstorage Leakage Current (Brake Delay Mode) Vstorage = 12V; VA = Vlogic = 0 Ibrake Vstorage Leakage Current (Brake Mode) Vstorage = 12V; VA = Vlogic = 0 17 V 140 450 KHz 25 µA 0.4 1 µA 0.1 1 µA SEQUENCE INCREMENT tseq Time Between Rising Edges µs 1 OUTPUT TRANSCONDUCTANCE AMPLIFIER Note: Measure at OTA Comp. pin. Voh Voltage Output High VoutL Output Voltage Isource Output Voltage 40.0 Output Sink Current 40.0 Isink VA = 10.5V 10 V 2.0 V 0.5 V µA LOGIC SECTION VinH VinL Input Voltage (All Inputs Except Run/Brake Vlogic = 4.5 to 5.5V VinH VinL Run/Brake Input Voltage Vlogic = 4.5 to 5.5V IinH IinL Input Current 3.5 1.5 V V 1.0 V V 2.0 1.0 µA mA 0.5 V V 12.0 MHz -1.0 VoutL VinL Output Voltage Fsys System Clock Frequency 8.0 Clock ON/OFF Time 20 toff /ton Vsink = 2.0mA Vsource = 2.0mA 4.5 ns Phase Delay Truth Table Tdelay (2) Tdelay (1) Tdelay (0) Commutation Phase Delay, in Electrical Degrees 1 0 1 2.0 1 0 0 9.4 1 1 1 18.80 1 1 0 20.68 0 0 1 22.56 0 0 0 24,44 (*) 0 1 1 26.32 0 1 0 28.20 (*) Input Default 7/31 8/31 6.33 8.12MHz 27 25 8 5 34 4.35 36 1 43 10 SYS CLK CHRG PUMP 1 10nF CHRG PUMP 2 CSA RSENSE OUT C OUT B CTR TAP OUT A F ALIGN CHRG PUMP 3 4.7µF VANLG MONO SEQ. 38 L6238S 12 GATE DRV 26 9 400pF PWM SLEW 100K GM COMP 44 37 BRK DLY 10K SPINDLE MOTOR DRIVER 11,42 VPWR 22µF 0.068µF 3 39 16 15 14 18 31 34 33 23 22 GND 20 6,7,17, 29,39,40 V LOGIC data(3) data(4) SEQ INC F MTR PWM TMR T DLY(2) T DLY(1) T DLY(0) 10K 43 POR VPUMP 41 1µF 3 14 9 37 L6244 44 Vpower CP1 0.01µF CP2 31 Rprogram V PROG VOICE COIL DRIVER 35 GATE DRIVE 6,7,17,29,39,40 18 27 28 36 26 25 24 23 22 21 20 19 0.068µF POR DLY GND CS A1 A0 WR data(7) data(6) data(5) data(2) VCTRL CONTROLLER data(1) OT WARM data(0) RUN/BRK VLOGIC OUT ENA 220pF VLOGIC(5V) 33 42 V CC/2 10 15 11 13 14 12 8 5 4 38 3.6K Rs 0.4 360K D95IN278 GAIN2-IN DA0Out GAIN1-IN 100K 10K 360K ERROR AMP OUTPUT DA2OUT SENSE OUT 360K OUT B SENSE +INPUT SENSE -INPUT OUT A V CC SENSE 27K VCM 0.1µF FUNCTIONAL DESCRIPTION 1.0 INTRODUCTION 1.1 Typical Application In a typical application, the L6238S will operate in conjunction with the L6244 Voice Coil Driver as 0.1µF 60-90Hz 12V Note: If the internal Start-up Algorithm is not used, connect this pin to SYS_CLK L6238S shown in Fig. 1-1. This configuration requires a minimum amount of external components. 1.2 Input Default States Figure 1-2 depicts the two possible input structures for the logic inputs. If a particular pin is not Figure 1-1 L6238S Figure 1-2 VLOGIC VLOGIC 10µA 330 330 10µA PULL-UP D95IN279 PULL-DOWN used in an application, it may either be connected to ground or VLOGIC as required, It may also be simply left unconnected. If no connection is made, the pin is either pulled high or low by internal constant current generators as shown above. A listing of the logic and clock inputs is shown in Table 1 with the corresponding default state. Table 1 Pin Function Configuration Tdly (0,1,2) Pull-Down Select Pole Pull-Down PWM/Linear Pull-Down Output Enable Pull-Down Run/Brake Pull-Up Sequence Increment Pull-Down System Clock Pull-Up Faling Pull-Up 1.3 Modes of Operation There are 5 basic modes of operation. 1) Tristate When Output Enable is low, the output power drivers are tristated. 2) Start-Up With Output Enable high, bringing Run/Brake from a low to a high will energize the motor and the system will be driven by the Fully-Integrated StartUp Algorithm. A user-defined Start-Up Algorithm, under control of a MicroProcessor, can also be achieved via the sequence increment input. 3) Run Run mode is achieved when the motor speed (controlled by the external microprocessor) reaches the nominal speed. 4) Park When Run/Brake is brought low, energy to park the heads may be derived from the rectified Bemf. The energy recovery time is a function of the Brake Delay Time Constant. In this state, the quiescent current of the device is minimized (sleep mode). 5) Brake After the Energy Recovery Time-Out, the device is in Brake, with all lower Drivers in full conduction. There are two mutually exclusive conditions which may be present during the Tristate Mode (wake up): a)the spindle is stopped. b)the system is still running at a speed that allows for resynchronization. In order to minimize the ramp up time, the microcontroller has the possibility to: check the SPIN SENSE pin, (which toggles at the Bemf zero crossing frequency) enable the power to the motor based on the previous information. Otherwise the µP may issue a Brake command, followed by the startup procedure after the motor has stopped spinning. 2.0 STATE DIAGRAMS 2.1 State Diagram Figure 2-1 is a complete State Diagram of the controller depicting the operational flow as a function of the control pins and motor status. The flow can be separated into four distinct operations. 2.2 Align + Go Figure 2-2 represent the normal flow that will achieve a spin-up of the spindle motor using the internally generated start up algorithm. Upon power up, or from any state with Run/Brake low the controller first sets the state machine for State=1 with the Outputs Tristated. The period counter that monitors the time between zero crossing is stopped, analog with the phase and mask delay counters. When Run/Brake is brought high, the motor is in the first part of the align mode at State 2 (Output A high and Output C low). If Output Enable is high, the controller first checks to determine if the motor is still spinning for a time of 21Ω (with Sys_Clk = 10MHz). The drivers are now enabled and after the align time-out, (64/Falign), the sequencer double increments the outputs to State 4 (Output B high and Output A low). The first part of this align mode is used to reduce the effects of stiction 9/31 L6238S Figure 2-1 POR=0 FROM ANY STATE (FOR IS GENERATED INTERNALLY BY MONITORING VLOGIC) RUN/BRAKE=0 FROM ANY STATE SEQLNC=1 & OUTENA=0 RUN/BRK=X STATE = 1 DRIVERS OFF MIN CLOCK DELAY PERIOD STOP DELAY STOP MASK STOP INT. START-UP DISABLED MIN. CLOCK DELAY LOAD MIN. DELAY LOAD MIN. MASK*** RUN/BRK=1 & OUTENA=1 RUN/BRAKE=1 DRIVERS ON PERIOD COUNT DELAY COUNT SEQINC=0 SEQINC=1 STATE=STATE+1* MASK COUNT SEQINC=0 MASK COUNT BEMF BEMF SEQINC=1 LOAD DELAY=PERIOD LOAD MASK=PERIOD RESET PERIOD PERIOD COUNT DELAY COUNT** SEQINC=1 STATE=STATE+2 OUTENA=1 LOAD MIN. DELAY LOAD MIN. MASK*** DELAY COUNT STATE=STATE+1 MASK COUNT BEMF STATE=STATE+1 FROM ANY STATE WITH SEQ_INC=0 BEMF DRIVERS OFF MIN CLOCK DELAY LOAD MIN MASK*** PERIOD STOP DELAY COUNT STATE=STATE+1 MASK COUNT RETURN TO PREVIOUS STATE (CHANGING SEQINC=1) * VALID IF SEQINC=0, AND DELAY TIMES OUT ** CLOCK DELAY=F(TDLY_[2:0]) WHEN BEMF PERIOD <3.3ms @ 10MHz (SPEED >12.7Hz FOR 8 POLES) OUTENA=1 OUTENA=1 OUTENA=1 BEMF OUTENA=1 OUTENA=0 BEMF DRIVERS OFF STATE=STATE+1 MIN CLOCK DELAY LOAD MIN DELAY LOAD MAX MASK DELAY COUNT STATE=STATE+1 MASK COUNT CHECK FOR Zc 2 21 SYS_CLK 2 21 DRIVERS ON PERIOD STOP DELAY STOP MASK STOP LOAD DELAY=MIN LOAD MASK=MIN RESET PERIOD PERIOD COUNT DELAY COUNT* STATE=STATE+1 MASK COUNT SYS_CLK 64/FALIGN RUN/BRK=0 DRIVERS OFF MIN CLOCK DELAY PERIOD STOP STATE=STATE+2 OUTENA=1 BEMF 192/FALIGN DRIVERS OFF MONO=0** OUTENA=0 RUN/BRK=0 221 DRIVERS OFF SYS_CLK STATE=STATE+1 LOAD DELAY=MIN LOAD MASK=MAX PERIOD COUNT DELAY COUNT STATE=STATE+1 MASK COUNT BEMF BEMF RUN MODE DRIVERS ON LOAD DELAY=PERIOD LOAD MASK=PERIOD RESET PERIOD PERIOD COUNT DELAY COUNT* STATE=STATE+1 MASK COUNT ALIGN & GO MODE OUTENA=0 DRIVERS OFF MIN CLOCK DELAY PERIOD STOP RESYNCHRONIZATION MODE BEMF D95IN280 * CLOCK DELAY=F(TDLY [2:0] WHEN BEMF PERIOD <3.3ms @ 10MHz (SPEED>12.7Hz FOR 8 POLES) BEMF: BEMF RISING WITH PNSLOPE=1 OR BEMF FALLING WITH PNSLOPE=0 BEMF1: BEMF RISING WITH PNSLOPE=0 OR BEMF FALLING WITH PNSLOPE=1 **MONO=0 WHEN FREQ(BEMF)=2*FREQ(PHASE) ***MIN MASK=192/SYS_CLK(I.E. WITH SYS_CLK=10MHz,MIN MASK=19.2µs) After the next align time-out 192/Falign), the controller enters the Go mode, were the sequencer again double increments the output phase upon detection of the motor’s Bemf. The align time-out may be optimized for the application by changing the Faling reference frequency. A Watch-Dog Timer protection feature is built into the control logic to monitor the Falign pin for a clocking signal. This circuitry, shown in Figure 2-3 will prevent start up the device if the Falign clock is not present. 10/31 Without this feature, the output would remain in the first phase under high current conditions, if the clock were not present. If the external sequencer is used to provide start up, the system clock may be tied to the Falign pin to satisfy the requirements of the Watch-Dog Timer. 2.3 Resynchronization If power is momentarily lost, the sequencer can automatically resynchronize to the monitored L6238S Bemf. This resychronization can either occur whenever Output Enable or Run/Brake is first brought low then high. Referring to figure 2-4, the ”Hold for Resync” state is brought low. The controller leaves this state and enters ”Start Resync” when Output Enable is high. Figure 2.2 POR=0 FROM ANY STATE RUN/BRK=0 FROM ANY STATE DRIVERS ON PERIOD STOP DELAY STOP MASK STOP STATE=1 DRIVERS OFF MIN CLOCK DELAY PERIOD STOP DELAY STOP MASK STOP Figure 2.3: Watch-Dog Timer 64/FALIGN RUN/BRAKE=1 CHECK FOR Zc 192/FALIGN OVER TEMP SHUTDOWN DRIVERS OFF MIN CLOCK DELAY LOAD MIN DELAY LOAD MIN MASK PERIOD STOP DELAY COUNT STATE=STATE+1 MASK COUNT STATE=STATE+1 LOAD DELAY=MIN LOAD MASK=MAX PERIOD COUNT DELAY COUNT STATE=STATE+1 MASK COUNT BEMF OUTENA=1 BEMF S Q CHECK FOR Zc DRIVERS ON LOAD DELAY=PERIOD LOAD MASK=PERIOD RESET PERIOD PERIOD COUNT DELAY COUNT* STATE=STATE+1 MASK COUNT 2 21 SYS_CLK TO START-UP LOGIC BEMF S Q D95IN310 BEMF: BEMF RISING WITH PNSLOPE=1 OR BEMF FALLING WITH PNSLOPE=0 BEMF: BEMF RISING WITH PNSLOPE=0 OR BEMF FALLING WITH PNSLOPE=1 ***MIN MASK=192/SYS_CLK (I.E. WITH SYS_CLK=10MHz, MIN MASK=19.2µs) OUTPUT ENABLE RUN/ BRAKE FALIGN D95IN311 Figure 2-4 BEMF LOAD MIN DELAY LOAD MIN MASK*** DELAY COUNT STATE=STATE+1 MASK COUNT OUTENA=1 BEMF CHECK FOR Zc BEMF RUN/BRK=0 BEMF LOAD DELAY=MIN LOAD MASK=MIN PERIOD COUNT DELAY COUNT* STATE=STATE+1 MASK COUNT OUTENA=1 DRIVERS OFF BEMF RUN MODE MONO=0** BEMF DRIVERS ON LOAD DELAY=PERIOD LOAD MASK=PERIOD RESET PERIOD PERIOD COUNT DELAYH COUNT* STATE=STATE+1 MASK COUNT OUTENA=0 DRIVERS OFF MIN CLOCK DELAY PERIOD STOP HOLD FOR RESYNC RESYNCHRONIZATION MODE D95IN312 *CLOCK DELAY=(TDLY [2:0] WHEN BEMF PERIOD <3.3ms @ 10MHz (SPEED>12.7Hz FOR 8 POLES) BEMF: BEMF RISING WITH PNSLOPE=1 OR BEMF FALLING WITH PNSLOPE=0 BEMF: BEMF RISING WITH PNSLOPE=0 OR BEMF FALLING WITH PNSLOPE=1 ** MONO=0 WHEN FREQ (BEMF)=2*FREQ(PHASE) *** MIN MASK=192/SYS_CLK(I.E.WITH SYS_CLK=10MHz, MIN MASK=19.2µs) 11/31 L6238S Figure 2-5 POR=0 FROM ANY STATE STATE=1 DRIVERS OFF MIN CLOCK DELAY PERIOD STOP DELAY STOP MASK STOP SEQINC=1 & OUTENA=0 RUN/BRK=X INT START-UP DISABLED MIN CLOCK DELAY LOAD MIN DELAY LOAD MIN MASK RUN/BRK=1 & OUTENA=1 DRIVERS ON PERIOD COUNT DELAY COUNT SEQINC=1 SEQINC=0 STATE=STATE+1 MASK COUNT MASK COUNT BEMF BEMF SEQINC=1 SEQINC=0 LOAD DELAY=PERIOD LOAD MASK=PERIOD RESET PERIOD PERIOD COUNT DELAY COUNT** SEQINC=1 FROM ANY STATE WITH SEQ_INC=0 STATE=STATE+1 RETURN TO PREVIOUS STATE (CHANGING SEQINC=1) D95IN313 *VALID IF SEQINC=0, AND DELAY TIMES OUT **CLOCK DELAY=F(TDLY_[2:0]) WHEN BEMF PERIOD <3.3ms @ 10MHz (SPEED >12.7Hz FOR 8 POLES) If zero crossings are detected, the sequencer will automatically lock on to the proper phase. This resynchronization will take effect with the motor speed running as low as typically 30% of it’s nominal value. 2.5 External Sequencing Although the user-defined Start-Up Algorithm is flexible and will consistently spin up a motor with no external interaction, the possibility exists where certain applications might require complete microprocessor control of start-up. The L6238S offers this capability via the SEQUENCE INCREMENT input. Referring to figure 2-5, during initial power-up with Output Enable low, the controller is in the ”Hold and Wait for Decision” state. If the SEQUENCE INCREMENT pin is brought high during this state, the Auto StartUp Algorithm is disabled and the sequencer can be controlled externally. When Output Enable and Run/Brake are brought high, the sequencer is incremented on each positive transition o the SEQUENCER IN12/31 CREMENT pin. During the time that this pin is high, all Bemf information is masked out. When it is low, the Bemf information can be detected normally after the internal mask time. The minimum mask time is 192/Sys_Clk (i.e. with Sys_Clk = 10MHz, min. mask = 19.2µs) Therefore to insure that the sequencer is under complete control of the state machine, the time that the SEQUENCE INCREMENT pin is held low should be much less then the min. mask time, but greater then 1µs. When the motor has reached a predetermined speed, the SEQUENCE INCREMENT pin can be left low and the L6238S Motor Control logic will take over and automatically spin up the motor to the desired speed . 3.0 START-UP ALGORITHMS 3.1 Spin-Up Operation The spin operation can be separated into 3 parts: 1) Open Loop Start-Up - The object is to create motion in the desired direction so that the Bemf voltages at the 3 motor terminals can provide reliable information enabling a transition to closed loop operation. L6238S Figure 3-1: Align+Go RUN/BRAKE ALIGNMENT GO SEQUENCER DOUBLE INCREMENTS *0.711s *2.133s AOUT 1 10V BOUT 2 10V COUT 3 10V STATE 2 A=HIGH B=FLOAT C=LOW STATE 4 A=LOW B=HIGH C=FLOAT * FALIGN=90Hz 2) Closed Loop Start-Up - The Bemf voltage zerocrossings provide timing information so that the motor can be accelerated to steady state speed. 3) Steady-State Operation - The Bemf voltage zero-crossings provide timing information for precision speed control. The L6238S contains features that offer flexible control over the start-up procedure. Either the onboard Auto-Start Algorithm can be used to control the start-up sequence or more sophisticated extenal start-up algorithms can be developed using the Serial Port and key control/sense functions brought out to pins. 3.2 Auto-Start Algorithm When initially powered up, the controller defaults to the internal AutoStart Mode. When Run/Brake is low, the L6238S is in brake mode, and the Auto-Start Algorithm is reset. In the brake mode, all of the lower DMOS drivers are ON, and the up- STATE 6 A=FLOAT B=LOW C=HIGH 500ms/DIV D95IN314 per drivers are OFF. The Auto-Start Algorithm is based on an Align & Go approach and can be visualized by referring to Figure 3-1. Shown are the Run/Brake control signals, sequencer function, and the three output voltage waveforms. Referring to figure 3-1, the following is the sequence of events during Auto-Start: With Output Enable = 1, Run/Brake = 0 - State Machine is set to State 1 with the drivers Trisatted. Alignment Phase (1) Run/Brake = 1 - Output Stage is sequenced to State 2 and the drivers energized with OUTPUT A high and OUTPUT C low for 64/Falign seconds. Alignment Phase (2) - Output Stage is double sequenced to State 4 with OUTPUT B high and OUTPUT A low for 13/31 L6238S 192/Falign seconds. - During the alignment phase, the SEQ INCREMENT signal is ignored. Go Phase - The internal sequencer double increments the output stage to State 6, which should produce torque in the desired direction. - with SEQ INCREMENT held low, the sequencer is now controlled by the Bemf zero crossings, and the motor should ramp up to speed. 3.3 Externally Controlled Start-Up Algorithms Enhanced Start-Up Algorithms can be achieved by using a µProcessor to interact with the L6238S.’ The L6238S has the ability to transition to Closed Loop Start-Up at very low speeds, reducing the uProcessor task to monitoring status rather than real time interaction. Thus, it is a perfect application for an existing µProcessor. The following control and status signals allow for very flexible algorithm development: SEQ_INCR A low to high transition at this input is used to increment the state of the power output stage. It is useful during start-up, because the µProcessor can cycle to any desired state, or cycle through the states at any desired rate. When held high, it inhibits the BEMF zero crossings from incrementing the internal sequencer. SPIN SENSE This output is low until the first detected Bemf zero crossing occurs. It then toggles at each successive zero crossing. This signal serves as a motion detector and gives useful timing information as well as the slope of the Bemf. 3.4 Start Up Approaches Align & Go Approach The Align & Go approach provides a very time efficient algorithm by energizing the coils to align the rotor and stator to a known phase. This approach can be achieved via the sequencing SEQ INCR. SPIN SENSE can be monitored to assure that motion occurred. Once ample time is given for alignment to occur, SEQ INCR can be double incremented, and the SPIN SENSE pin can be monitored to detect motion. When SEQ INCR is pulled low, control is transferred to the internal sequencer, and the L6238S finishes the spinup operation. If no motion is detected, SEQ INCR can be incremented to a different phase and the process can be repeated. The alignment phase may cause backward rotation, which on the average will be greater than the Stepper Motor approach. 14/31 The Auto-Start algorithm described earlier is an Align & Go approach. The main advantages of the integrated Auto-Start are that the µP is not involved real-time, and there are a minimum of interface pins required to the spindle control system. Stepper Motor Approach This approach minimizes backward rotation by sequencing SEQ INCR at an initial rate that the rotor can follow. Thus, it is driven in a similar fashion to a stepper motor. The rate is continually increased until the Bemf voltage is large enough to reliably use the zero-crossings for commutation timing. SEQ INCR is held low, causing control to be passed to the L6238S’s internal sequencer as in the Align & Go approach. The Stepper Motor approach takes longer than the Align & Go approach because the initial commutation frequency and subsequent ramp rate must be low enough so that the motor can follow without slipping. This implies that to have a reliable algorithm, the initial frequency and ramp rate must be chosen for the worst case motor under worst case conditions. 4.0 MOTOR DRIVER 4.1 Output Stage The output stage forms a 3-Phasefull wave bridge consisting of six Power DMOS FET High output currents are allowed for bbrief periods. High output currents are allowed for brief periods. Output Power exceeding the stand-alone power dissipation capabilities of the L6238S can be increased with the addition of an external P-FET or by the use of Pulse-Width-Modulation. Table 4-1 is a reference diagram that lists the parameters associated with 8-pole motors operating at 3600 and 5400 RPM. Figure 4-1 represents the waveforms associated with the output stage. The upper portion of figure 4-1 shows the flow of current in the motor windings for each of the 24 phase increments. A rotational degree index is shown as a reference along with a base line to indicate the occurrence of a zero crosing. The output waveforms are a digitally reproduced voltage signals as measured on samples.The feedback Input is multiplexed between the internal Bemf Zero Crossing Detector and an externally provided sync pulse (EXT INDEX) Shown in figure 10 is the classical state diagram for a phase detector along with waveform examples. A typical sequence starts when the outputs switch states. Referring to figure 4-1, during phase 1, output A goes high, while outputB is low. During this phase, output C is floating, and the Bemf is monitored. The outputs remain in this state for 60 electrical degrees as indicated by the first set of dashed lines. After this period the out- L6238S Table 4-1 Rotational Speed 3600rpm 5400rpm Rotational Frequency 60Hz 90Hz Rotational Period 16.667ms 11.111ms Electrical Period 4.167ms 2.778ms Phase Period 694.5µs 463.0 Figure 4-1: Waveforms 15/31 L6238S put switched to phase 2 with output A high and C low with the Bemf amplifier monitoring output B. In order to prevent commutation current noise being detectedm as a false zero crossing, a masking circuit automatically blanks out all incoming signals as soon as a zero crossing is detected. When the next commutation occurs an internal counter starts counting down to set the time that the masking pulse remains. The counter is initially loaded with a number that is equal to time that is always 25% of the previous phase period or 15 electrical degrees. The timeout of the masking pulse shown for reference at the bottom of figure 4-1. Thus the actual masking period is the total of the time from the detected zero crossing to the phase commutation, plus 25% of the previous period. The mask pulse operation is further discussed in section 4.6, Slew Rate Control and PWM operation. After the masking period, the Bemf voltage at output B is monitored for a zero crossing. Upon detection of the crossing, the output is commutated after the selected phase delay insuring maximum Figure 4-2 16/31 torque. The spin sense waveform at the bottom of the figure indicates that this output signal toggles with each zero crossing. 4.2 Brake Delay When Run/Brake is brought low, a brake is initiated. Referring to figure 4-2, SW1 is opened and the brake delay capacitor, Cbrake, is allowed to discharge towards groun via Rbrake. At the same time, switches SW2 through SW7 bring the gates of the output FETs to ground halting conduction, causing the motor to coast. While the motor is coasting, the Bemf is used to park the heads. When Cbrake reaches a voltage that is below the turn ON threshold of Q1, Switches SW8, 9, and 10 bring the gates of the lower drivers to Vbrake potential. This enables the lower FETs causing a braking action. The analog and logic supplies are not monitored in the L6238S, since the L6244 already monitors this voltage and initiates a Park function when either supply drops to a predeterminated level. L6238S Figure 4-3 4.3 Charge Pump The charge pump circuitry is used as a means of doubling the analog supply voltage in order to allow the upper N-channel DMOS transistors to be driven like P-channel devices. The energy stored in the reservoir capacitor is also used to drive the lower drivers in a brake mode if the analog supply is lost. Figure 4-3 is a simplified schematioc of the charge pump circuitry. A capacitor, Cpump, is used to retrieve energy from the analog supply and then ”pumps” it into the storage capacitor, Cresvr. An internal 300KHz oscillator first turns ON Q2 to quickly charge Cpump to approximately the rail voltage. The oscillator then turns ON Q1 while turning OFF Q2. Since the bottom plate of Cpump, is now effectively at the rail voltage via D2. A zener-referenced series-pass regulator supplies Figure 4-4 OUTPUT B C VPOWER VPUMP L1 SW2 1 UPPER A VCTRL + - Q1 0 Cfet SW3 OUTA 1 LOWER A L3 I1 Islew A2 L2 Q2 0 Cfet RSENSE I2 Islew A3 CSA X4 VANALOG Q3 RS Q4 PWM SLEW/RC Q5 RSLW SLEW RATE REFERENCE CURRENT 3.1V D95IN315 17/31 L6238S a voltage, Vbrake, during brake mode. The maximum capacitance specified for the Storage Capacitor is 4.7µF.For applications requiring a larger value, an external diode should be connected between Vanalog and the Storage Capacitor to prevent excessive inrush current from damaging the charge pump circuitry. A small value resistor (i.e. 50W) may instead be inserted in series with the Storage Capacitor to limit the inrush current. 4.4 Linear Motor Current Control The output current is controlled in a linear fashion via a transconductance loop. Referring to Figure 4-4 the sourcing FET of one phase is forced into full conduction by connecting the gate to Vpump, while the sinking transistor of an appropriate phase operates as a transconductance element. To understand the current control loop, it will be assumed that Q2 in figure 4-4 is enabled via SW3 by the sequencer. During a run condition, the current in Q2 is monitored by a resistor Rs connected to the Rsense input. The resulting voltage that appears across Rs is amplified by a factor of four by A3 and is sent to A2 where it is compared to the Current Command Signal. A2 provides sufficient drive to Q2 in order to maintain the motor speed at the proper level as commanded by the Speed Controller. The pole/zero locations are adjusted such that a few dB of gain (typ. 20dB) remains in the transconductance loop at frequencies higher than the zero. The inductive characteristic of the load provides the pole necessary for loop stability. Thus the loop bandwidth is actually limited by the motor itself. Figure 4-5 shows the complete transconductance loop including compensation, plus the response. The Bode plot depicts the normal way to achieve stability in the loop. The pole andzero are used to set a gain of 20dB at a higher frequency and the pole of the motor cuts the gain to achieve stability. Loop instability may be caused by two factors: 1)The motor pole is too close to the zero. Referring to figure 4.6, the zero is not able to decrement the shift of phase, and when the effect of the pole is present, the phase shift may reach 180° and the loop will oscillate. To rectify this situation, the pole/zero must be shifted at lower frequencies by increasing the compensation capacitor. Figure 4-6 4.5 Transconductance Loop Stability The RC network connected to the Compensation pin provides for a single pole/zero compensation scheme. The pole/zero compensation scheme. Figure 4-5 Figure 4-7 18/31 L6238S Figure 4-8 2)The motor capacitance, CM, itself can interfere with the loop, creating double poles. If the gain at higher frequencies is sufficiently high, the double pole slope of 40dB/decade can cause the phase shift to reach 180°, re sulting in oscillation. Figure 4-8 is a Bode plot showing how to correct this situation. The bold line indicates the response with relatively high gain at the higher frequencies. By leaving the pole unchanged and increasing the zero, the response indicated by the dashed lines can be achieved. 4.6 Slew Rate Control A 3-phase motor appears as an inductive load to the power supply. The power supply sees a dis- turbance when one motor phase turns OFF and another turns ON because the FET turn-OFF time is much shorter than the L/R rise time. Abrupt FET turn-OFF without a proper snubbing circuit can even cause current recirculation back into the supply. However, the need for a snubber circuit can be eliminated by controlling the turn-OFF time of the FETs. The rate at which the upper and lower drivers turn OFF is programmable via an external resistor, Sslew connected to the SLEW RATE pin. This resistor defines an internal current source that is utilized to limit the voltage slew rate at the outputs during transition, thus minimizing the load change that the power supply sees. To insure proper operation the range of resistor values indicated should not be exceeded and in some applications values near the end points should be avoided as discussed below. Low Values of Rslew - If a relatively low value of Rslew is selected, the resultant fast slew rate will result in increased commutation cross-over current, higher EMI, and large amount of commutation current. This last case can cause voltage spikes at the output that can go as much as lV below ground level. This situation must be avoided in this integrated circuit (as in most) since it causes unpredictable operation. High Values of Rslew - Higher values of Rslew result of course in slow slew rates at the outputs which is, under most conditions, the desired case since the problems associated with fast rates are reduced. The additional advantage is lower acoustical noise. Problems can occur though if the slew rate for a Figure 4-9: Effect of Slow Slew Rate. 19/31 L6238S Figure 4-10: External P-Fet. given application is too slow. Figure 4-9 is an oscillograph taken on a device that had a fairly large value for Rslew and failed to spin up and phase lock a motor. The problem manifests itself as the motor begins to spin up. At lower RPMs, the Bemf of the motor is relatively small resulting in higher amounts of commutation current. In figure 4-9, the upper waveform is the voltage appearing at OUTPUT relative to the CENTER TAP input. The lower waveform is the actual output of the Bemf amplifier available on special engineering prototypes. The oscillograph was taken just as the problem occured. The period between zero crossings was ~800µs resulting in a mask time period of 200µs. As can be seen, the excessively long slew rate actually exceeded the mask period and was detected as a zero crossing. This resulted in improper sequencing of the outputs relative to the proper phases and caused the motor to spin down. 4.7 Ext PFET Driver The power handling capabilities of the 3 phase output stage can be extended with the addition of a single P-Channel FET. 20/31 Figure 4-10 shows the Ext FET connection and demonstrates how the L6238S automatically senses the FETs presence. When the voltage at the Gate Drive pin is ≥ 0.7V, the output of comparator A3 goes high, removing the variable drive A1 from the internal FETs and connects them instead to Vanalog via the commutation switches to facilitate full conduction. The upper FETs drive paths are not shown for clarity. A3 also closes SW2 allowing A1 to linearly drive the external P-Channel FET Q1 via inverter A2. 4.8 Bemf Ampolifier Since no Hall Effect Sensors are required, the commutation information is derived from the Bemf voltage zero-crossings of the undriven phase with respect to the center tap. The Bemf comparator and associated signal levels are depicted in figure 4-11. For reliable operation, the Bemf signal amplitude should be a minimum of ± 60 mV to be properly detected. In order to provide for noise immunity, internal hysteresis is incorporated in the detection circuitry to prevent false zero crossing detection. For laboratory evaluation purposes, a simple re- L6238S Figure 4-11: Bemf Amplifier. VoBEMF ViBEMF(mV) -35 -25 SLOPE=0 0 25 35 SLOPE=1 D95IN316 sistive network as shown in figure 4.12 can be used to emulate the Bemf of the motor. The actual Bemf zero-crossing is 30 electrical degrees (50% of a commutation interval) away from the optimal switch point. A digital counter circuit measures 50% of the previous interval to determine the next interval’s commutation delay from the zero crossing. During the low RPM stages of start up the long commutation intervals may cause the counter to overflow, in which case 50% of the max count will be less than 50% of the ideal commutation interval. Therefore, the torque will not be optimal until the desired commutation interval is less than the dynamic range of the counter. Figure 4-12: Bemf Emulator Figure 4-13 4.9 Center Tap Protection Spindle Motors with a high number of windings exhibit a transformer coupling effect that in some cases can cause relatively high currents to flow through the center tap input. Current flowing out of the center tap pin as high as 25mA has been observed with certain motors. R1 1K TO CENTER TAP INPUT DS1 D95IN317 21/31 L6238S The high current flows from the grounded substrate of the integrated circuit (p-type material), through one or more epitaxial pockets (n-type material) and out the center par pin. This current can cause adverse operation of the controllet due to substrate injection and might possibility damage the internal metalization runs. The normal current for this input is in the 200µA range. Referring to figure 4-13, a simple protection scheme consisting of a 1K resistor and a low current Schottky diode should be added if the application causes excessive current (i.e. >1mA) to flow through the center tap pin. 5.0 PWM MOTOR CURRENT CONTROL A unique feature of the L6238S in the optional Pulse Width Modulation (PWM) control of motor current. Using Variable-frequency, Constant-OFF time Current-Mode control, the L6238S can drive higher power motors without the need for external drivers, while minimizing internal power dissipation. Additional benefits include reduced power supply consumption (up to 50% savings) and lower wattage requirements for the current sensing resistor. Constant-OFF time Current-Mode control, operates on the principle of monitoring the motor current and comparison it to a reference or control level. When the motor current reaches this commanded level, the output drivers turn OFF and remain OFF for a Constant-OFF time. After this OFF time the drivers turn back ON to repeat the cycle. Figure 5.1 is a block diagram of the PWM control circuitry. When using PWM as opposed to linear control, two changes are made to the control loop: 1.The slew rate control is disabled, allowing the outputs to slew at a minimum rate of 10V/µs. This is accomplished by closing SW3 and SW5. 2.The OTA amplifier is taken out of the control loop via SW6. The lower drivers are now driven into hard conduction by tying the gates to the analog supply during the On time of the PWM cycle. The current in the motor windings is monitored via the voltage dropped in the sensing resistor, Rsense . This voltage is multiplied by a factor of 4 in the Current Sense Amplifier (CSA) and sent to negative input of the PWM Comparator (A2). The control voltage, Vcontrol, is applied to the positive input of A2. When the output of the CSA reaches a level that is equal to the commanded level, the output of A2 switches low, toggling the latch comprised of N1 and N2. This causes the upper drivers to turn off and opens SW1. Q3 turns OFF allowing the Constant-OFF time capacitors, Figure 5-1 OUTPUT B C VPOWER VPUMP VANALOG Q1 UPPER A Q2 PWM/LIN CONTROL SLEW RATE REFERENCE Q3 CURRENT SW2 N3 L1 1 L2 Q4 0 Cfet SW3 I1 Islew L3 SW1 OUTA LOWER A SW4 3.1V 1 Q5 0 SW5 Cfet I2 Islew RSENSE VANALOG A3 PWM/SLEW + 1.2V - SW6 A1 N1 1 0 FROM TRANS. LOOP N2 RSLEW COFF + A2 - VCTRL X4 CSA CSA D95IN318 22/31 RSLW L6238S Coff to discharge to dischargte through Rslew, initiating the Constant-OFF time-out. When the voltage on Coff reaches 1.2V, comparator A1switches state toggling the latch in the opposite state, turning the upper driver back ON. SW1 also closed quickly charging up Coff for the next cycle. Figure 5-2 VPOWER Q1 5.1 PWM Design Considerations In order to select the parameters associated with PWM operation, the following factors must be taken into consideration: 1. PWM Switching Frequency 2. Duty Cycle 3. Motor Currents 4. Minimum ON Time 5. Noise Blanking 6. Bemf Masking/Sampling Q3 D1 D3 L1 L2 OUTPUTA OUTPUTB Q2 Q4 D2 D4 RSENSE RSNS D95IN319 5.1.1. PWM Switching Frequency The PWM switching frequency Fpwm is found from: Fpwm = 1 Ton + Toff Figure 5-3 VPOWER (5.1.1) where: Ton = The time required for the motor current to reach the commanded level. Toff = The programmed OFF time. The two main considerations for this parameter are the minimum and maximum switching frequency. The maximum switching frequency occurs during the Start-up and should be kept below 50KHz due tointentional bandwidth limitations and output switching losses. 5.1.2 Duty Cycle Besides reducing the power dissipation of the controller output stage, running in PWM offers 2 additional ”free” benefits: A. Reduced Powe Supply Current at Start Up B. Lower Power Rating for the Motor Current Sense Resistor. Figure 5-2 is the current path during the ON time of a phase period. The current from the supply passes through the upper sourcing DMOS, Q3 transistor through the two driven winding, the lower DMOS, Q2 and finally through the current sensing resistor Rsns. Since both Q3 and Q4 are ON, while Q3 is turned OFF. The voltage, causing the current to continue to flow through Q2, and Q4. If the duty cycle is nearor at 50%, then for 1/2 the PWM cycle, no current is flowing from the power supply or the sense resistor while current is still flowing in the motor. This lowers the requirement Q1 Q3 D1 D3 L1 L2 OUTPUTA OUTPUTB D2 D4 Q2 Q4 RSENSE RSNS D95IN320 for both the Power Supply and the Power Rating for the sensing resistor. 5.1.3 Motor Currents Note: It is not the objective of this section to describe the principles of brushless DC motor, but to provide sufficient information about the parameters associated with PWM operation in order to optimize an application. A simplified model of a motor is shown in figure 54. For this discussion, lower order effects due to mutual inductance between windings, resistance due to losses in the magnetic circuit, etc. are not shown. The motor at stall is equal to a resistance, Rmtr, in series with an inductance, Lmtr. When the motor is rotating, there is an induced emf that appears across the armaure terminals and is shown in figure 5-4 as an internally generated voltage Ibemf), Eg. 23/31 L6238S The additional resistance associated with the output stage and sensing resistor are also in series with the motor. If we let Rs equal the total series resistence: Figure 5-4 Lmtr Rs = 2*RdsON + Rmtr + Rsense (5.1.5) Rmtr then (5.1.4) becomes: + Eg - V = Lmtr D95IN321 dimtr dt Rs imtr + Eg (5.1.6) The relation between these variables is given by: V = Lmtr dimtr dt Rmtr imtr + Eg (5.1.2) Figure 5-6 where: Lmtr V = Applied Voltage imtr = Motor Current Lmtr = Total inductance windings Rmtr = Resistance in series with the motor Eg = The internally generated voltage of the motor, proportional to the motor velocity of the Since: = KEω (5.1.3) Eg The above equations can be combined to form the basic electrical equation for a motor: V = Lmtr dimtr dt Rmtr imtr + KEω (5.1.4) Figure 5.5 is a simplified electrical equivalent of the output stage of the L6238S along with the model of the motor during the time that the Output Drives are conducting. Figure 5-5 UPPER Rdson Rmtr motor KEW + LOWER Rdson D95IN323 Figure 5-6 is an equivalent circuit of the output stage during the Constant-OFF period. During the OFF time the lower driver for the particular phase beign driven remains ON. The internally generated voltage forces the path of current though the motor, its series resistance, the RdsON of the Lower Driver and finally through the opposite lower driver. PWM Example (Refer to Figure 5-7) The following is an example on how to select the timing parameters. Given: DCStart Current = 1.25A Ripple Current = 100mA Duty Cycle = 50% Rmtr Motor Interface (L) = 880µH + Total Series Resistance (Rs) = 4.8Ω Lmtr KEW LOWER Rdson Rsense If the worst case start current is 1.25A and the duty cycle is 50%, then the Peak Current, It will be: 0.1 it = 1.25 + 2 D95IN322 24/31 LOWER Rdson it = 1.30A L6238S the voltage drop remains constant across the windings. The time required for the inductor current to reach the valley current is given by: The Valley current, Ib will thereforebe: ib = 1.30 - 0.1A ib = 1.20A toff = During the Align and Go Phase (where the power dissipation requirements are highest, Eg is zero. The initial time required to reach the Peak current is: tinit = ±L I,R ln 1 ± V R Ib ln R (5.1.9) Substituting values: toff = (5.1.7) 880e±6 1.3 ln 4.8 1.2 toff = 14.67µs Substituting values: tinit = It L Note: that the parameters for this example were selected to arrive at a 50% duty cycle. This will not always be the case due to factors such as fixed motor parameters, etc. ± 880e ± 6 1.3 ⋅ 4.8 ln 1 ± 12 4.8 The Constant Off timer period can be determined from: tinit = 134.6µs The ON time can be calculated from: V ± ib Rs ton = ln Rs V ± i t Rs Vchrg toff = Rslew ⋅ Coff ⋅ ln Vtrip (5.1.10) Where: L (5.1.8) Toff = Constant-OFF Time Rslew = Slew Rate Resistor Substituting values: Coff Off Time Capacitor 12 ± 1.2 880E ± 6 4.8 ln ton = 4.8 12 ± 1.3 4.8 Vchrg = Initial Capacitor Charge Voltage = Capacitor Lower Trip Threshold Vtrip = Substituting nominal values given: T off = 0.75 ⋅ Rslew ⋅ Coff ton = 14.67µs Solving for Coff Figure 5-7 D95IN324 Coff = It=1.3A Ib=1.2A Iavg=1.25A Toff 0.75Rslew In the example, to set the OFF timer for a 50% duty cycle: Given: Toff = Rslew = Coff = Iout A 200mA 4 14.67µs 100KΩ (typical Value) 14.67e±6 100e3 Coff ≈ 146pF 20µs/DIV During the OFF time, the motor current continues to flow through the DMOS transistors and threfore 5.1.4 Minimum ON Time The bandwidth of the PWM loop was optimized to reject unwanted switching noise while providing 25/31 L6238S sufficient response, commensurate with the switching speed of the output drivers. At higher frequencies the switching losses inherent in the drivers start to negative any of the power dissipation savings gained with PWM operation. The current sense amplifier has a minimum slew rate of 0.31V/µs. With a worst case Motor peak start-up current of 2.5A and Sense Resistor of 0.33, the resultant Rsense voltage would be equal to 825mV. With a minimum gain of 3.8V/V, the CSA output voltage would have to slew to 3.14V. Therefore it would require approximately 10µs for the output voltage to reach the required commanded level. If an ON time were selected that was less than this time, the motor current would overshoot the desired level resulting in incorrect current control possibly exceeding the output capabilities of the drivers. Figure 5-9 is an additional block diagram of the PWM control loop including the noise blanking circuit. The output of A3 goes high when ever the voltage at the CSA input is more positive then the Control Voltage. This is the case when either the motor current or the turn-ON transient has reached the commanded level. The output of A3 is gates by N11. In order to provide a blanking period, Q1 is turned Figure 5-8 D95IN325 3µs BLANKING PULSE COMMANDED CURRENT LEVEL 5.1.5 Noise Blanking Referring to Figure 5-8, when operating with lower levels of current (i.e. < 700mA, with Rsense = 0.33Ω), the possibility exiss where the noise due to output Turn-ON can exceed the Commanded Current Level causing prematire TurnOFF. In order to provide noise immunity from this switching noise, a blanking circuit automatically rejects any signal appearing at the output of the CSA for a 3µs period. Vrsense 1 10µs/DIV Figure 5-9 2.4V SW1 N12 Q3 N1 Q1 C1 8pF N6 I1 5µA N7 N9 CLK_BEMF N2 TO OUPUT DRIVERS R1 1.2V X4 N8 N10 DELAY N3 PWM_SLEW + A2 - N11 + A3 - CSA INPUT VCONTROL PWM COMP I2 20µA PWM TIMER N4 N5 Q2 PWM/LIN RUN/BRAKE 26/31 C3 C4 N12 D95IN326 L6238S ON during the Constant-OFF time, charging C1 to the internal rail. At the end of the OFF time, Q1 is turned OFF allowing current source I1 to discharge the capacitor towards ground. While the voltage on C1 is above the low input threshold of N1, the output of N1 is low, preventing any change of state at the output of N11 due to a high A3 output. When the capacitor reaches the low input threshold of N1, N1 chnges state allowing A3 to control the state of N11. 5.1.6 Masking/Bemf Sampling in PWM The method of sampling the floating phase for the bemf zero crossing defers between Linear and PWM operation. In Linear Mode, the bemf is sampled continuously after the mask time-out, until the zero crossing is detected. Then the mask is enabled for a time based on the commutation phase delay plus the additional time based on the previous period as explained earlier. With PWM operation however, the switching noise at turn ON (after the Constant-OFF time) can be significant, especially at low RPMs where the bemf is the lowest. In order to provide the greatest noise immunity in PWM, the floating phase is monitored only at the point where the output is about to be turned OFF. In operation, when the motor current reaches the commanded level, the floating phase is first monitored to determine if the bemf has crossed the zero. The output is then turned OFF for the Constant-OFF time out. As the motor current increases through, the increasing bemf causes the motor current to naturally decrease. Eventually a point is reached where the PWM is running at 100% duty cycle and the motor current cannot reach the commanded level. At this time the bemf is no longer smpled, preventing further commutation of the output. The PWM Limit Timer is used to set up a maximum ON time. When this limit is exceeded the method of sensing the bemf is essentially the same as in the case of operating in linear mode. Figure 5-10 is an oscillograph of the controller operating in PWM mode. The top trace is Aout. The 2nd trace is the voltage seen at the PWM/SLEW pin indicating the exponential discharging of the timing capacitor during the OFF time. Trace 3 is the voltage appearing on the PWM Timer capacitor, while trace 4 is the motor current. Referring again to Figure 5-9, and 5-10 transistor Q2 is turned ON at the beginning of the OFF time, discharging the external capacitor C4 to near ground level. At the end of the OFF-Time, Q2 is turned off and C4 starts charging linearly via I2. C4 is again discharged at the beginning of the OFF time and the cycle repeats. As long as C4 does not reach the threshold of A1 (typically 3.5V), the bemf is only sampled just before turnoff of the output. As the motor is starting up in figure 5-10, the duty cycle is roughly 50%. The PWM limit timer is reset to ground by the start of the OFF timer before reaching the 3.5V threshold. In figure 5-11, as the motor spins up, the on time of the output increases and the PWM limit timer reaches the 3.5V. Eventually the duty cycle reaches 100% and the sampling of the bemf is essentially the same as in the linear mode. The selection of components for the PWM timer is not critical. Since the objective is to sample the bemf only at turn OFF to maximize the signal to noise ratio, the PWM timer slope can be set up to convert to the full bemf sampling after a few revolutions of the motor when the bemf has reached an appropriatevoltage output. Figure 5-10 Figure 5-11 D95IN327 D95IN328 Aout Aout 1 10v 1 PWM/Slew 2 PWM/Slew 2V 2 PWM Limit Timer 500mV 3 Iout A 4 2V PWM Limit Timer 500mV 3 1A 10V Iout A Fpwm=50KHz Coff=120pF Ctmr=220pF 20µs/DIV 4 1A Fpwm=12KHz Coff=120pF Ctmr=220pF 50µs/DIV 27/31 L6238S PLCC44 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. MIN. TYP. MAX. A 17.4 17.65 0.685 0.695 B 16.51 16.65 0.650 0.656 C 3.65 3.7 0.144 0.146 D 4.2 4.57 0.165 0.180 d1 2.59 2.74 0.102 0.108 d2 E 0.68 14.99 0.027 16 0.590 0.630 e 1.27 0.050 e3 12.7 0.500 F 0.46 0.018 F1 0.71 0.028 G 28/31 inch MAX. 0.101 0.004 M 1.16 0.046 M1 1.14 0.045 L6238S PQFP44 PACKAGE MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. A MIN. TYP. MAX. 3.40 A1 0.25 A2 2.55 B 0.134 0.010 2.80 3.05 0.100 0.110 0.35 0.50 0.0138 0.0197 C 0.13 0.23 0.005 0.009 D 16.95 17.20 17.45 0.667 0.677 0.687 D1 13.90 14.00 14.10 0.547 0.551 0.555 D3 10.00 0.394 e 1.00 0.039 0.120 E 16.95 17.20 17.45 0.667 0.677 0.687 E1 13.90 14.00 14.10 0.547 0.551 0.555 E3 10.00 L 0.65 0.394 0.80 L1 0.95 0.026 0.0315 1.60 0.0374 0.063 0°(min.), 7°(max.) K D D1 A A2 D3 A1 33 23 22 34 0.10mm .004 44 B E E1 B E3 Seating Plane 12 11 1 C L L1 e K PQFP44 29/31 L6238S TQFP64 PACKAGE MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. A MIN. TYP. MAX. 1.60 A1 0.05 A2 1.35 B C 0.063 0.15 0.002 0.006 1.40 1.45 0.053 0.055 0.057 0.18 0.23 0.28 0.007 0.009 0.011 0.12 0.16 0.20 0.0047 0.0063 0.0079 D 12.00 0.472 D1 10.00 0.394 D3 7.50 0.295 e 0.50 0.0197 E 12.00 0.472 E1 10.00 0.394 E3 7.50 0.295 L 0.40 0.60 L1 0.75 0.0157 0.0236 1.00 0.0295 0.0393 0°(min.), 7°(max.) K D D1 A D3 A2 A1 48 33 49 32 0.10mm E E1 E3 B B Seating Plane 17 64 1 16 C L L1 e K TQFP64 30/31 L6238S Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGSTHOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1995 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 31/31