STMICROELECTRONICS L6232E

L6232E
SPINDLE DRIVER
1.5A MAXIMUM PEAK CURRENT
CONTROLLED SLEW RATE
CENTRAL CHARGE PUMP
PWM AND LINEAR MODES
CUTOFF TIME USER CONFIGURABLE
FAST, FREE-WHEELING DIODES ON CHIP
OVER-TEMPERATURE PROTECTION
BRAKE FUNCTION INPUT
PLCC21+7
ORDERING NUMBER: L6232E
DESCRIPTION
The L6232E is a triple half bridge driver intended
for use in brushless DC motor applications. This
part can be used to form the power stage of a
three-phase, brushless DC motor control loop,
and is especially useful for disk drive applications.
Power drivers are Integrated DMOS transistors
and feature fast recirculating diodes as an integral
part of their structure. The logic inputs are TTLlevel compatible, with internal pull-up, allowing interfacing to open collector outputs. All necessary
circuitry to perform PWM and linear motor speed
control is included. A central charge pump is utilized to drive the upper DMOS transistors, and
also to power the braking function. The L6232E is
packaged in PLCC28.
BLOCK DIAGRAM
October 1996
1/10
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L6232E
PIN DESCRIPTION
Pin
Name
1 to 4
GND
5, 9
SENSE
6
INLB
7, 11
VS
Function
Common Ground. Also provides heat-sink to PCB.
Output for current sense resistors.
Logic Input to turn on the lower driver (Active High).
Supply Voltage.
8
INLA
10
CS
External Charge Pump Capacitor.
12
CP
External Main Charge Pump capacitor.
13
RC
Cutoff Time RC Network in PWM mode. The Resistor value is also used to define
the slew-rate in linear mode (LIN).
14
INLC
15
BRK DLY
Logic input to turn on the lowey driver (Active High).
Logic input to turn on the lower driver (Active High).
External RC network for the brake delay.
16
INUC
17
PWM Vref
18
LIN Vref
19
COMP
External compensation for error amplifier
20
OUTA
DMOS Half-bridge A Out.
21
BRK
22
OUTB
DMOS Half-bridge B Out.
23
INUA
Logic Input to turn on the upper drivers (Active Low).
24
INUB
Logic Input to turn on the upper drivers (Active Low).
25
OUTC
DMOS Half-bridge C Out.
26 to 28
GND
PIN CONNECTION (Top view)
2/10
Logic Input to turn on the upper driver (Active Low).
Input for Reference Control in PWM mode
Input for Reference Control voltage in LIN mode
Active LOW logic input that triggers the delayed brake.
Common Ground. Also provides heat-sink to PCB.
L6232E
ABSOLUTE MAXIMUM RATINGS
Symbol
VDS sus
VS
VO pe ak
VCp
Vi
VREF
Value
Unit
Peak Output Sustaining Voltage
Parameter
15
V
Supply Voltage
15
V
Output Peak Voltage (tpK = 5 µsec; 10% d.c.)
18
V
Charge Pump Input Voltage
30
V
Logic Input Voltage
-0.3 to 7
V
PWM VREF--LIN VREF Input Voltage
-0.3 to 7
V
V is
Sense Input Voltage
-1 to 7
V
Ip
Sink-Source Peak Output Current (*)
3.5
A
IO
Sink-Source DC Output Current
1.8
A
Total Power Dissipation (Tamb = 70°C)
1.5
W
-40 to 150
°C
Ptot
Tstg, Tj
Storage and Junction Temperature
THERMAL DATA
Symbol
R th j-pin
Rth j-amb
Description
Thermal Resistance Junction-pins
Thermal Resistance Junction-ambient (**)
Value
Unit
14
52
°C/W
°C/W
Max.
Max.
Notes
(*) Pulse width (limited only by junction temperature and by the transient thermal resistance.
(**) Mounted on board with 16cm2 35µm thickness copper area on board heatsink.
ELECTRICAL CHARACTERISTICS (See the block diagram, VS =12V, R = 100KΩ; C = 180pF;
T j = 25°C, unless otherwise specified)
Symbol
Parameter
VS
Supply Voltage
IS
Quiescent Supply Current
Test Condition
Min.
Typ.
Max.
Unit
10.5
12
13.5
V
BRK = L; INUA = INUB = INUC
= L; INLA = INLB = INLC = H;
Table 1
0.3
0.5
mA
BRK = H; INUA = INUB = INUC
= H; INLA = INLB = INLC = L;
Table 1
4
6
mA
1
mA
0.47
Ω
IOL
Output Leakage Current
VO = VS = 13.5V
RDSon
Sink Out ON Resistance
Tj = 25°C (see Fig.4)
0.42
Tj = 125°C
0.7
Tj = 25°C (see Fig.4)
0.42
Tj = 125°C
0.7
RDSon
VF
td(BRK)
Source Out ON Resistance
Body Diode Forward Drop (sink
and source)
IDS = 1A (see Fig. 6)
Brake Delay Time
See Fig. 1, 3; note1
1
Ω
0.47
Ω
Ω
1.5
210
V
ms
TBRK
Braking Time
IB(LIN)
LIN Vref Input Bias Current
LIN Vref = 0.4 to 5.5V
400
950
nA
IB(PWM)
PWM Vref Input Bias Current
PWM Vref = 0.4 to 5.5V
400
950
nA
LIN Vref
Reference Voltage Input
Note 2; RS = 0.5Ω
Imotor (PWM) = 1A
Imotor (LIN) = 200mA
2
V
0.4
V
PWM Vref
Gv
Sense Amplifier Voltage Gain
10
PWM Vref = 2.5V,
LIN Vref = 0.4V,
RS = 0.5Ω; Note 2
3.7
s
4
4.3
V/V
3/10
L6232E
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Gm
LIN Error Amplifier
Transconductance
Zout
Error Amplifier Output
Impedance
VINH
Logic Input Voltage BRK; INUA;
INUB; INUC; INLA; INLB; INLC
VINL
Min.
Typ.
Max.
Unit
0.8
mA/V
2
MΩ
2
V
0.8
V
Logic Input Current BRK; INUA;
INUB; INUC; INLA; INLB; INLC
Vi = 2.7V
-1
mA
IINL
Vi = 0.4V
-0.1
mA
tdonU
Upper/Lower Turn-on Delay
Table 1
IINH(leak)
see Fig. 3
tdonL
tdoffU
Upper/Lower Turn-off Delay
tdoffL
dV/dt
Source DMOS Slew-Rate
(PWM)
see Fig. 3
dV/dt
Source DMOS Slew-Rate (LIN)
see Fig. 3
dV/dt
Sink DMOS Output Turn-off
Slew-Rate
Note 3; R = 100KΩ
µs
0.7
0.15
µs
15
µs
0.5
µs
V/µs
10
1
V/µs
0.15
V/µs
380
KHz
40
µs
FC
Internal Clock Frequency
Toff
PWM Cutoff Time
T sd
Shutdown Temperature
160
°C
Tsdr
Recovery Temperature
120
°C
R=100KΩ; C=180pF, Note 4;
see Fig. 2
Notes:
1) The Head Park time must be shorter than the Brake Delay time t d(BRK) = RdCd
2) Both in PWM and in LIN mode the Ref. Voltage must agree to V ref=GV RS Imotor
3) The resistance of the RC network defines the dv/dt value.
4) toff = 1.8RC + 6 ⋅ 10-6
Table 1
INPUT STATE
OUTPUT STATE
INUA
INUB
INUC
INLA
INLB
INLC
A
B
L
L
L
H
H
H
*
*
*
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
*
*
*
H
H
H
H
H
H
L
L
L
H = The Upper DMOS is ON
L = The Lower DMOS is ON
* = Tristate condition
4/10
C
L6232E
Figure 1: Brake Delay and Braking timing of the L6232E. At the time t1 a VP Powerdown threshold
detector drives low the BRK input; at time t2 the Charge Pump voltage becomes inadequate
to maintain ON the lower DMOS.
FUNCTIONAL DESCRIPTION (Refer to the
Block Diagram)
The commutation sequence is provided by the
user via six inputs. INUA,INUB,INUC turn on the
three upper DMOS drivers when held at logic
LOW, and inputs INLA,INLB,INLC turn on the
three lower DMOS drivers when held at logic
HIGH.
The BRK and BRK DLY inputs offer flexibility to
the system designer in the implementation of the
braking function. The BRK logic input, when
pulled low will turn-off all upper and lower Dmos
drivers. The low transition at BRK will produce a
delayed negative transition at the BRK DLY input,
configurable by connection of a capacitor Cd and
a resistor Rd from the BRK DLY pin to ground.
The negative transition at BRK DLY will initiate
the braking of the motor by turning on all lower
Dmos, while keeping all upper DMOS turned-off.
This feature provides a time interval where the
motor BEMF can be used to power the head
parking function before the braking procedure is
iniziated. External detection of the supply(VP)
drop-off is necessary to provide the appropriate
logic signal to the BRK input. (see Fig. 1)
The brake function utilizes the energy stored in
the central charge pump capacitor (Cp) to turn-on
or turn-off the DMOS drivers. This allows for
completion of the braking procedure after the VP
supply has powered down.
The L6232E is capable of driving the motor in
either pulse width modulation (PWM) or linear
(LIN) mode. The driving mode is determined by
the smaller of two analog voltages inputs, LIN
Vref and PWM Vref. The motor current is controlled by LIN Vref and PWM Vref and the current
sense resistor Rs connected to the SENSE output. The SENSE output provides for connection of
a resistor in series with the source of all lower
DMOS drivers. The voltage at this pin provides
the error signal wich is utilized internally to regulate the motor current Im. The current in both
PWM and linear mode is determined by the expression :
Vref
Im =
GV ⋅ RS
in wich Gv is the voltage gain of the sense amplifier. In linear mode, the current is regulated by a
linear control loop wich drives the lower DMOS.
Compensation of the linear control loop is
achieved by connection of a series network
(Rc,Cc) from the transconductance amplifier output (Gm) and ground. Control is passed to each
lower DMOS in succession during the commutation sequence(MPX).
The rate at which the upper and lower drivers
turns-off during linear mode operation is configurable externally by the value of the resistor R used
at the RC pin. This defines a current which is utilized internally to limit the voltage slew-rate at the
outputs during transitions. The output slew-rate is
internally adjusted for fast slewing during PWM
operation to reduce losses, and a relatively
slower rate during linear mode operation to mini5/10
L6232E
mize noise effects(EMI). LIN Vref and PWM Vref
are connected to a comparator whose output is
fed to the logic . The upper and lower DMOS
driver slew-rates are controlled by the internal
logic.
In PWM mode, the upper driver is turned-off when
the motor current reaches the intended value. An
internal One-Shot pulse determines the lenght of
time the upper driver stays off before turning on
again. The pulse width, and thus the cutoff time
(toff), is configurable by means of the external RC
network connected to the RC pin. (see Fig. 2). The
resistor at the RC pin, therefore determines both
the driver output slew-rate during linear mode and
the off-time constant during PWM. The lower driver
is always on during PWM mode of operation; an
on-chip 2µs mask can prevent the beginning of a
new cutoff time because of transient current spikes
caused by the upper drivers turn-on.
The driving mode is determined by the smaller of
the two controlling input voltages. In a typical application the motor start-up would occur in PWM
mode to limit power dissipation, with on-speed
control then performed in linear mode.
Thermal protection circuitry will shut-off all drivers
when the chip junction temperature exceeds the
threshold temperature. A small amount of hysteresis is included to prevent rapid on/off cycling of
the power stages.
Additional protection is provided against driver input
combinations where the upper and lower drivers of
a half bridge are turned on simultaneusly, resulting
in a short from supply to ground. The chip logic will
cause both the upper and lower drivers involved to
turn-off. (see Table 1)
APPLICATION INFORMATION
A typical application configuration of the L6232E
driving a three-phase brushless DC motor is
shown in Fig.3. The spindle motor is a 4 ohm2mH per phase, star connected. This load requires a suitable compensation of the linear control loop that can be achieved by Rc= 10 Kohm
and Cc= 10nF (R3;C8). Changing the motor characteristics, the RcCc network would be modified
for the best performances of the system. At the
start-up the spindle is driven in PWM mode fixed
toff time.
The off-time is calculated by the formula :
toff = 0.69 R2 C7
See fig.2 for a quick choice of the needed capacitor, after the resistor has been fixed. The value of
the resistor defines the rate at which the upper
and lower drivers turn-off during linear mode operation to avoid EMI effects. During turn-off, the
slew rate is constant for the sink stage, while it
has a varying slope for the source stage because
of the non linear change of the gate to source impedance of the DMOS transistor. Practically, the
6/10
Figure 2: Typical toff vs. Capacity of C
slowest slew rate is obtained at the sink transistor
switch-off time (see fig. 5), then it increases during the first period of the source transistor switchoff (source,1st) and it becomes the fastest during
the final portion of the turn-off duration (source,
2nd). The PWM to linear mode of operation is
switched by decreasing the LIN Vref level under
the PWM Vref value that could be fixed and calculated by:
PWM Vref = 4 Rs Ip
where Ip is the peak chopping current in the motor windings. Of course, when the required RPM
is reached, it become of no need a strong torque
and the LIN Vref starting from a value higher than
the calculated PWM Vref, decreases to the value
:
LIN Vref = 4 Rs Im
where Im, smaller than Ip, is the needed motor current to keep constant spin. This last reference voltage is generally a PLL output driven by speed
transducers coupled to the spindle (like Hall effect
sensors or BEMF processors). To drive the upper
DMOS and during the brake function a voltage
higher than the supply Vs is needed. The charge
pump integrated in the L6232E keeps C3 at the
correct voltage. To guarantee efficient braking of
the motor , C3 must be chosen of adeguate quality
(very high equivalent parallel resistance). C4 can
be a ceramic disk capacitor . The typical application od the L6232E is in HDD systems on which
there is the need to park the Read-Write Heads before the motor braking. This behavior is possible
with the circuit of Fig.3. At Power Supply switch-off
(see Fig. 1), VP falls down and drives down the
BRK input (Active Low). D1 insulates the L6232E
from the power suppy output while the power output stage is switched in a high impedance state.
The spindle motor acting as a three-phase alternator supplies the Heads voice coil motor driven
through integrateddiodes that rectifie the EMF. After a delay longer than the parking time, the lower
output DMOS are switched-on and the spindle motor is braked. The brake delay time is tipically 150
msec and it is defined by :
L6232E
td(BRK) = 1.4 R1 C6
The sensing resistor value is generally lower
than 1ohm, but a wire wounded type must be
avoided. In Fig.3 the 0.33 ohm sensing resistor
is shown as three parallel 1ohm metal film resis-
tors. Care must be taken in the PC Board design
particularly about ground loops and ground copper area. The typical Thermal Resistance junction
to ambient versus PC Board copper area (Fig.7)
is shown in Fig 8. For Transient Thermal Resistance see Fig. 9.
Figure 3: Typical Application Circuit
Figure 4: Typical Normalized RDS (on) vs.
Junction Temperature
Figure 5: Output Voltage Slew Rate Control vs.
1/R2 Value
7/10
L6232E
Figure 6: Typical Body Diode Forward Drop vs.
Drain to Source Current.
Figure 7: On Board Dissipation Copper Area Size
Figure 8: Typical Rth j-amb vs. On-Board Heatsink
Side l.
Figure 9: Typical Transient Rth in Single Pulse
Condition.
8/10
L6232E
PLCC28 PACKAGE MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
12.32
12.57
0.485
0.495
B
11.43
11.58
0.450
0.456
D
4.2
4.57
0.165
0.180
D1
2.29
3.04
0.090
0.120
D2
0.51
E
9.91
0.020
10.92
0.390
0.430
e
1.27
0.050
e3
7.62
0.300
F
0.46
0.018
F1
0.71
0.028
G
0.101
0.004
M
1.24
0.049
M1
1.143
0.045
9/10
L6232E
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as criticalcomponents in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
 1996 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
10/10